JPH04123391A - Output buffer circuit for gate array - Google Patents

Abstract

PURPOSE:To independently generate a memory backup control signal without depending upon a gate array by providing the output buffer circuit with a means for forming an output signal with a previously determined logical level in response to an external power supply disconnection detecting signal indicating the disconnection of a power supply to a gate array circuit. CONSTITUTION:In the case of a memory backup mode in which a signal BCIN is a low level, a signal BCOUT outputs a VDD2 (high level) as a backup control signal, and in a normal operation mode, outputs a logical signal for memory access to an SRAM chip 12 in the gate array circuit. Namely when a system side power supply VDD1 is dropped and disconnected, an SRAM chip backup mode is set up, and when the VDD 1 is increased, a memory accessible mode to the SRAM chip 12 can be set up. In a memory backup mode, an SRAM chip memory backup control signal can be formed.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to a gate array output buffer 7 circuit, and more particularly to a gate array output buffer circuit suitable for use in backing up an SRAM chip.

Prior Art Conventional gate array integrated circuit devices typically use a single operating power supply. Therefore, it has the following drawbacks.

For example, in a logic circuit system using a gate array integrated circuit chip and a memory chip such as SRAM that requires backup, during normal operation, the SRA is activated by a memory access signal output from the gate array integrated circuit chip.
The M chip may be accessed, and the SRAM chip may be backed up and controlled using a predetermined logic level (high level) signal when in memory backup mode.

In such a memory backup mode, in order to fix the backup control signal from the gate array integrated circuit chip at a high level, it is necessary to keep the single power supply of the gate array integrated circuit chip on.

In memory backup mode, even though the gate array integrated circuit does not need to operate, the power to the gate array integrated circuit chip is turned on to generate a high-level control signal for memory backup. The disadvantage is that the entire array must be kept active, which is wasteful in terms of power consumption.

In addition, since the power supply during normal operation and the backup power supply are switched by a switch circuit using diodes and transistors, the voltage drop of the gate array power supply is caused by the voltage drop of the diode and transistor. Another drawback is that the operating margin of the gate array is reduced.

Therefore, it is conceivable to separately provide only a logic circuit for memory backup control outside the gate array integrated circuit chip. However, in this case, a special logic IC is required, which has the drawback of increasing the space occupied by the IC and increasing the price.

OBJECTS OF THE INVENTION An object of the present invention is to provide an output buffer circuit for a gate array that can independently generate a memory backup control signal without relying on the gate array during a memory backup mode for an SRAM.

Structure of the Invention The gate array output buffer 7 circuit according to the present invention is a gate array output buffer 7 circuit that receives the output of the gate array circuit as an input and outputs a logical output signal according to the output to the outside. It is characterized by having means for generating an output signal of a predetermined logic level in response to a power-off detection signal from the outside indicating that the power to the circuit is turned off.

Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, referring to FIG. 2, there is shown an example of a circuit that implements backup control of an SRAM by applying an embodiment of the present invention.

V DDI is the normal power supply for the gate array integrated circuit chip 10, V DD2 is the backup power supply for the SRAM chip 12, and VDD represents the power supply for the entire system.

The system power supply VDD and the voltage of the battery 14 are applied to the power supply monitoring IC chip 13, and the system power supply VDD
(-VDDI) is higher than the voltage of the battery 14, the power supply monitoring IC chip 13 changes VDDI to VDD.
If the power supply V DDI is cut off and becomes lower than the battery voltage, the battery voltage is output as V DD2.

Further, the power supply monitoring IC chip 13 generates a low level signal (BCIN) when the power supply V DDI becomes below a specified value, and generates a high level signal when it exceeds the specified value.

The backup mode of the SRAM chip 12 is switched by a C8 (chip select) control. In the backup mode, a signal of /X low level is applied, and during memory access, it can be accessed at a high level. This signal is supplied as BCOUT from the gate array integrated circuit chip 10, and the signal indicating the power monitoring result of the power monitoring IC chip 13 is supplied as BCOUT.
! N to the integrated circuit chip 10.

FIG. 3 is a specific operation time chart of the circuit shown in FIG. 2. V DDI changes from Ov to 5■, V DD2
If VDDI is lower than the battery voltage (3V in the figure),
It is the battery voltage, and when it is high, it is the voltage of VDDI.

Signal BclNl; When LVDDI 75<4.5 V or more, VDDI is used as is and becomes a /1 high level signal, indicating normal operation mode; below 4.5 V, it becomes a low level (Ov) signal, indicating memory backup mode. show.

The signal BCOUT outputs VDD2 ('\I level) when the signal BCIN is in the low level memory pick-up mode, and becomes a backup control signal.
．． In the normal operation mode of 5V or more, a logic signal for memory access to the SRAM chip 12 of the gate array circuit is output.

In other words, when the system side power supply VDDI decreases and is cut off, the SRAM chip enters the backup mode and the VDDI
When DDI rises to 74.5 V or higher, the SRAM chip enters memory access mode.

From the above, an exemplary circuit of a 10 bus sofa associated with the SRAM chip 12 of the gate array integrated circuit chip 10 is obtained as shown in FIG.

This buffer 11 has two gates 2 and an inverter (MOS) transistor 3 whose input is the output of this gate.
1 of the NOR gate 55) and a drain resistor 4)
It includes a pull-down resistor 1 that pulls down the input.

The SRAM access signal from the gate array section is applied to the pull-down input terminal of the NOR gate 2, and the signal BCIN is applied to the other input terminal of the NOR gate 2 via the inverter 5. These buffer 11 and inverter 5 are connected to the power supply V
It is operated by DD2.

In normal memory access mode, signal BC! Since N is at high level, one input of NOR gate 2 is always fixed at low level by inverter 5. Therefore, the memory access signal IN from the gate array section is output as is as the signal BCOUT by the NOR gate 2 and transistor 3.

In the memory backup mode, VDDI is disconnected and at a low level, and the output from the gate array section becomes floating, but one input of the NOR gate 2 is fixed at a low level by the pull-down resistor 1. At this time, since the signal BCIN is at a low level, the output of the -inverter 5 becomes a level of 1 (V DD2). Therefore, this high level signal is directly output as a signal BCOUT by the NOR gate 2 and transistor 3, and the memory Backup is possible.

Effects of the Invention As described above, since the operating power supply of the IO buffer cell of the gate array related to the SRAM chip can be different from the operating power supply of the gate array, the IO buffer cell can be operated in the memory backup mode. The cell makes it possible to generate a memory backup control signal for the SRAM chip, which eliminates the need to specifically provide a backup logic gate for the SRAM outside the gate array, reducing the number of external circuit ICs and lowering the price. This has the effect of making it possible to achieve low power consumption.

Further, when the system power is turned off, the output of the IO buffer cell can be used for control (shutdown control) for forcibly turning off the power of IC chips of other systems.

[Brief explanation of the drawing]

Fig. 1 is a circuit diagram of an embodiment of the present invention, Fig. 2 is a block diagram of an SRAM memory backup control system to which the circuit of Fig. 1 is applied, and Fig. 3v! J is a time chart showing the operation of the blocks in FIG. 2. Explanation of symbols of main parts 1...Pull-down resistor 2...Nor gate 12...
SRAM3...MOS transistor 10...Gate array integrated circuit chip 11...
... IO buffer cell 13 ... Power monitoring IC chip 14 ... Battery

Claims (3)

[Claims] (1) An output buffer circuit for a gate array which inputs the output of a gate array circuit and derives a logical output signal according to the output to the outside, and detects a power outage from the outside indicating a power outage of the gate array circuit. 1. An output buffer circuit for a gate array, comprising means for generating an output signal of a predetermined logic level in response to a signal. (2) a first input terminal to which the output of the gate array circuit is supplied; a second input terminal to which the power-off detection signal is supplied; means for pulling the terminal to a predetermined logic level;
2. The means for generating the output signal at a predetermined logic level when the gate array circuit is powered off receives the predetermined logic level and the logic level of the power-off detection signal as inputs. Output buffer circuit for gate array described. (3) The pulling means includes a pull-down resistor connected to the first input terminal, and the means for generating an output signal of a predetermined logic level connects the first and second input terminals to two input terminals. 3. The gate array output buffer circuit according to claim 1, comprising a NOR gate and an inverter for inverting the output of the NOR gate.