JPS5986314A - Balancing type frequency converter - Google Patents
Balancing type frequency converterInfo
- Publication number
- JPS5986314A JPS5986314A JP19533482A JP19533482A JPS5986314A JP S5986314 A JPS5986314 A JP S5986314A JP 19533482 A JP19533482 A JP 19533482A JP 19533482 A JP19533482 A JP 19533482A JP S5986314 A JPS5986314 A JP S5986314A
- Authority
- JP
- Japan
- Prior art keywords
- frequency converter
- frequency
- spurious
- hybrid
- converters
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
- H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
- H03D7/14—Balanced arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Superheterodyne Receivers (AREA)
Abstract
Description
【発明の詳細な説明】
この発明はスプリアス出力を抑圧する機能を有するバラ
ンス形周波数変換器の改良に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an improvement in a balanced frequency converter having a function of suppressing spurious output.
ダイオード等を用いた周波数変換器では２局発周波数と
人力信号周波数の混合により１次式に示す様な無数の周
波数成分を生じる。A frequency converter using a diode or the like generates countless frequency components as shown in a linear equation by mixing two local oscillation frequencies and a human signal frequency.
ｆｏｕｔ−１ｎｆＬ＋ＸｍＦ６１（１）但しｆＬ：局発
周波数、Ｆ８：入力信号周波数ｎ、ｍ＝ｏ、１，２，３
． ・・
この中でｆＬ＋Ｆ８又はＦｓ−ｆＬが各々送信周波数変
換器、受信周波数変換器の出力信号周波数成分であり、
他の周波数成分はスプリアスとなる。通常、このスプリ
アスは帯域通過ろ波器、低域通過ろ波器等のフィルタに
より充分な減衰量をカえることにより出力端には現われ
ない。fout-1nfL+XmF61 (1) where fL: local frequency, F8: input signal frequency n, m=o, 1, 2, 3
．． ... In this, fL+F8 or Fs-fL are the output signal frequency components of the transmitting frequency converter and receiving frequency converter, respectively,
Other frequency components become spurious. Normally, this spurious does not appear at the output end because a sufficient amount of attenuation is provided by a filter such as a band pass filter or a low pass filter.
しかしながら１例えばｆＬ＝ ２ ＧＨｚ 、 Ｆ８＝
６ＧＨｚの受信周波数変換器の場合、出力信号成分Ｆ８
−八−４ＧＨｚと９局発周波数の２倍波２ｆ□、−４Ｇ
Ｈｚが同一周波数となる為フィルタによりスプリアスを
抑圧することは不可能である。この様な場合。However, for example fL=2 GHz, F8=
For a 6GHz receiving frequency converter, the output signal component F8
-8-4GHz and 9th station frequency double wave 2f□, -4G
Since the Hz is the same frequency, it is impossible to suppress the spurious with a filter. In such a case.
従来は第１図に示すバランス形周波数変換器が用いられ
ている。図において、１は入力信号を分岐する１８０°
ハイブリツド、２は局発電力を分岐する同相ハイブリッ
ド、３は出力信号を合成する１８０°ハイブリ、ド、４
，５は周波数変換器である。図から明らかな如く、各々
の周波数変換器４゜５で発生する２ ｎｆ Ｌ及びｔ
ｎｆＬ±２ ｍＦ ｓ Ｉの周波数成分は出力の１８０
°ハイブリツド３に同相で入力する為、原理的には、出
力端には現われない。Conventionally, a balanced frequency converter shown in FIG. 1 has been used. In the figure, 1 is 180° where the input signal is branched.
Hybrid, 2 is an in-phase hybrid that branches local power, 3 is a 180° hybrid that combines output signals, de, 4
, 5 is a frequency converter. As is clear from the figure, 2 nf L and t generated in each frequency converter 4.5
The frequency component of nfL±2 mF s I is 180 of the output
° Since it is input to the hybrid 3 in the same phase, in principle it does not appear at the output terminal.
第２図は従来実施されている他のバランス形周波数変換
器で、６は入力９０°ハイブリ、ド、７は同相ハイブリ
ッド、８は出力９０°ハイブリットゝ、９゜１０は周波
数変換器である。この構成の場合は。FIG. 2 shows another conventionally implemented balanced frequency converter, where 6 is an input 90° hybrid, 7 is an in-phase hybrid, 8 is an output 90° hybrid, and 9° and 10 are frequency converters. For this configuration.
図の位相関係からｎｆＬ−Ｆ８１ ｎｆＬ−５Ｆ８．
ｎｆＬ−９Ｆｓ、・・が、原理的には出力端に現われな
い。From the phase relationship in the figure, nfL-F81 nfL-5F8.
nfL-9Fs, . . . does not appear at the output terminal in principle.
以上述べた従来の実施例では、原理的には、スプリアス
が出力端に現われないが、実際には各局わずかでもバラ
ツキがあり、また信号分岐・合成用のハイブリッドにも
振巾・位相差がある為、スプリアスは完全には抑圧され
ない。第３図は１両周波数変換器で生ずるスプリアス間
の振＋１］・位相のバラツキとスプリアス抑圧量の関係
を図示したものである。図から１例えば、４０ｄＢ以」
二のスプリアス抑圧量を得る為には位相・振巾のパラツ
ギを各々１°□０．１ｄＢ以内に抑える必要があるが、
これは１以上述べた各周波数変換器、・・イブリッドの
特性を考慮すると殆んど不可能な値である。In the conventional embodiment described above, in principle, spurious does not appear at the output end, but in reality there is even a slight variation in each station, and the hybrid for signal branching and combining also has amplitude and phase differences. Therefore, spurious signals are not completely suppressed. FIG. 3 illustrates the relationship between the spurious suppression amount and the amplitude +1]/phase variation between spurious signals generated in one and both frequency converters. From the figure, for example, 40 dB or more.
In order to obtain the second spurious suppression amount, it is necessary to suppress the phase and amplitude deviations within 1°□0.1dB.
This is an almost impossible value when considering the characteristics of each of the frequency converters and hybrids mentioned above.
この発明の目的は上記従来の欠点を解決したバランス形
周波数変換器を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a balanced frequency converter that solves the above-mentioned conventional drawbacks.
この発明は１以上述べたバランス形周波数変換器のスプ
リアス抑圧特性を良好に保つ為に、各周波数変換器のダ
イオードに各々独立に順方向直流バイアス電圧”Ｂ＋
’ ”Ｂ２を印加しｌ ■Ｂ１ ” ８２を調整するこ
とにより、各周波数変換器で発生するスプリアスの振巾
を合わせ出力端に現われるスプリアスを極小にしたもの
である。In order to maintain good spurious suppression characteristics of the balanced frequency converter mentioned above, this invention applies a forward DC bias voltage "B+" to each diode of each frequency converter independently.
By applying B2 and adjusting B1 82, the amplitude of the spurious generated in each frequency converter is matched and the spurious appearing at the output terminal is minimized.
第４図は本発明の１実施例の構成を示すフ゛ロック図で
ある。図において、１１は入カイ言号分岐用の１８０°
ノ・イブリッド、１２は局発電力外１賎用の同相ノ・イ
ブリバ、１３は出力信号合成用の１８０゜ハイブリッド
、１４．１５は周波数変換＠１ ＋ Ｖａ １＋■ は
各々の周波数変換器への直流ノクイアス電圧２
である。前述の如く９周波数変換器１４．１５のダイオ
ードに直流・Ｓイアスミ圧を印カロした場合。FIG. 4 is a block diagram showing the configuration of one embodiment of the present invention. In the figure, 11 is 180° for input language branching.
12 is an in-phase hybrid for use outside the local power output, 13 is a 180° hybrid for output signal synthesis, 14.15 is a frequency conversion@1 + Va 1+■ is a power supply to each frequency converter. The direct current noquious voltage is 2. As described above, when DC/Si asmium pressure is applied to the diodes of 9 frequency converters 14 and 15.
（１）式で示しだ各出力周波数成分の変換損失を変イヒ
させることが出来る。例えばＧａＡｓのショノトキタ゛
イオードの場合、順方向にノ々イアスを印カロし０．３
〜０．７ｖ程度変化させることにより、任意スジ１ノア
ス（例えば２ｆＬ）に着目して９両周波数変換器力）ら
発生する振巾を一致させることカニ出来る。一方位相は
信号線路又は局発側線路に位相調整回路を挿入し一致さ
せることが出来る。ｂａち、出力端におけるスプリアス
を完全に抑圧できる。これらの操作による信号周波数成
分に対する変換損失のイ氏下は通常１〜２ｄＢ以内に抑
えること力；出来る為。As shown in equation (1), the conversion loss of each output frequency component can be varied. For example, in the case of a GaAs short diode, a noise is applied in the forward direction and the energy is 0.3
By changing the voltage by about 0.7 V, it is possible to match the amplitudes generated from arbitrary streaks of 1 NOA (for example, 2 fL) and 9 frequency converter forces. On the other hand, the phases can be matched by inserting a phase adjustment circuit into the signal line or the local line. Furthermore, spurious signals at the output end can be completely suppressed. The conversion loss for signal frequency components caused by these operations can usually be suppressed within 1 to 2 dB.
殆んどの場合、実用上の問題を生じない。In most cases, it does not cause any practical problems.
第５図は本発明の他の一実施例の構成を示すブロック図
で、１６は入力９０°ノ・イ′リット８，１７は局発電
力の同相ノ・イブリッド、１８は出力の９０°ノ・イブ
リッド、１９．２０は周波数変換θ羽。FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention, in which 16 is an input 90° nozzle, 17 is an in-phase nozzle for local power, and 18 is an output 90° nozzle.・Ibrid, 19.20 is frequency conversion θ feather.
ｖ 、■ は直流・ぐイアスミ圧である。この場合８１
８２
も、第２図の場合のスプリアス例えばｆＬ−Ｆ８に着目
して上述と同じように・々イアスミ圧調整により、この
スゲリアスを完全に抑圧できる。v and ■ are direct current/guinea pressure. In this case 81
82 as well, this spurious can be completely suppressed by focusing on the spurious in the case of FIG.
以上の説明では各周波数変換器をシン＋′Ｉ？ルで表わ
していたが、直流・ぐイアスミ圧を印加した周波数変換
器の具体的な例を第６図、第７図に示す・第６図におい
て、２１は入力信号用帯域通過ろ波器（ＢＰＦ） 、
２２は局発用ＢＰＦ 、 ２３は出力信号、 用ＢＰＦ
、 ２４はダイオード、２５はＲＦ’チョーク回路を
有する直流バイアス線である。図では直流バイアス線２
５を局発電力印加端子より取シ出しているが、これを入
出力信号端子から取り出しても同じであることは言うま
でもない。In the above explanation, each frequency converter is syn+'I? Figures 6 and 7 show specific examples of frequency converters that apply direct current and Guiasmi pressure.In Figure 6, 21 is a band-pass filter for input signals ( BPF),
22 is BPF for local oscillator, 23 is output signal, BPF for
, 24 is a diode, and 25 is a DC bias line having an RF' choke circuit. In the figure, DC bias line 2
5 is taken out from the local power application terminal, but it goes without saying that the same effect can be obtained even if it is taken out from the input/output signal terminal.
第７図は１８０°ノ・イブリッドを用いた周波数変換器
の例で、２６は１８０°／Ｓイブリツド、２７゜２８は
ダイオード、２９．３０はＲＦチョーク回路を有する直
流バイアス線を示す。この場合は。FIG. 7 shows an example of a frequency converter using a 180°/S hybrid, where 26 is a 180°/S hybrid, 27° and 28 are diodes, and 29.30 is a DC bias line having an RF choke circuit. in this case.
直流バイアス電圧として士■８を使用し２両ダイオード
に均等にバイアスを印加している。8 is used as a DC bias voltage, and bias is applied equally to both diodes.
以上説明したように２本発明を用いれば、バランス形周
波数変換器を構成する各周波数変換器のダイオードに各
々独立に順方向直流バイアス電圧を印加諷整することに
より、各周波数変換器から発生ずるスプリアスの振ｒｉ
を一致させることが出来るため１発生スプリアスを信号
出力端で充分に抑圧する効果を発揮するものである。As explained above, if the present invention is used, a forward DC bias voltage is independently applied to the diodes of each frequency converter constituting the balanced frequency converter, and the voltage generated from each frequency converter is adjusted. Spurious vibration
Since it is possible to make them match, it is possible to sufficiently suppress the spurious generated at the signal output end.
第１図は従来のバランス形周波数変換器の１例を示すブ
ロック図、第２図は従来の他のバランス形周波数変換器
（イメージリジェクション形）のブロック図、第３図は
２つのスジリアス信号間の振巾・位相のアンバランスと
スフ０リアス抑圧量の関係を示すグラフ、第４図は本発
明によるバランス形周波数変換器の一実施例の構成を示
したブロック図 第５図は本発明による他のバランス形
層）
波数変換器（イメージリジェクション形）の一実施例の
構成を示しだブロック図、第６，７図は周波数変換器の
ダイオードへの順方向直流・ぐイアスミ圧印加方法を示
すブロック図である・１．３．１１，１３．２６・・・
１８０°ノへイブリッド、２゜７．１２．１７・・・同
相ハイブリ１．ド、４，５，９，１０゜１４．１５，１
９．２０・・・周波数変換器、６，８．１６゜１８９０
°ハイブリツド、２１，２２．２３・帯域通過ろ波器、
２４．２７．２９・・ダイオード、２５１２９．３０・
・・直流バイアス用チョーク回路。
第１図
１θ
第２図
振巾バラツキ（ｄＢ）
第３図
ＶＢ２
第４図Figure 1 is a block diagram showing an example of a conventional balanced frequency converter, Figure 2 is a block diagram of another conventional balanced frequency converter (image rejection type), and Figure 3 is a block diagram showing two streaky signals. FIG. 4 is a block diagram showing the configuration of an embodiment of the balanced frequency converter according to the present invention. FIG. Figures 6 and 7 are a block diagram showing the configuration of an embodiment of a wave number converter (image rejection type) (other balanced type layer). This is a block diagram showing 1.3.11, 13.26...
180° hybrid, 2°7.12.17...In-phase hybrid 1. Do, 4,5,9,10°14.15,1
9.20...Frequency converter, 6,8.16°1890
°Hybrid, 21, 22. 23・Band pass filter,
24.27.29...Diode, 25129.30...
...DC bias choke circuit. Fig. 1 1θ Fig. 2 Amplitude variation (dB) Fig. 3 VB2 Fig. 4
Claims (1)
のハイブリッドで分岐された各々の信号を周波数変換す
るダイオードを用いた２つの周波数変換器と、該各局波
数変換器の出力を合成した信号を出力する第２のハイブ
リッドとを有するバランス形周波数変換器に於いて、前
記各周波数変換器を構成するダイオードが、各々独立の
順方向直流バイアス電圧を印加されたダイオードである
ことを特徴とするバランス形周波数変換器。 ２ 前記第１及び第２のハイブリッドの両方とも１８０
°ハイブリツドである特許請求の範囲第１項記載のバラ
ンス形周波数変換器。 ３ 前記第１及び第２のハイブリ、ドの両方とも９０°
・・イブリッドである特許請求の範囲第１項記載のバラ
ンス形周波数変換器。[Claims] 1. A first hybrid that branches a human power signal. The first power source is driven by local power obtained from the same local power source.
A balanced frequency converter that has two frequency converters using diodes that convert the frequencies of each signal branched by the hybrid, and a second hybrid that outputs a signal that combines the outputs of the wave number converters at each station. A balanced frequency converter, wherein the diodes constituting each frequency converter are diodes to which independent forward DC bias voltages are applied. 2 Both the first and second hybrids are 180
The balanced frequency converter according to claim 1, which is a hybrid. 3. Both the first and second hybrids are at 90°.
. . . The balanced frequency converter according to claim 1, which is an hybrid.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19533482A JPS5986314A (en) | 1982-11-09 | 1982-11-09 | Balancing type frequency converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19533482A JPS5986314A (en) | 1982-11-09 | 1982-11-09 | Balancing type frequency converter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5986314A true JPS5986314A (en) | 1984-05-18 |
Family
ID=16339440
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19533482A Pending JPS5986314A (en) | 1982-11-09 | 1982-11-09 | Balancing type frequency converter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5986314A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0347761A2 (en) * | 1988-06-20 | 1989-12-27 | Hughes Aircraft Company | Local oscillator feedthru cancellation circuit and method therefor |
| US5428839A (en) * | 1993-09-07 | 1995-06-27 | Motorola, Inc. | Planar magic-tee double balanced mixer |
| US9518504B2 (en) | 2011-11-17 | 2016-12-13 | Kawasaki Jukogyo Kabushiki Kaisha | Air intake structure of engine and motorcycle having the same |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5625811A (en) * | 1979-08-09 | 1981-03-12 | Toshiba Corp | Mixer circuit |
-
1982
- 1982-11-09 JP JP19533482A patent/JPS5986314A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5625811A (en) * | 1979-08-09 | 1981-03-12 | Toshiba Corp | Mixer circuit |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0347761A2 (en) * | 1988-06-20 | 1989-12-27 | Hughes Aircraft Company | Local oscillator feedthru cancellation circuit and method therefor |
| US5428839A (en) * | 1993-09-07 | 1995-06-27 | Motorola, Inc. | Planar magic-tee double balanced mixer |
| US9518504B2 (en) | 2011-11-17 | 2016-12-13 | Kawasaki Jukogyo Kabushiki Kaisha | Air intake structure of engine and motorcycle having the same |
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