JPS5984550A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5984550A JPS5984550A JP19473582A JP19473582A JPS5984550A JP S5984550 A JPS5984550 A JP S5984550A JP 19473582 A JP19473582 A JP 19473582A JP 19473582 A JP19473582 A JP 19473582A JP S5984550 A JPS5984550 A JP S5984550A
- Authority
- JP
- Japan
- Prior art keywords
- pattern
- resist
- photo
- film
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の利用分野〕
本発明は微細パターンの加工金倉む半導体装置の製法に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a method for manufacturing a semiconductor device using fine pattern processing.
半導体装置における配線金属などの微細バターーンの加
工は主にリフトオフ法が使われている。The lift-off method is mainly used to process fine patterns such as wiring metal in semiconductor devices.
第1図は従来のリフトオフ法を説明する構造断面図で、
半導体基板(例えばG a A s等の化合物半導体基
板)1上に被着した絶縁膜2の一部にホトレジスト膜3
をマスクに穴あけ加工4して、Atなどの金属膜5を被
着した状態を示す。このあとホトレジストを溶解する溶
液にこの試料を浸漬してホトレジストヲ取去るとこの上
にあった不用の金属膜5が一諸に除去され、所望の金属
パターン6のみが形成される。従来のり7トオ7法では
ホトレジストが溶けに<<、一部分に不用の金属とホト
レジストが残ってしまう欠点があった。不用の金属を除
去するため、超音波振動などの機械的な力を利用するこ
と力tSるFAuなどのように所望の金属パターンの半
導体基板に対する密着力が弱い場合には、はがれ゛る不
良が発生して、良好にパターンを加工することが難しか
った。Figure 1 is a structural cross-sectional view explaining the conventional lift-off method.
A photoresist film 3 is formed on a part of an insulating film 2 deposited on a semiconductor substrate (for example, a compound semiconductor substrate such as GaAs) 1.
This shows a state in which a hole 4 is made in the mask and a metal film 5 made of At or the like is deposited. Thereafter, when this sample is immersed in a solution that dissolves the photoresist and the photoresist is removed, the unnecessary metal film 5 on the photoresist is completely removed, and only the desired metal pattern 6 is formed. The conventional glue 7 to 7 method had the drawback that the photoresist was easily melted, leaving unnecessary metal and photoresist in some areas. In order to remove unnecessary metal, mechanical force such as ultrasonic vibration is used. If the desired metal pattern has weak adhesion to the semiconductor substrate, such as with FAu, peeling defects may occur. This made it difficult to process a good pattern.
本発明の目的は再現性に優れたリフトオフ法を提供する
ことにある。An object of the present invention is to provide a lift-off method with excellent reproducibility.
ホトレジスト上に被着した金属層はホトレジストを溶解
させる場合に邪魔になり、特に大面積で、厚い金属層が
ホトレジスト上にある場合は除去しにくい。本発明はこ
の欠点を改良する目的で成されものである。The metal layer deposited on the photoresist becomes a nuisance when dissolving the photoresist and is difficult to remove, especially if there is a large area and a thick metal layer on the photoresist. The present invention has been made to improve this drawback.
本発明の骨子は次の通シである。 The gist of the present invention is as follows.
試料上にパターン材を形成する工程において、る材料全
均一に被着する工程と、上記、加工したパターン部を覆
うがごとくホトレジストなどからなる被覆物パターン全
役ける工程と、該被覆物パターン全マスクにして上記の
所望のパターン材となる材料の不用部分を除去する工程
と、上記、少なくとも第一層以上の贋金除去する工程に
よって、所望のパターン材を形成するものである。In the step of forming a pattern material on a sample, there is a step of uniformly applying the material to the entire surface, a step of applying a coating pattern made of photoresist or the like to cover the processed pattern portion, and a step of coating the entire pattern of the pattern material. The desired pattern material is formed by the step of removing unnecessary portions of the material that will become the desired pattern material as a mask, and the step of removing counterfeit materials from at least the first layer.
〔発明の実施例〕
以下、本発明の一実施例全第2図によシ説明する。本実
施例では、従来の第1図につづき、第2図に示す工程全
追加する。Atなどの金属膜5を被着したのち、ホトレ
ジスIf塗布して凹部全平坦化したのち、所望の金属パ
ターンを覆いかくずサイズ金もったレジスト/<ターン
7(被覆物)くターン)を加工形成する(第2図C(a
))。このレジストパターンの寸法はホトリングフイの
合せ精度(通常は±0.5μm)k見越してパターン金
覆う程度か、これ以上でよく、限定されるものでない。[Embodiment of the Invention] Hereinafter, an embodiment of the present invention will be explained with reference to FIG. In this embodiment, following the conventional process shown in FIG. 1, all the steps shown in FIG. 2 are added. After depositing a metal film 5 such as At, photoresist If is applied to flatten the entire recessed area, and the desired metal pattern is covered with a gold-rich resist/<turn 7 (coated material) turn). form (Fig. 2C(a)
)). The dimensions of this resist pattern are not limited, and may be just enough to cover the pattern gold in anticipation of the alignment accuracy of the photoring fin (usually ±0.5 .mu.m), or larger.
つづいてレジストパターン7全マスクにして金属膜5を
エツチング8.8’ してホトレジスト膜3の上面全露
出させる(第2図(b))。残在金菖層は9゜9′を符
号されている。この状態で残ったホトレジスト全除去す
れば、取去、シ易ぐ、不用な金属部9゜9′全簡単に取
去ることができる(第2図(C月。Subsequently, the metal film 5 is etched 8.8' using the entire resist pattern 7 as a mask to expose the entire upper surface of the photoresist film 3 (FIG. 2(b)). The remaining gold irises layer is marked 9°9'. If all the remaining photoresist is removed in this state, all unnecessary metal parts 9° and 9' can be easily removed (see Fig. 2 (C)).
ホトレジストの除去方法は通常のレジスト溶解液でもよ
いが、液のよごれをきらう場合には02−ガス雰囲気の
プラズマエッチによってもよく、プーロセスの余裕度は
従来のリフトオフ法に比べて著るり、<向上できた。The photoresist can be removed using a normal resist dissolving solution, but if contamination of the solution is to be avoided, plasma etching in a 02-gas atmosphere can also be used. did it.
上記、実施例では金属膜の下部材としてホトレジストヲ
用いたが、本発明ではこの下部材の表面を露出できる構
成のため、下部材として耐熱性に優れた8 102 +
S iNなどの絶縁膜を使い、オーバエツチングによ
って金属膜全除去することができ点
る。これは、Pt、Mo、Wなどの高−金属のみならず
S11 リンガラスなどの材質もリフトオフによってパ
ターン形成できる特徴がちる。また、上記の実施例で述
べた被覆物パターンの材質はホトレジストである必要が
ない。In the above examples, a photoresist was used as the lower member of the metal film, but in the present invention, since the surface of the lower member can be exposed, 8 102 +, which has excellent heat resistance, is used as the lower member.
Using an insulating film such as SiN, the entire metal film can be removed by overetching. This has the characteristic that not only high-density metals such as Pt, Mo, and W, but also materials such as S11 phosphorus glass can be patterned by lift-off. Furthermore, the material of the covering pattern described in the above embodiments does not need to be photoresist.
以上、本発明の内容を半導体装置の金属パターンの形成
、として述べたが、ジョセフソン接合デバイスなど微細
化を必要とするものに適用できることは言うに及ばない
。Although the present invention has been described above as forming a metal pattern for a semiconductor device, it goes without saying that it can be applied to devices that require miniaturization such as Josephson junction devices.
本発明によれば、リフトオフ時に、不用の金属膜のほと
んどがあらかじめ取シ除かれているので、ホトレジスト
膜と残った不用の金属膜を再現性よく除去することがで
きた。これによって、必要以上の機械的振動作業がなく
、密着力の弱いものにもリフトオフ法でパターン加工で
きるため、す7トオ7法の適用範囲を広げることができ
た。According to the present invention, since most of the unnecessary metal film is removed in advance during lift-off, the photoresist film and the remaining unnecessary metal film can be removed with good reproducibility. As a result, the range of application of the 7-to-7 method has been expanded because there is no need for excessive mechanical vibration work, and even items with weak adhesion can be patterned using the lift-off method.
第1図は従来法による半導体装置の製造工程中の一断面
図、第2図は本発明による半導体装置の製造工程を示す
断面図である。
1・・・半導体基板、2・・・絶縁膜、3・・・ホトレ
ジスト膜、4・・・開孔、5・・・金属層、6・・・金
属パターン、7・・・レジストパターン、8.8’・・
・金属膜5のエツチング部1.9,9′・・・残存金属
部。
軍 1 図
第 Z 図FIG. 1 is a cross-sectional view showing a process for manufacturing a semiconductor device according to a conventional method, and FIG. 2 is a cross-sectional view showing a process for manufacturing a semiconductor device according to the present invention. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Photoresist film, 4... Opening, 5... Metal layer, 6... Metal pattern, 7... Resist pattern, 8 .8'...
- Etched portions 1.9, 9' of metal film 5...remaining metal portions. Army 1 Figure Z
Claims (1)
なくとも第一層以上の層にパターン部を加工する工程と
、上記層や上面に所望のパターン材となる材料全均一に
被着する工程と、上記、加工したパターン部を覆うがご
とくホトレジストなどからなる被覆物パターンを設ける
工程と、該被覆物パターン全マスクにして上記の所望の
パターン材となる拐料の不用部分を除去する工程と、上
記、少なくとも第1層以上の贋金除去する工程によって
、所望のパターン材を形成すること全特徴とした半導体
装置の製法。1. In the step of forming a pattern material on a predetermined substrate, a step of processing a pattern part on at least the first layer or above, and uniformly depositing the material that will become the desired pattern material on the above layers and the upper surface. a step of providing a covering pattern made of photoresist or the like to cover the above-mentioned processed pattern portion; and a step of using the entire covering pattern as a mask to remove unnecessary portions of the stripping material that will become the desired pattern material. A method for manufacturing a semiconductor device, characterized in that a desired pattern material is formed by the step of removing counterfeit money from at least the first layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19473582A JPS5984550A (en) | 1982-11-08 | 1982-11-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP19473582A JPS5984550A (en) | 1982-11-08 | 1982-11-08 | Manufacture of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5984550A true JPS5984550A (en) | 1984-05-16 |
JPH0530054B2 JPH0530054B2 (en) | 1993-05-07 |
Family
ID=16329355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP19473582A Granted JPS5984550A (en) | 1982-11-08 | 1982-11-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5984550A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011075888A1 (en) * | 2011-05-16 | 2012-11-22 | Robert Bosch Gmbh | Semiconductor device with at least one contact and method for producing a semiconductor device with at least one contact |
-
1982
- 1982-11-08 JP JP19473582A patent/JPS5984550A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE102011075888A1 (en) * | 2011-05-16 | 2012-11-22 | Robert Bosch Gmbh | Semiconductor device with at least one contact and method for producing a semiconductor device with at least one contact |
DE102011075888B4 (en) * | 2011-05-16 | 2014-07-10 | Robert Bosch Gmbh | Semiconductor device with at least one contact and method for producing a semiconductor device with at least one contact |
US9202702B2 (en) | 2011-05-16 | 2015-12-01 | Robert Bosch Gmbh | Semiconductor device having at least one contact, and manufacturing method for a semiconductor device having at least one contact |
Also Published As
Publication number | Publication date |
---|---|
JPH0530054B2 (en) | 1993-05-07 |
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