JPS5982769A - thin film silicon transistor - Google Patents
thin film silicon transistorInfo
- Publication number
- JPS5982769A JPS5982769A JP57193812A JP19381282A JPS5982769A JP S5982769 A JPS5982769 A JP S5982769A JP 57193812 A JP57193812 A JP 57193812A JP 19381282 A JP19381282 A JP 19381282A JP S5982769 A JPS5982769 A JP S5982769A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- line
- source
- transistor
- source line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 28
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 25
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010703 silicon Substances 0.000 title claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000011159 matrix material Substances 0.000 claims description 8
- 239000004973 liquid crystal related substance Substances 0.000 abstract description 23
- 239000010408 film Substances 0.000 abstract description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 13
- 238000000034 method Methods 0.000 abstract description 9
- 238000005530 etching Methods 0.000 abstract description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 6
- 229910052814 silicon oxide Inorganic materials 0.000 abstract description 6
- 239000011521 glass Substances 0.000 abstract description 5
- 239000012535 impurity Substances 0.000 abstract description 3
- 238000001259 photo etching Methods 0.000 abstract description 2
- 238000004544 sputter deposition Methods 0.000 abstract description 2
- 238000004519 manufacturing process Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- 230000007547 defect Effects 0.000 description 5
- 238000002834 transmittance Methods 0.000 description 4
- 229910000838 Al alloy Inorganic materials 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 235000018597 common camellia Nutrition 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910003437 indium oxide Inorganic materials 0.000 description 2
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 description 2
- 240000001546 Byrsonima crassifolia Species 0.000 description 1
- 235000003197 Byrsonima crassifolia Nutrition 0.000 description 1
- 241000209507 Camellia Species 0.000 description 1
- 240000001548 Camellia japonica Species 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- MZZINWWGSYUHGU-UHFFFAOYSA-J ToTo-1 Chemical compound [I-].[I-].[I-].[I-].C12=CC=CC=C2C(C=C2N(C3=CC=CC=C3S2)C)=CC=[N+]1CCC[N+](C)(C)CCC[N+](C)(C)CCC[N+](C1=CC=CC=C11)=CC=C1C=C1N(C)C2=CC=CC=C2S1 MZZINWWGSYUHGU-UHFFFAOYSA-J 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000005484 gravity Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 229910001887 tin oxide Inorganic materials 0.000 description 1
- 239000012780 transparent material Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136259—Repairing; Defects
- G02F1/136263—Line defects
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F2202/00—Materials and properties
- G02F2202/10—Materials and properties semiconductor
- G02F2202/104—Materials and properties semiconductor poly-Si
Landscapes
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は薄膜シリコントランジスタに関するものであり
、ざらには電極配線の断線防止を目的としたものである
。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a thin film silicon transistor, and its main purpose is to prevent disconnection of electrode wiring.
近年情報化社会といわれる中で、コンピューター明達機
器の発展には目ざましいものがあり、これにともなって
表示装置においても従来からのＣＲＴにかわるものとし
て各種の平面ディスプレーの開発も盛んである。特に平
面ディスプレーでは液晶ディスプレーが低重力、低電圧
、又は受光タイプのための見易すブの面で時計電卓には
元より家電製品、自動車用パネルとしても巾広く用いら
れている。2. Description of the Related Art In recent years, in what has been called an information-oriented society, there has been a remarkable development of computer-enabled devices, and along with this, various flat displays have been actively developed as display devices to replace the conventional CRT. In particular, among flat displays, liquid crystal displays are widely used in clock calculators, home appliances, and automobile panels due to their low gravity, low voltage, or light-receiving type, making them easy to view.
又、現在ＯＦＴに替る安価だ平面ディスプレーとして注
目されているものに薄膜シリコントランジスタのアクテ
ィブマトリックスによって液晶を駆動する方式が検討さ
れている。Furthermore, as a planar display that is currently attracting attention as an inexpensive alternative to OFT, a system in which liquid crystal is driven by an active matrix of thin film silicon transistors is being considered.
これは透明基板上にスイッチング用薄膜シリコントラン
ジスタ回路をマトリックス状に形成し、この基板と他の
一方の透明ガラス板間に液晶を封入した画像表示用のデ
ィスプレーパネルである。This is a display panel for displaying images in which switching thin film silicon transistor circuits are formed in a matrix on a transparent substrate, and liquid crystal is sealed between this substrate and another transparent glass plate.
アクティブマトリックスによる液晶表示装置の画素の構
成の一例を゛第１図に示した。An example of the structure of a pixel of a liquid crystal display device using an active matrix is shown in FIG.
スイッチングトランジスタ１のゲー）！ｆｄゲートライ
ン４に、ソース１！椿はソースライン５にそれぞれ接続
これ、ドレイン電極は液晶３の駆動Ｎ椿及び、コンデン
サー２の一方の電極に接続ばれている。、り薄膜シリコ
ントランジスタを用いガラス板上にアクティブマトリッ
クスを構成した場合の一画素の構成例を示したものが第
２図の平面図である、６は薄膜シリコントランジスタの
ドレイン、チャンネル、ソースを形成する多結晶シリコ
ンであり、ゲート電極はゲートライン７に接続され、又
ソース電析はソースライン８に接続されている。夕、液
晶駆動電極９は図かられかるように薄膜シリコントラン
ジスタのドレインの多結晶シリコンを研在して設けられ
れば製造工程が簡単となる。しかるに光透過型の液晶表
示装置の場合液晶駆動１［ｉ９け、導電性を有する透明
電極でなければならないが、薄膜シリコントランジヌタ
乙の材料として用いる多結晶シリコンは、１０００λ程
度に薄くしても光を余り通さずさらに、干渉色により着
色され駆動電極として用いることは出来ない。現在導電
性の透明物質としては酸化スズ又は酸化インジウムある
いは酸化スズと酸化インジウムの合金Ｃ以下ＩＴＯとい
う）を用いるのが液晶を用いた表示装置の一般的な方法
であって、安定性、導電性、光の透過性が非常に良く、
透明電極として理想的である。Game of switching transistor 1)! Source 1 to fd gate line 4! The camellias are connected to the source line 5, and the drain electrodes are connected to the driving N camellia of the liquid crystal 3 and one electrode of the capacitor 2. The plan view in Figure 2 shows an example of the configuration of one pixel when an active matrix is constructed on a glass plate using thin film silicon transistors. 6 forms the drain, channel, and source of the thin film silicon transistor. The gate electrode is connected to a gate line 7 and the source electrode is connected to a source line 8. Finally, if the liquid crystal drive electrode 9 is provided by grinding the polycrystalline silicon of the drain of the thin film silicon transistor as shown in the figure, the manufacturing process will be simplified. However, in the case of a light-transmissive liquid crystal display device, the liquid crystal drive 1 [i9] must be a transparent electrode with conductivity, but the polycrystalline silicon used as the material for the thin film silicon transistor 2 can be thinned to about 1000λ. It does not pass much light and is colored by interference color, so it cannot be used as a drive electrode. Currently, the common method for display devices using liquid crystals is to use tin oxide, indium oxide, or an alloy of tin oxide and indium oxide (hereinafter referred to as ITO) as an electrically conductive transparent material. , very good light transmittance,
Ideal as a transparent electrode.
又ソースライン８は一般的にはアルミニウム又はシリコ
ン入りのアルミニウムが用いられているが製造工程を簡
略化するため液晶駆動電極材である工ＴＯを用い液晶駆
動電極９と同時に形成することが可能である。この場合
液晶駆動電極部は光の透過率を高めるため可能な限り薄
い工Ｔｏで形成されることが望ましいがソースラインの
配線抵抗を下げるためにはおのずと限界があり普通２０
００λ前後の膜厚が配線抵抗及び透過率の面で良いとさ
れている。又、液晶駆動電極は表示性能を向上はせる目
的からも面積を可能な限り大きくとる必要があるためソ
ースライン巾は逆にできる限り細い方向にもっていくこ
とが理想である。In addition, the source line 8 is generally made of aluminum or silicon-containing aluminum, but in order to simplify the manufacturing process, it is possible to form the source line 8 at the same time as the liquid crystal drive electrode 9 by using TO, which is a material for the liquid crystal drive electrode. be. In this case, it is desirable that the liquid crystal drive electrode part be formed of the thinnest material possible in order to increase the light transmittance, but there is a natural limit to lowering the wiring resistance of the source line, and it is usually 20.
It is said that a film thickness of around 00λ is good in terms of wiring resistance and transmittance. Further, since it is necessary to make the area of the liquid crystal drive electrode as large as possible for the purpose of improving display performance, it is ideal that the source line width is made as thin as possible.
しかしながら、第２図の如くソースライン８けゲートラ
イン７を絶縁膜を介して横ぎる構造となっておｈ％ζら
には薄膜シリコントランジスタの多結晶シリコン領域６
をも横ぎる構造となっている。しかも第３図の如くソー
スライン１２も多結晶シリコンのトランジスタ領域１１
の両者とも断面構造は段差部にて下地の絶縁膜１ｏが矢
印の如くえぐれを生じている。これは製造工程中におい
て表面清浄化を目的とする絶縁膜表面層をわずかエツチ
ング除去する工程のためであわ、この工程は品質の安定
性を確保するため必要不可欠なものである、段差部にわ
ずかなえぐれを生じた領域を薄い膜厚のソースライン１
２が横ぎる場合は第４図の如くソースライン１３が段差
部にて〈濾び状にエツチングが進行しついにはラインの
断線につながることになる。液晶表示装置において、各
画素の表示欠陥は、欠陥個所が集中しない限り、表示効
果をそれほどそこなうものではないが、前記の如くライ
ン断線は一本の線欠陥として表われ、表示効果を大きく
そこなうことになる。However, as shown in FIG. 2, the source line 8 crosses the gate line 7 via an insulating film, and the polycrystalline silicon region 6 of the thin film silicon transistor
It has a structure that crosses the Moreover, as shown in FIG. 3, the source line 12 is also made of polycrystalline silicon transistor region 11.
In both of these cross-sectional structures, the underlying insulating film 1o is hollowed out at the step portion as shown by the arrow. This is because the surface layer of the insulating film is slightly etched away for the purpose of surface cleaning during the manufacturing process, and this process is essential for ensuring quality stability. The eroded area is covered with a thin source line 1.
2 crosses over, the source line 13 is etched at the stepped portion in a "filter-like" manner, as shown in FIG. 4, which eventually leads to line breakage. In a liquid crystal display device, display defects in each pixel do not significantly impair the display effect as long as the defects are not concentrated, but as mentioned above, a line break appears as a single line defect and can greatly impair the display effect. become.
本発明はかかる従来の欠点を除去するものであ ５−
リ、ソースラインのゲートライン及び多結晶シリコント
ランジスタとの重なり領域を仙よりライン 巾を太く
することにより、ソースラインの断線を防止するもので
ある。The present invention eliminates such drawbacks of the conventional art. It is.
以下本発明を実施例をもとに詳細に説明する。The present invention will be described in detail below based on examples.
第５図は薄膜シリコントランジスタを用いたアクティブ
マトリックス液晶表示装置の本発明による製造工程を説
明するものである。FIG. 5 explains the manufacturing process of an active matrix liquid crystal display device using thin film silicon transistors according to the present invention.
第５図（ハ））ではガラス板１４の表面上に多結晶シリ
コン薄膜１５を形成し、薄膜シリコントランジスタのド
レイン轡チャンネルｅソース領域とすべき部分以外をエ
ツチング除去した時の断面を示したものである。薄膜シ
リコントランジスタのドレイン及びソース領域には高濃
度の不純物が拡散される。次に第５図（ｂ）に示される
様に多結晶シリコン薄膜１５の表面をおおってシリコン
酸化膜１６を形成する。このシリコン酸化膜は多結晶シ
リコン１５の表面を熱酸化して得たものでも、又気相反
応生長法によって得たものでも良い。さらにはシリコン
酸化膜でなく他の絶縁膜、例えばシリコ ６ −
ン空化膜アルミナ膜等でもよい。次にドレイソ領域上ノ
シリコン酸化膜１６にコンタクトホールを開孔し、ドレ
イン型棒を取り出し窓を作る。FIG. 5(c) shows a cross section when a polycrystalline silicon thin film 15 is formed on the surface of the glass plate 14 and the portions other than those to be used as the drain, channel, and source regions of a thin film silicon transistor are removed by etching. It is. Highly concentrated impurities are diffused into the drain and source regions of thin film silicon transistors. Next, as shown in FIG. 5(b), a silicon oxide film 16 is formed to cover the surface of the polycrystalline silicon thin film 15. This silicon oxide film may be obtained by thermally oxidizing the surface of polycrystalline silicon 15, or may be obtained by a vapor phase reaction growth method. Further, instead of the silicon oxide film, other insulating films such as a silicon 6-vacuum film, an alumina film, etc. may be used. Next, a contact hole is made in the silicon oxide film 16 above the drain region, and the drain type rod is taken out to form a window.
次に第５図（Ｃ）の如く、高濃変に不純物をドープした
多結晶シリコンを用いにゲートライン１７を形成後、絶
縁膜１８を基板主面全面に堆積する。Next, as shown in FIG. 5C, a gate line 17 is formed using polycrystalline silicon heavily doped with impurities, and then an insulating film 18 is deposited over the entire main surface of the substrate.
次に第５図（ｄ）の如く、基板主面上にＩＴＯ膜１７ｙ
２ｏｏｏＸ スパッタしたのちホトエツチングにて液
晶駆動電極部とソースラインを同時に形成する。Next, as shown in FIG. 5(d), an ITO film 17y is placed on the main surface of the substrate.
2oooX After sputtering, a liquid crystal drive electrode portion and a source line are formed simultaneously by photoetching.
この際前述の如くゲートライン１９及びトランジスター
領域２０の段差部には工程中のエツチング液を用いたク
リーニング工程により、矢印の如くえぐれを生じており
、そのためＩＴＯにて形成したソースライン１８の前記
えぐれ個所との交点部はわずかくさび状の横方向へのエ
ツチングが第４図と同じ様に進行しておりエツチングを
過度に行なうことによりこのくさび状のエツチングが更
に進行し、やがてラインの断線につながる。そのため本
発明においてはソースライン２２の巾をゲートライン２
３Ｅｌびトランジスタのソース領域２４との重なり部の
入館６図の如く太くすることにより仮りにエツチングが
過度に行なわれても断線が生じ難くするとともにトラン
ジスタのソース領域の段差部分２５において仮りに断線
が生じても第６図矢印の如くソース領域の周辺部２１に
て確実にラインが導通している形状とｔｌっている。な
お部分的にこの様なソース領域との断線が生じても各画
素の点欠陥としてあられれ表示性能にはさほど影響しな
い。しかしながらラインそのものが断線した場合におい
ては線状の欠陥が表示されるため表示性能が確実に低下
し製品として使用は不可能となる。At this time, as described above, the stepped portions of the gate line 19 and the transistor region 20 are gouged as shown by the arrows due to the cleaning process using an etching solution during the process, and therefore the gouges of the source line 18 formed of ITO are removed. At the intersection with the line, slightly wedge-shaped horizontal etching progresses as shown in Figure 4. If etching is performed excessively, this wedge-shaped etching progresses further, eventually leading to line breakage. . Therefore, in the present invention, the width of the source line 22 is set to the width of the gate line 2.
By making the overlapping part with the source region 24 of the transistor thicker as shown in Figure 6, even if etching is performed excessively, it is difficult to cause a disconnection, and it is also possible to prevent a disconnection from occurring at the step part 25 of the source region of the transistor. Even if this occurs, the shape is such that the line is reliably conductive at the peripheral portion 21 of the source region as shown by the arrow in FIG. Note that even if such a disconnection with the source region occurs partially, it occurs as a point defect in each pixel and does not significantly affect the display performance. However, if the line itself is broken, a linear defect will be displayed, and the display performance will definitely deteriorate, making it impossible to use the product as a product.
以上の如く本発明はソースラインの断線を防止する方法
としてゲートラインとの交点領域及びトランジスタのソ
ース領域との交点領域を第６図の如くソースライン中を
太くシ竹にソース領域との重なり部においては完全にソ
ース領域の外周部をソースラインが覆う形にて形成され
ているためソースラインの断線を確実に防止でき液晶表
示パネルの品質の向上はもとより低価格化にも大いに寄
奥するものである。As described above, the present invention provides a method for preventing disconnection of the source line, in which the intersection region with the gate line and the intersection region with the source region of the transistor are thickened in the source line and overlapped with the source region, as shown in FIG. Since the source line is formed to completely cover the outer periphery of the source region, disconnection of the source line can be reliably prevented, which not only improves the quality of LCD panels but also greatly contributes to lower prices. It is.
なお本発明の実施例においてはソースライン中をゲート
ラインとの交点領域及びトランジスタのソース領域の両
方とも線巾を広げる方式にて説明しているが、製造方式
によってはいずれか一方のみ断線が生じやすい場合も考
えられるため、必要に応じていずれか一方のみ線巾を太
くすることでもかまわない。In the embodiments of the present invention, a method is described in which the line width is widened in both the intersection region with the gate line and the source region of the transistor in the source line, but depending on the manufacturing method, disconnection may occur in only one of them. Since there may be cases where the line width is easy to use, it is possible to increase the line width of only one of them if necessary.
第７図及び第８図はその実施例の一例であり、第７図は
トランジスタのソース領域２６における外周部を完全に
覆った形状にてソースライン２７が形成これている。第
８図はゲートライン２８との重なり領域の入ソースライ
ン２９の線巾を広げたものである。FIGS. 7 and 8 show an example of the embodiment, and in FIG. 7, a source line 27 is formed in a shape that completely covers the outer periphery of the source region 26 of the transistor. In FIG. 8, the line width of the input source line 29 in the overlapping region with the gate line 28 is enlarged.
なお実施例において工ＴＯ膜厚を２０００スに設定し説
明しているが２ｏｏｏＸ程度が透過率及びライン抵抗の
面にて好ましい膜厚と考えられるが特に限定するもので
はない。又ソースラインの配線材料は工程の簡略化のた
め液晶表示型棒である工ＴＯと同一材料が好ましいが他
の配線材料例えばアル ９−
ミニラム、アルミニウム合金等でも本発明を逸脱するも
のではない。In the examples, the TO film thickness is set to 2,000 x and is described, but a film thickness of approximately 200 x is considered to be a preferable film thickness in terms of transmittance and line resistance, but is not particularly limited. Further, the wiring material of the source line is preferably the same material as the TOTO which is the liquid crystal display type bar in order to simplify the process, but other wiring materials such as aluminum alloy, aluminum alloy, etc. may be used without departing from the present invention.
なお本発明におけるソースライン１］は設計上決足され
るものでありソース領域あるいは液晶表示ｌｉｔ給の寸
度により限定されるものであってゲートラインの重なり
部の線巾もさらにはトランジスタのソース領域からのオ
ーバーラツプ量もおのずと限定範囲内にて決定これるも
のである。Note that the source line 1 in the present invention is determined by design and is limited by the size of the source region or liquid crystal display lit supply, and the line width of the overlapped portion of the gate line is also determined by the source area of the transistor. The amount of overlap from the area can also be determined within a limited range.
第１図はアクティブマトリックス液晶表示装置の１つの
画素の構成例を示したものであり、第２図は従来の薄膜
シリコントランジスタを用いたアクティブマトリックス
液晶表示装置の１つの画素のパネル上での構成例の一例
を示した平面図である。第３図は第２図の断面図である
。
第４図はソースラインがゲートライン及びトランジスタ
のソース領域とクロスする部分に発生する〈ζび状のサ
イドエッチ状態を示す平面図である。
１０−
第５図（ａ−ｄ）は本発明の薄膜シリコントラジスタの
製造工程を示す断面図である。
第６図、第７図、第８図は本発明におけるソースライン
の形状を示すためのソースラインとゲートライン及びト
ランジスタのソース領域近傍の平面図である。
１．６・・・・・・薄膜シリコントランジスタ２・・・
・・・コンデンサー
３・・・・・・液晶
４、７．１２．１７．２３．２８・・・・・・ゲートラ
イン５、８．１３．２２．２７．．２９・・・・・・ソ
ースライン９・・・・・・液晶表示電極
１０．１８・・・・・・絶縁膜
１１・・・・・・薄膜シリコントランジスタ１４・・・
・・ガラス板
１５・・・・・・多結晶シリコン薄膜
１６・・・・・・シリコン酸化膜
２０・・・・・・薄膜シリコントランジスタ２１ ・・
・・・・ンース領塚の周辺部２５・・・・・・ ソース
領域の段差部２４．２６・・・・・・ソース領域
具 上
出願人 株式会社 諏訪精工舎
第１図
第３図
第４図Figure 1 shows an example of the configuration of one pixel of an active matrix liquid crystal display device, and Figure 2 shows the configuration of one pixel on a panel of an active matrix liquid crystal display device using conventional thin film silicon transistors. It is a top view showing an example. FIG. 3 is a sectional view of FIG. 2. FIG. 4 is a plan view showing an ζ-shaped side etch state that occurs at the portion where the source line crosses the gate line and the source region of the transistor. 10- FIGS. 5(a-d) are cross-sectional views showing the manufacturing process of the thin film silicon transistor of the present invention. FIG. 6, FIG. 7, and FIG. 8 are plan views of the source line, gate line, and the vicinity of the source region of the transistor to show the shape of the source line in the present invention. 1.6 Thin film silicon transistor 2...
... Capacitor 3 ... Liquid crystal 4, 7.12.17.23.28 ... Gate line 5, 8.13.22.27. ．． 29...Source line 9...Liquid crystal display electrode 10.18...Insulating film 11...Thin film silicon transistor 14...
... Glass plate 15 ... Polycrystalline silicon thin film 16 ... Silicon oxide film 20 ... Thin film silicon transistor 21 ...
... Peripheral part of Nance territory mound 25 ... Stepped part of source region 24.26 ... Source region tool Applicant Suwa Seikosha Co., Ltd. Figure 1 Figure 3 Figure 4
Claims (1)
びゲート線からなるアクティブマトリックス基板におい
て、前Ｆスイッチング用薄膜シリコントランジスタのソ
ース領域と、ゲート線のいずれか一方夕は両方に重なり
合うデータ線の線巾は他の領域を走るデータ紳巾より広
く形成され、シカも前Ｆスイッチング用薄膜シリコント
ランジスタのソース領域上を走るソース線はソース領域
長端の周辺をも被覆して形成されていることを特徴とす
る薄膜シリコントランジスタ。In an active matrix substrate consisting of a thin film silicon transistor for switching, a source line, and a gate line, the line width of the data line that overlaps either the source region of the front F switching thin film silicon transistor or the gate line or both is the same as that of the other region. The thin film silicon is characterized in that the source line running above the source region of the thin film silicon transistor for F switching is formed to cover the periphery of the long end of the source region. transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57193812A JPS5982769A (en) | 1982-11-04 | 1982-11-04 | thin film silicon transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57193812A JPS5982769A (en) | 1982-11-04 | 1982-11-04 | thin film silicon transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5982769A true JPS5982769A (en) | 1984-05-12 |
Family
ID=16314169
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57193812A Pending JPS5982769A (en) | 1982-11-04 | 1982-11-04 | thin film silicon transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5982769A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60236266A (en) * | 1984-05-10 | 1985-11-25 | Matsushita Electric Ind Co Ltd | semiconductor equipment |
| JPS63222443A (en) * | 1987-03-11 | 1988-09-16 | Alps Electric Co Ltd | Thin film transistor matrix array |
| US5075674A (en) * | 1987-11-19 | 1991-12-24 | Sharp Kabushiki Kaisha | Active matrix substrate for liquid crystal display |
| EP0488802A2 (en) * | 1990-11-30 | 1992-06-03 | Sharp Kabushiki Kaisha | An active matrix display device |
| US5276540A (en) * | 1990-11-30 | 1994-01-04 | Sharp Kabushiki Kaisha | Active matrix substrate with conductive film covering transparent conductive film portion connecting additional and non-additional capacitance portions of pixel electrode |
-
1982
- 1982-11-04 JP JP57193812A patent/JPS5982769A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60236266A (en) * | 1984-05-10 | 1985-11-25 | Matsushita Electric Ind Co Ltd | semiconductor equipment |
| JPS63222443A (en) * | 1987-03-11 | 1988-09-16 | Alps Electric Co Ltd | Thin film transistor matrix array |
| US5075674A (en) * | 1987-11-19 | 1991-12-24 | Sharp Kabushiki Kaisha | Active matrix substrate for liquid crystal display |
| EP0488802A2 (en) * | 1990-11-30 | 1992-06-03 | Sharp Kabushiki Kaisha | An active matrix display device |
| US5276540A (en) * | 1990-11-30 | 1994-01-04 | Sharp Kabushiki Kaisha | Active matrix substrate with conductive film covering transparent conductive film portion connecting additional and non-additional capacitance portions of pixel electrode |
| US5287206A (en) * | 1990-11-30 | 1994-02-15 | Sharp Kabushiki Kaisha | Active matrix display device |
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