JPS5981586A - Reference signal generating circuit - Google Patents

Abstract

PURPOSE:To generate a reference signal with a constant period at low cost from the segment driving signal of a digital timepiece LSI through simple circuit constitution by providing two delay circuits, two exclusive OR circuits, and an OR circuit which ORs the output of those two exclusive OR circuits. CONSTITUTION:The segment driving signal a1 is passed through a delay circuit DL10 and further passed through a waveform shaping circuit HS10, to obtain an output a1'. Then, an exclusive OR gate EX1 ORs the segment driving signal a1 and output a1' exclusively to obtain an output a1'' synchronizing with the rising and falling of the segment driving signal a1. Similarly, the segment driving signal e1 is passed through a delay circuit DL11 and further passed through the waveform shaping circuit HS11 to generate an output e1'. An exclusive OR gate EX2 ORs the segment driving signal e1 and output e1' to obtain an output e1 synchronizing with the rise and fall of the segment driving signal e1; and an OR gate OR2 ORs the outputs a1'' and e1'' to obtain a reference signal (o) with a one-minute period.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reference signal generation circuit for a timepiece.

Magnetic reversal display watches display the time by reversing each segment of a segmented time display.
In order to change the display content at regular intervals, it is safe to erase the display before the digit whose display content should be changed and display the next display content, but the driver VJ circuit requires a fluorescent display tube, an invented diode, etc. A general-purpose digital device that drives the segment-type display unit! LSI for digital clocks: When used, such LSIs for digital clocks can only receive segment drive signals, and the standard for each fixed period of time (for example, 1 minute) to clear the display. In order to obtain the signal, another reference signal generation circuit was added to the digital clock LSI.

This reference signal generation circuit detects changes in the segment drive signal of the digital clock LSI.For example, in order to obtain a reference signal every minute, the digital clock LSI
Least significant digit (1 minute digit) of SI segment drive signal
It is created based on the segment drive numbers 0 to 9 of the signal.

Hereinafter, a conventional example of this reference key code generating circuit will be explained in detail.

FIG. 1 shows a seven-segment display for one-minute digits consisting of seven segments, with symbols 31 to 31 adjacent to each segment.
gl indicates a segment drive signal that drives the corresponding segment. As shown in FIG.
When OJ is displayed, segment drive signal a1
~f1 is "H".

Also, when 1-IJ-'ki is indicated, the segment drive signal b1. C1 is 1-HJ. r2J
-r9J, is displayed in Figure 2 (C1~(J
)1 The segment drive signal shown here is at the "H" level.

As shown in FIG. 3, the reference signal generation circuit that detects the changes in the segment drive signals ① to gl, which change once every minute in a 10-minute cycle, is configured to have segment drive signals a 1 - f as shown in FIG. By taking the logical product of 1, only during the period when the 7-segment display is displaying ``0'', the output will be A or l'J as shown in Figure 4.
And similarly, the AND gate AN whose output B-J becomes "H-1" only during the period when "1" to "9." are displayed.
1 to AN9 and output A of AND gate ANQ to AN9
・Delay circuits DLo to DL that each delay J by a certain period of time
9, waveform shaping circuit 1 H8Q to H89 that shapes the outputs of delay circuits DLo to DLo into rL waveforms, respectively, and AND gate ANQ 5-How to output ANo J3 and waveform shaping circuit f
(By taking the logical product with the output of S
'~AN9' and this AND gate 0'~AtJg'
The reference signal K every minute is obtained by logically adding the outputs A' to J' of
It consists of an or gate OR1 which has a remaining life. In addition,
Delay circuits DLo to DL9 and waveform shaping circuits H8O to H89
and and gate 0' ~, IVNg' is ant game 1
- A differentiation circuit that differentiates the outputs A-J of ANO to AN9 will be configured.

However, such a conventional reference signal generation circuit has a circuit configuration for obtaining a reference signal K every minute or an emergency number (return).
Konaro was the most expensive in IL (there was a deaf problem).

The purpose of this invention is to provide a reference signal creation circuit that can create a constant synchronization reference signal from the segment drive signal of an inexpensive digital clock LSI with a small circuit configuration. be.

The present invention utilizes segment F i, , 7, f signals a1 . , 1o of el
When looking at the changes in the minute numbers (changes from 0 to 9), as shown in Figure 5, the segment numbers (
No. 111 a, e □ must be on at least one side.
By noting that the rising edge of F has changed, and by detecting the rising and falling edges of this segment dove-like ′, rj′a - “It is something that exists.

An embodiment of the present invention will be explained with reference to FIGS.
(Output a1' is obtained from S1o, and segment drive signal a1 and output a1 are obtained from exclusive or game 1/EX.
' Output a synchronized with the rising and falling edges of segment drive signal a1
Similarly, one segment drive signal e1 is passed through the delay circuit DLII, and further passed through the waveform shaping circuit H8111 to obtain an output e' from the waveform shaping circuit H8, and the segment drive signal e1 is driven by the exclusive OR gate EX2. By taking the exclusive OR of the signal e1 and the output e1', an output e]7 synchronized with the rise and fall of the segment dry 1 signal e1 is obtained, and the OR gate OR2
By calculating the logical sum of the outputs a1-'el-, a standard (signature 0) of a period of 1 minute is obtained from the OR gate OR2.

As a result of this configuration, digital IL/clock LSI
From this, it is possible to create a reference signal 0 with a period of 1 minute using a circuit configuration that is simpler and cheaper than the one shown in FIG.

Next, 24
Magnetic reversal time display clock @Figure 8 (Al-(D)
, will be explained based on FIGS. 9 and 10. This magnetic reversal type display clock consists of a display drive circuit section I, a reference signal generation circuit section U,
Coil application/rest time setting circuit section (and 1 when digital)
It is composed of an LSI IV for "1", a monitor display element V, a "0" detection circuit section vI, and an instant reversal type display element (not shown).

In the display drive circuit section 1, C0a1 to COg□ and C0a2 to Co62 are coils of magnetic reversal type display elements of the 1 minute digit, C0a2 to C0g2 and Cσa1 to C(j6
2 is the same coil for <10 minutes, coa3 to co63 and CCfe, 3 to Cσ83 is the same coil for the 1 o'clock position, C0a4 to C0g4 and C, ~C (J'g, is 1
It is carp M in the 0 o'clock digit. TR engineering ~ Oldly, each coil C (J'a1 ~ C (L□, C sail, ~Cσ62゜C
Shizuku, ~CO'g3. This is a transistor that commonly controls energization to CCya4 to CCya4. TRal-TR6□
1 is a transistor that individually controls the current supply to the coil 7 and COa□ to C0g1, and the segment drive signals a1 to g1 of the digital clock LSI IV are input to the base. T.R.
A2 to TRg2 are transistors that individually control the energization of the coils C0a2 to Co62, and the segment drive<W number a2 to g2 is input to the base. TRa3~TR
g3 is coil C0a3 le C0g3 heno through ridge individually system 0
Segment drive signals a3 to g3 are input to the base of the TJ transistor. TI< ,,~TR64
1t] This is a transistor that individually controls the energization to IjL'coa and IjL'coa, and the segment drive signals f, a4 to g, are input to the base. FF2 to FF4 are flip-flops, AN11 to AN13 are AND gates, 0
1d3 to OR5 are OR gates.

The reference signal generation circuit section ■ has the same configuration as shown in Fig. 6 and generates the segment drive signals al and e of LSI IV for digital clock.
l is input.

In the coil application/rest time setting circuit section 1llI, Z
is power-on clear circuit, FF is Frilip Flora 7
°, O20 is an astable multivibrator, I) FF1
O3 and I') FF2 is D flip-prop, AN'1
4 is an AND gate, OR6, OR7 is an OR gate, NO
The NOR gate, IN1 is the inverter, and TR5 is the transistor, SW.

SW2 is a mode switching switch.

The LSIIV for digital clocks is a general-purpose one with an output of 7
and each (row segment drive signal a~gl, a2~
Output gz+ a3 to g3, 34 to g4. SW3
, SW4 HaRt11 combination switch, Nate.

"0" (In the yellow output circuit, AN, 5 to AN2o are AND gates, IN2 to IN are inverters, I)L□
2~I) L12 is a delay circuit, IN5~IN・/ are inverters for waveform shaping, and LS IIV for digital clock.
The segment drive signals d1 to a3. gl to g3 are being input.

Next, the operation of this electrically reversible display timepiece will be explained with reference to FIGS. 9 and 10.

When the power is turned on and the power-on clear is performed, the output PC instantaneously becomes l'HJ from the 1st path Z, and 1 minute later, the reference signal 0 of the first output is output from the reference signal generation circuit section ■. , B, and the output of the Flino Flops 7FF becomes "L", and the astable multivibrator O5C starts emitting one output, generating the output C1ock, and this output C1ock becomes the D Flino Flop I) FF. The DFF2+ input will be disconnected. In this case, the output Cl0Ck has an rHJ period of '■'1 and an "L" period of T27'. T of C: L is [1j[ when the coil 7 is applied, and T2 is static IjT, + Terama.

I) FF "Flop" DFFl, I) FF2 have the outputs Q, Q2. After the 2nd fixed buffless is output as the output C1ock,
Age-) Rear 1. from NOl. Tobals a is output,
Orgame 1-Frilip Flora 1FF1 via OR6
is reset and floated, and the astable multi-channel pipebrator O8C
The oscillation stops, frisso ° flo, 7 ° FF2 ~ FF,
will also be reset.

In other words, when the first reference signal 0 is generated, the AND gate AN14 outputs a pulse ifi! Buffless b of T1 is output, transistor 'rR, of 1 minute digit becomes 2r, and one coil 7+zC (Ya□~Ccf6
□When power is turned off for all 1 unit, the 1 minute digit display is erased.

-, after erasing, T2 period has passed and the output 62 of D Friso Aflori 7゛1) FF2 becomes 1-LJ, and the subsequent T controller 1 period 1 ■ 1 top resistor TR5 turns on and power is supplied to point X. The segment drive signals a1 to f1 of the segment drive signals al''gl for one minute (row) of the digital clock LSIIV become rHJ, and the transistors 71'Ra1 to 1'Rg.

11. is turned on, and the coil C01 and C0f1 that drive the 1 minute digit segment of the magnetic reversal type display element are energized.11.
The 1 minute digit is displayed as 10.

0:00 minutes should be displayed one minute after the power-on clear, and the 1.0 minute digit and 1 o'clock digit should also be erased and displayed as 9.

Here, the "0" detection circuit (ii) will be explained with reference to FIG. Segment dry 1 signals d1 to d3. g1~
If you check the voltage level for each number displayed on g3, it will be as shown in the figure [
This will happen. Therefore, segment drive signal d~d
3 and the inverted outputs of segment drives @g-g3 are passed through AND gates AN15-HA7, respectively, and the outputs c-e of AND gates AN15-AN1rl become as shown in the diagram.1. AND GATE A-N15~AN
17, respectively, when the single display is "0" as shown in the figure/
</Res C' to e' will remain for the rest of their lives. In other words, the output e (when the first minute digit is ``0-'' is rHJ, the output d is ``-H'' when the tenth digit is 10, and the output C is 1 o'clock digit is 10. ”, it becomes rHJ,
Pulses C' to e' are obtained by differentiating the outputs C to e.

Since it is 0:00 immediately after power-on clearing, at this time, pretend 1. )70・sol'FF2~FF, output is 1
It says ゛H. Therefore, after one minute has passed after power-on clear, the buffless width Tl is determined by the AND gate ANL4.
When the pulse b is output, as mentioned above, the transistor TR turns on and the transistors TR0 and AN11 to AN13 turn on and the transistor TR0 turns on.
~TR3 has also become a member and has a magnetic reversal type display element for 10 o'clock, 1 o'clock and 10 minute digits.
．． C sail 3 ~ Cσ3. C, to C, is energized, 10
The display of the hour, 1 o'clock and 10 minute digits are respectively erased. After that, the output υ2 of D-Furirif "Flo-Tsub DFF2"
When becomes I'LJ, transistor TR5 turns on and >'x
The power is supplied to one point X, and the segment drive signals for each digit are a~f1. a2~f2pa3~f3 i from transistor'■゛I<a1~TR,0,TRa2~
TRf2. TRa3 to TRf3 are turned on, and each digit of Coi/l/COa□ to COf□, C0a2 to cof2.
C0a3 to C0f3 are energized, and the magnetic reversal type display element becomes C, which indicates oHo o minutes. However, is the 10 o'clock digit segmented =? Since the 7f signal is not input, it remains unerased.

Thereafter, each time the reference signal 0 is outputted from the reference signal generating circuit (2), the display of the 1-minute digit becomes 11-dimensional by the same operation. However, the 1f\f and 10th digits remain unchanged.

Next, with the display showing 0:09, the reference signal 0 and 1 are input from the code creation circuit (■), but the 1 minute digit operates in the same way as Ail, and from 19. It changes to "0". Also, since the 1-minute digit is 1-Oji, /< /res e' force S@ is generated from l-Oj G output circuit ■, and as a result, the Frino Afro knob FF4's Output power (IH
j, the AND gate AN13 is turned on, and the 10-minute digit display changes from 10-1 to "1".

Next, when the display is 0 verses 59 minutes and the manual input is 1 minute σ) digit 1l-9J power reading 1
0", and the display changed to 10 pus. From 1, "0" detection port l bribe ν1 to 1< Lus d', e'ka~
Occurs, fly 1, 7° float, knob FF2. FF, 3
The output of becomes 1-HJ, and the AND gate AN12,
AN l:S is turned on and the 10 minute line is displayed.
The display power of the 1 o'clock digit becomes "1".

When changing from 9:59 7 ha to 10:00 OO minutes and 1
When changing from 9:59 to 20:00, change from 0 to 20:00.
"/<jres C' to e' are generated from the detection circuit (2), and the display is changed by the same operation.

The same applies when changing from 23:59 to 00:00 minutes.

When adjusting the time, set the mode switch SW1 and SW2 to the time setting mode, prohibit the power supply to the Only the display of the element is erased, and the time setting switch and the switch rSW3. The time is set using SW4 while controlling the monitor display element V. I was afraid to use the digital clock LSI while adjusting the time.
/ segment drive signal a~g], 132~g2
133~g3+a4~g4 changes, but the display of the magnetic reversal display element remains erased.

This magnetic reversal type display clock erases the display on the magnetic reversal type display element while setting the time. ; Since it is possible to hold 11 times, there is no possibility of incorrect display. In other words, the followability of the reversing mechanism of the magnetic reversal type display element is extremely poor compared to fluorescent display tubes and light emitting diodes, and the fast-forward Ga for time adjustment from general-purpose digital watch LSIIV cannot follow it at all, causing errors. Is there a problem with displaying or is it possible to solve such a problem?

As described above, the reference signal generation circuit of the present invention provides a first segment drive signal that delays for a certain period the first segment drive signal that is output from the digital V clock integrated circuit that drives the seven-segment display and drives the upper horizontal piece segment. 1 delay circuit, and a first Ex! which takes the exclusive OR of the first segment drive signal and the output of the first delay circuit.
The output from the digital clock collector M circuit outputs the lower left vertical segment to V.
1! a second delay circuit that delays a second segment drive signal for a predetermined period of time; and the exclusive OR circuit of n
Since it is equipped with an OR circuit that takes the logical OR of the output of the OR circuit, it can be used as a segment drive for clock LSIs by a simple four-way I4 configuration. This has the advantage that a reference signal with a constant period can be created from the signal.

[Brief explanation of the drawing]

@Figure 1 is a configuration diagram of the segment display element, Figure 2 +A1~
(Jl is an explanatory diagram showing the display status from O to 9, 3rd and 1st
is a circuit diagram of a conventional reference signal generation circuit, FIG. 4 is a waveform diagram of each part thereof, FIG. 5 is a waveform diagram for explaining the principle of this invention, and No. 6 (2) is a circuit of a simple embodiment of this invention. Figure 7 is a waveform diagram of each part, Figure 8 (A1-[Dl is a circuit diagram of a la air layer inversion type display clock with a built-in reference signal generation circuit of the embodiment, Figures 9 and 10 are its circuit diagrams). It is a waveform diagram of each part. DLlo, DLll-delay circuit, H8l09H5II
-Waveform shaping circuit, EXI, EX2... Exclusive Mair gate, OR2... Or gate A el L HL HL HL HL H Fig. 5 Fig. 7 - α Hi

Claims (1)

[Claims] The first signal is output from the digital clock integrated circuit that drives the 7-segment display and moves the H side horizontal R segment.
a first delay circuit that delays the segment drive signal of 11↑ for a certain period of time;
[Note: A first exclusive-OR circuit that takes the exclusive OR of the outputs of the delay circuits in 1, and a second exclusive-OR circuit that outputs from the digital clock integrated circuit and drives the left-hand clock segment. a second delay circuit that delays the drive signal for a certain period of time; and a second exclusive OR circuit that takes the exclusive OR of the output of the second segment drive signal and the second delay circuit. and an OR circuit that takes the logical sum of the outputs of the first and second ExM-Sive OR circuits.