CN115428064B - Dot matrix display device and timer - Google Patents

Abstract

The dot matrix display device (1) disclosed in the present invention comprises a display unit (3), a conversion circuit (5) and a control circuit (6). The display unit comprises a plurality of gate signal lines (31), a plurality of source signal lines (32) and a plurality of pixel circuits (33) arranged corresponding to the intersections of the plurality of gate signal lines and the plurality of source signal lines. The conversion circuit synchronously acquires a serial signal (SI) inputted from the outside to a serial state and a first clock signal (SCK) inputted from the outside, and converts the acquired serial signal into a parallel signal, the serial signal comprising address data for determining a pixel circuit for rewriting image data and image data supplied to the pixel circuit. The control circuit generates a control signal for controlling the timing of the serial-parallel conversion of the conversion circuit based on a second clock signal (ENB_V) having a frequency lower than that of the first clock signal.

Description

Dot matrix display device and timing device

Technical Field

The present disclosure relates to a dot matrix display device and a timing device using the dot matrix display device.

Background Art

Conventionally, for example, a dot matrix display device described in Patent Document 1 is known.

Prior Art Literature

Patent Literature

Patent Document 1: Japanese Patent Application Publication No. 2015-87437

Summary of the invention

The dot matrix display device disclosed in the present invention comprises:

A display unit having: a plurality of gate signal lines extending in a first direction; a plurality of source signal lines extending in a second direction intersecting the first direction; and a plurality of pixel circuits arranged corresponding to intersections of the plurality of gate signal lines and the plurality of source signal lines;

a conversion circuit that acquires a serial signal input from the outside via a serial interface in synchronization with a first clock signal input from the outside, and converts the acquired serial signal into a parallel signal, the serial signal including address data for specifying a pixel circuit for rewriting image data and the image data supplied to the pixel circuit; and

The control circuit generates a control signal for controlling the timing of serial-to-parallel conversion of the conversion circuit based on a second clock signal having a frequency lower than that of the first clock signal.

The timekeeping device of the present disclosure is a timekeeping device including the dot matrix display device of the present disclosure, and has a configuration including an elapsed time control unit that controls the minimum unit of elapsed time.

BRIEF DESCRIPTION OF THE DRAWINGS

The objects, features and advantages of the present invention will become more apparent from the following detailed description and accompanying drawings.

FIG. 1 is a circuit block diagram showing an example of the structure of a dot matrix display device according to the present disclosure.

FIG. 2 is a part of a timing chart for explaining the overall operation of the dot matrix display device of FIG. 1 .

FIG. 3 is a circuit diagram showing an example of the configuration of a pixel circuit in the dot matrix display device of FIG. 1 .

FIG. 4 is a circuit diagram showing an example of the configuration of a frequency dividing circuit in the dot matrix display device of FIG. 1 .

FIG. 5A is a circuit diagram showing an example of a configuration of a control circuit in the dot matrix display device of FIG. 1 .

FIG. 5B is a circuit diagram showing an example of a configuration of a control circuit in the dot matrix display device of FIG. 1 .

FIG. 5C is a circuit diagram showing an example of a configuration of a control circuit in the dot matrix display device of FIG. 1 .

FIG. 6A is a circuit diagram showing an example of the configuration of a conversion circuit in the dot matrix display device of FIG. 1 .

FIG. 6B is a circuit diagram showing an example of the configuration of a conversion circuit in the dot matrix display device of FIG. 1 .

FIG. 6C is a circuit diagram showing an example of the configuration of a conversion circuit in the dot matrix display device of FIG. 1 .

FIG. 7A is a circuit diagram showing an example of the configuration of a conversion circuit in the dot matrix display device of FIG. 1 .

FIG. 7B is a circuit diagram showing an example of the configuration of a conversion circuit in the dot matrix display device of FIG. 1 .

FIG. 7C is a circuit diagram showing an example of the configuration of a conversion circuit in the dot matrix display device of FIG. 1 .

FIG. 8 is a circuit diagram showing an example of the configuration of a decoder circuit in the dot matrix display device of FIG. 1 .

FIG. 9A is a circuit diagram showing an example of a configuration of a driver circuit in the dot matrix display device of FIG. 1 .

FIG. 9B is a circuit diagram showing an example of the configuration of a driver circuit in the dot matrix display device of FIG. 1 .

FIG. 10 is a part of a timing chart for explaining the operation of a counter circuit in the dot matrix display device of FIG. 1 .

FIG. 11 is a schematic front view of a timepiece device including the dot matrix display device of FIG. 1 .

DETAILED DESCRIPTION

The structure based on the dot matrix display device involved in the embodiment of the present disclosure is described. The dot matrix display device described in Patent Document 1 includes a plurality of pixel units, which are arranged corresponding to a plurality of gate signal lines, a plurality of source signal lines, and a plurality of intersections of the gate signal lines and the source signal lines, and each has a storage circuit. Such a dot matrix display device performs a rewrite drive for rewriting image data for a pixel unit selected based on the gate signal lines and the source signal lines, and performs a still image drive using the image data stored in the storage circuit for a non-selected pixel unit.

In the conventional dot matrix display device, the address data for selecting the pixel unit to perform the rewrite drive and the image data supplied to the selected pixel unit are input in series. Therefore, the transmission time of the address data and the image data becomes longer, and sometimes the operation becomes slower. In addition, in the conventional dot matrix display device, when the clock frequency is increased in order to shorten the transmission time, the control circuit controlling the rewrite drive is difficult to follow the high-speed clock frequency, and therefore sometimes cannot operate normally.

Hereinafter, the embodiment of the dot matrix display device of the present disclosure will be described with reference to the accompanying drawings. The figures referred to below show the main components of the dot matrix display device involved in the embodiment of the present disclosure. Therefore, the dot matrix display device involved in the embodiment of the present disclosure may also have known structures such as a circuit substrate, wiring conductors, control IC, LSI, etc. which are not shown in the figure.

FIG. 1 is a circuit block diagram showing an example of the structure of a dot matrix display device involved in the present disclosure, and FIG. 2 is a part of a timing diagram for explaining the overall operation of the dot matrix display device of FIG. 1 . FIG. 3 is a circuit diagram showing an example of the structure of a pixel circuit in the dot matrix display device of FIG. 1 , and FIG. 4 is a circuit diagram showing an example of the structure of a frequency division circuit in the dot matrix display device of FIG. 1 . FIG. 5A to 5C are circuit diagrams showing an example of the structure of a control circuit in the dot matrix display device of FIG. 1 , and FIG. 6A to 6C and FIG. 7A to 7C are circuit diagrams showing an example of the structure of a conversion circuit in the dot matrix display device of FIG. 1 , and FIG. 8 is a circuit diagram showing an example of the structure of a decoder circuit in the dot matrix display device of FIG. 1 , and FIG. 9A and FIG. 9B are circuit diagrams showing an example of the structure of a driver circuit in the dot matrix display device of FIG. 10 is a part of a timing diagram for explaining the operation of a counter circuit in the dot matrix display device of FIG. 1 . Hereinafter, a case where a dot matrix display device has 65536 dots (256×256 dots) of pixels will be described, but the number of pixels of the dot matrix display device is arbitrary. In addition, hereinafter, a pixel circuit configured to perform black and white display will be described, but the pixel circuit can be configured to perform grayscale display or full color display.

The dot matrix display device 1 of the present embodiment may include a display unit 3 , a frequency division circuit 4 , a conversion circuit 5 , and a control circuit 6 .

The display unit 3 is disposed on one main surface of the substrate 2. The substrate 2 is, for example, a transparent or opaque glass substrate, a plastic substrate, a ceramic substrate, etc. The substrate 2 may have a shape such as a polygonal plate such as a rectangular plate, a circular plate, an elliptical plate, or other shapes.

The display unit 3 includes a plurality of gate signal lines 31, a plurality of source signal lines 32, and a plurality of pixel circuits 33. The plurality of gate signal lines 31 are arranged in a first direction (e.g., a row direction), and the plurality of source signal lines 32 are arranged in a second direction (e.g., a column direction) intersecting the first direction. The plurality of pixel circuits 33 are arranged in a matrix corresponding to the intersections of the plurality of gate signal lines 31 and the plurality of source signal lines 32.

The image data in the plurality of pixel circuits 33 is rewritten, i.e., one or more pixel circuits 33 to be rewritten and driven are selected based on address data input from an external signal supply device (not shown). The image data is rewritten for the selected one or more pixel circuits 33. New image data used for rewriting is input from the signal supply device. For the pixel circuits 33 that are not selected, still image driving using the image data held in the pixel circuits 33 is performed.

3, each pixel circuit 33 includes a write switch circuit 331, a latch circuit 332, a pixel potential generating circuit 333, and a liquid crystal element 334. The liquid crystal element 334 includes a pixel electrode 334a, a liquid crystal 334b, and a counter electrode 334c.

The write switch circuit 331 has a thin film transistor (TFT) element. The TFT element has a semiconductor film composed of, for example, amorphous silicon (a-Si), low-temperature polysilicon (LTPS), a gate electrode, a source electrode, and a drain electrode. The gate electrode is connected to one of the plurality of gate signal lines 31, and the source electrode is connected to one of the plurality of source signal lines 32. The drain electrode is connected to the input terminal of the latch circuit 332.

The latch circuit 332 is, for example, as shown in FIG3 , composed of a static random access memory (SRAM) formed by connecting a first CMOS (Complementary Metal Oxide Semiconductor) inverter 332a and a second CMOS inverter 332b in a ring shape. The latch circuit 332 connects the first CMOS inverter 332a and the second CMOS inverter 332b in series, so that the output from the drain common connection point of the second CMOS inverter 332b is fed back to the gate common connection point of the first CMOS inverter 332a. Thus, when a high-level signal (hereinafter, also referred to as an H signal) is input to the gate common connection point of the first CMOS inverter 332a, a low-level signal (hereinafter, also referred to as an L signal) is output from the drain common connection point of the first CMOS inverter 332a. When the L signal from the first CMOS inverter 332a is input to the gate common connection point of the second CMOS inverter 332b, an H signal is output from the drain common connection point of the second CMOS inverter 332b, and the H signal is fed back to the gate common connection point of the first CMOS inverter 332a. As a result, the "H, L, H" signal is always maintained on the ring-shaped transmission line.

For example, as shown in FIG. 3 , the pixel potential generating circuit 333 is composed of an exclusive OR (EXOR) logic gate circuit. The pixel potential generating circuit 333 has two input terminals, and the write data signal SIG held in the latch circuit 332 is input to one input terminal, and the common voltage VCOM supplied from the external device is input to the other input terminal. The common voltage VCOM can also periodically invert the voltage of the H (high) level (for example, 3V) and the voltage of the L (low) level (for example, 0V). For example, when the write data signal SIG held in the latch circuit 332 is an L signal, a potential difference is generated between the voltage of the opposing electrode 334c and the pixel electrode 334a, and if it is a normally white mode, it becomes a black display, and if it is a normally black mode, it becomes a white display. In addition, when the write data signal SIG held in the latch circuit 332 is an H signal, no potential difference is generated between the voltage of the opposing electrode 334c and the pixel electrode 334a, and if it is a normally white mode, it becomes a white display, and if it is a normally black mode, it becomes a black display. In such driving of the pixel circuit 33, even when the common voltage VCOM is driven in reverse phase, the potential difference between the voltage of the counter electrode 334c and the pixel electrode 334a can be maintained, so the pixel circuit 33 can be AC driven while maintaining the image display in the pixel circuit 33. Thus, the degradation of the liquid crystal 334b of the pixel circuit 33 can be suppressed.

When rewriting the image display in the pixel circuit 33, the write switch circuit 331 is turned on. That is, the H signal is supplied to the gate signal line 31, and the image data signal is supplied to the source signal line 32. The image data signal supplied to the source signal line 32 is transmitted to the latch circuit 332 and held in the latch circuit 332. As a result, the potential difference between the voltage of the counter electrode 334c and the pixel electrode 334a changes according to the image data signal. For example, when the image data signal is an L signal, if it is a normally white mode, it becomes a black display, and if it is a normally black mode, it becomes a white display. When the image data signal is an H signal, if it is a normally white mode, it becomes a white display, and if it is a normally black mode, it becomes a black display.

The pixel circuit 33 may also be configured such that the latch circuit 332 holds a plurality of bits. In this case, the pixel circuit 33 can perform grayscale display. In addition, the pixel circuit 33 may also be configured to include a sub-pixel circuit for performing red grayscale display, a sub-pixel circuit for performing green grayscale display, and a sub-pixel circuit for performing blue grayscale display. In this case, the pixel circuit 33 can perform full-color display.

In the dot matrix display device 1, rewriting drive in the display unit 3 can be performed for each pixel circuit 33 connected to one gate signal line 31, and still image drive can be performed for the other pixel circuits 33. Therefore, the dot matrix display device 1 has low power consumption.

For example, as shown in FIG4 , the frequency division circuit 4 divides the shift clock signal SCLK (hereinafter, also referred to as the first clock signal) input from the signal supply device to generate a clock signal (hereinafter, also referred to as the second clock signal) DIV_CLK having a lower frequency than the first clock signal SCLK. The signal supply device generates the first clock signal SCLK based on the image signal, synchronization signal, clock signal, etc. input from an external device such as a TV receiver or a personal computer, and outputs it to the dot matrix display device 1. In addition, the signal supply device generates the serial signal SI and the chip selection signal SCS described later, and outputs these signals to the dot matrix display device 1.

The dot matrix display device 1 of this embodiment may also include a clock frequency control unit for controlling the frequency of the first clock signal SCLK. In this case, it is easy to increase the frequency of the first clock signal SCLK. The clock frequency control unit may also be included in the above-mentioned signal supply device, or may be provided separately from the signal supply device. In addition, the clock frequency control unit may also be program software stored in the RAM (Random Access Memory) or ROM (Read Only Memory) of a driving element such as an IC (Integrated Circuit) or an LSI (Large Scale Integrated Circuit), or may be a frequency control circuit formed on a circuit substrate, etc.

In addition, the dot matrix display device 1 of this embodiment divides the first clock signal SCLK by the frequency dividing circuit 4 to generate a second clock signal DIV_CLK having a lower frequency than the first clock signal SCLK, but is not limited to this structure. For example, it may also include: a first clock signal generating unit that generates the first clock signal SCLK; and a second clock signal generating unit that is separately provided from the first clock signal generating unit to generate the second clock signal DIV_CLK. In this case, the frequency of the first clock signal SCLK and the frequency of the second clock signal DIV_CLK can be controlled more accurately.

For example, as shown in FIG4 , the frequency division circuit 4 includes a trigger circuit 41 and an inverter circuit 42. The trigger circuit 41 has a D terminal, a CK terminal, a Q terminal, and an XRST terminal. The first clock signal SCLK is supplied to the CK terminal. The input terminal of the inverter circuit 42 is connected to the Q terminal, and the output terminal of the inverter circuit 42 is connected to the D terminal. In addition, the chip selection signal SCS is supplied to the XRST terminal. The chip selection signal SCS is a signal that becomes an H (high) level when the display unit 3 is rewritten and driven. According to the frequency division circuit 4, the frequency of the second clock signal DIV_CLK output from the Q terminal becomes half of the frequency of the first clock signal SCLK. In addition, the frequency division number of the frequency division circuit 4 is arbitrary. For example, the frequency division circuit can divide the first clock signal SCLK by 3, 4, or n (n is an integer greater than 2). The higher the frequency of the first clock signal SCLK, the greater the value of n.

The conversion circuit 5 acquires the serial signal SI input from the signal supply device in synchronization with the first clock signal SCLK. The serial signal SI is input from the signal supply device to the conversion circuit 5 via the serial interface. The conversion circuit 5 converts the acquired serial signal SI into a parallel signal.

In the present embodiment, for example, as shown in FIG. 2 , the serial signal SI includes address data A0 to A7 (in the case of collective reference, simply recorded as “A”) and image data D0 to D255 (in the case of collective reference, simply recorded as “D”). The address data A0 to A7 is data for specifying (i.e., selecting) one or more pixel circuits 33 among a plurality of pixel circuits 33 for rewriting image data. The image data D0 to D255 is data indicating an image to be displayed by the one or more pixel circuits 33 selected.

The serial signal SI may include dummy data DM not used for rewriting driving. In the present embodiment, as shown in FIG. 2 , for example, the serial signal SI includes dummy data DM0 to DM31 (when collectively referred to, simply described as “DM”).

The serial signal SI is transmitted to the conversion circuit 5 in synchronization with the first clock signal SCLK. For example, as shown in FIG2 , the serial signal SI may transmit address data A0 to A7 with the first 8 clocks, transmit image data D0 to D255 with the next 256 clocks, and then transmit dummy data DM0 to DM31 with the next 32 clocks.

In this case, the transmission period of the dummy data DM can be utilized for the rewrite execution period of the rewrite drive, etc., which is conducive to high speed. That is, the transmission period of the dummy data DM can also be the activation period of the gate signal GATE supplied to the gate signal line 31 based on the gate signal GATE of the address data A, and the activation period of the source signal supplied to the source signal line 32 based on the source signal of the image data D.

The transmission period of the dummy data DM may be equal to or less than the total transmission period of the address data A and the transmission period of the image data D. In this case, it is advantageous to increase the speed. The transmission period of the dummy data DM may be greater than 0.5 times and less than 1 times the total transmission period of the address data A and the transmission period of the image data D, but is not limited to this range.

In addition, the transmission period of the dummy data DM may be equal to or shorter than at least one of the transmission period of the address data A and the transmission period of the image data D. In this case, it is advantageous to increase the speed. The transmission period of the dummy data DM may be 0.7 times or more and 1 times or less than at least one of the transmission period of the address data A and the transmission period of the image data D, but is not limited to this range.

In addition, the transmission period of the dummy data DM may be equal to or shorter than the shorter one of the transmission period of the address data A and the transmission period of the image data D. In this case, it is advantageous to increase the speed. The transmission period of the dummy data DM may be 0.7 times or more and 1 times or less than the shorter one of the transmission period of the address data A and the transmission period of the image data D, but is not limited to this range.

The control circuit 6 controls the rewriting drive of the display unit 3. The control circuit 6 operates in synchronization with the second clock signal DIV_CLK. The control circuit 6 generates a control signal for controlling the serial-parallel (serial-to-parallel) conversion in the conversion circuit 5, and in particular, a control signal for controlling the timing of the serial-parallel conversion in the conversion circuit 5.

The control circuit 6 includes a counter circuit (counting circuit) 61 , a vertical control circuit 62 , and a horizontal control circuit 63 .

The counter circuit 61 operates synchronously with the second clock signal DIV_CLK to generate a counter signal (count signal) CNT[8:0]. The counter signal CNT[8:0] is a signal obtained by counting the number of rising edges of the second clock signal DIV_CLK, which is a pulse signal. The counter signal CNT[8:0] is used to generate a control signal for controlling the serial-parallel conversion performed by the conversion circuit 5.

The counter circuit 61 includes a plurality of combinational logic circuits 611 and a plurality of flip-flop circuits 612 in the case of a synchronous counter circuit as shown in FIG. 5A , for example.

The combinational logic circuit 611 is composed of a plurality of logic gate circuits. In addition, each flip-flop circuit 612 has a D terminal, a Q terminal, a CK terminal, and an XRST terminal. Each flip-flop circuit 612 outputs each bit of the counter signal CNT[8:0] (CNT0 to CNT8 shown in FIG. 5A ) from the Q terminal. Each bit of the next counter signal NEXT_CNT[8:0] generated by the combinational logic circuit 611 based on the counter signal CNT[8:0] is input to the D terminal (NEXT_CNT0 to NEXT_CNT8 shown in FIG. 5A ). The second clock signal DIV_CLK is input to the CK terminal, and the chip select signal SCS is input to the XRST terminal.

Usually, a combinational logic circuit is a circuit that does not have a feedback loop consisting of logic gates that calculate basic logic functions such as NOT, AND, OR, and wiring that connects them. A combinational logic circuit has several inputs and outputs (usually one), and each input value and output value takes a value of 0 or 1. Each output value is uniquely determined only by the combination of input values. That is, the combinational logic circuit calculates a logic function. Any logic function can be expressed by a product-sum formula. Therefore, it is possible to use each logic gate of NOT, AND, and OR and implement any logic function through a combinational circuit of NOT-AND-OR. Such a circuit is usually called an AND-OR two-level combinational logic circuit, but as the number of levels of the logic circuit increases, the operating speed will slow down, so the combinational logic circuit 611 is likely to become the speed limiter of the upper limit frequency of the first clock signal SCLK (in the past, about 1.5MHz).

The vertical control circuit 62 generates a vertical start pulse signal SRIN_V and a gate activation signal ENB_V based on the counter signal CNT[8:0] output from the counter circuit 61. The vertical start pulse signal SRIN_V is a start signal of a shift register that generates an acquisition timing signal for address data A0 to A7. The vertical start pulse signal SRIN_V is activated corresponding to the front end of the address data A. In addition, in this specification, "signal activation" means that the signal becomes an on state (i.e., H (high) state), and "signal inactivation" means that the signal becomes an off state (i.e., L (low) state). The gate activation signal ENB_V is a signal that determines the activation period of the gate signal GATE supplied to the gate signal line 31. The gate activation signal ENB_V is activated when the dummy data DM is transmitted after the address data A and the image data D are transmitted.

For example, as shown in Figure 5B, the vertical control circuit 62 includes a combinational logic circuit 621, a trigger circuit 622, a first single-shot pulse circuit 623, a second single-shot pulse circuit 624, a third single-shot pulse circuit 625, an OR logic gate circuit (hereinafter also referred to as an OR circuit) 626 and an RS latch circuit 627.

The combinational logic circuit 621 is configured to include a plurality of logic gate circuits and generates a first control signal CS1 based on the counter signal CNT[8:0] generated by the counter circuit 61 and outputs the first control signal CS1 to the flip-flop circuit 622 .

The flip-flop circuit 622 has a D terminal, a Q terminal, a CK terminal, and an XRST terminal. The first control signal CS1 generated by the combinational logic circuit 621 is input to the D terminal. The second clock signal DIV_CLK is input to the CK terminal. The chip select signal SCS is input to the XRST terminal. The Q terminal is connected to the first single-shot pulse circuit 623. The flip-flop circuit 622 keeps the first control signal CS1 at the rising edge of the second clock signal DIV_CLK, and outputs the first control signal CS1 to the first single-shot pulse circuit 623.

The first one-shot pulse circuit 623 includes a delay circuit and an AND logic gate circuit, and generates a first trigger signal TS1 in response to a rising edge of the first control signal CS1 outputted from the flip-flop circuit 622 , and outputs the first trigger signal TS1 to the OR circuit 626 .

The second one-shot pulse circuit 624 includes a delay circuit and an AND logic gate circuit, and generates a second trigger signal TS2 in response to a rising edge of the chip selection signal SCS, and outputs the second trigger signal TS2 to the OR circuit 626 .

The third one-shot pulse circuit 625 includes a delay circuit and a NOR logic gate circuit. The third one-shot pulse circuit 625 generates a third trigger signal TS3 in response to a falling edge of the second clock signal DIV_CLK, and outputs the third trigger signal TS3 to the RS latch circuit 627 .

The OR circuit 626 performs an OR operation on the first trigger signal TS1 output from the first one-shot pulse circuit 623 and the second trigger signal TS2 output from the second one-shot pulse circuit 624 , and outputs the result to the RS latch circuit 627 .

The RS latch circuit 627 has an S terminal, an R terminal, and a Q terminal. The OR of the first trigger signal TS1 and the second trigger signal TS2 output from the OR circuit 626 is input to the S terminal. The third trigger signal TS3 output from the third single-shot pulse circuit 625 is input to the R terminal. The RS latch circuit 627 outputs the vertical start pulse signal SRIN_V from the Q terminal. The operation of the RS latch circuit 627 is well known. For example, when the RS latch circuit 627 inputs an L signal to the S terminal and an H signal to the R terminal, as long as the L signal as the vertical start pulse signal SRIN_V is output from the Q terminal, and the signal input to the S terminal or the R terminal does not transition, or the S terminal or the R terminal is input with an L signal, the output state is maintained. In addition, when the RS latch circuit inputs an H signal to the S terminal and an L signal to the R terminal, as long as the H signal as the vertical start pulse signal SRIN_V is output from the Q terminal, and the signal input to the S terminal or the R terminal does not transition, or the S terminal or the R terminal is input with an L signal, the output state is maintained.

For example, as shown in FIG. 5B , the vertical control circuit 62 includes a combinational logic circuit 628 and a flip-flop circuit 629 .

The combinatorial logic circuit 628 includes a plurality of logic gate circuits and generates a second control signal CS2 based on the counter signal CNT[8:0] generated by the counter circuit 61 , and outputs the second control signal CS2 to the flip-flop circuit 629 .

The trigger circuit 629 has a D terminal, a Q terminal, a CK terminal, and an XRST terminal. The second control signal CS2 generated by the combinational logic circuit 628 is input to the D terminal. The second clock signal DIV_CLK is input to the CK terminal. The chip select signal SCS is input to the XRST terminal. The trigger circuit 629 outputs the gate activation signal ENB_V from the Q terminal. The trigger circuit 629 keeps the second control signal CS2 at the rising edge of the second clock signal DIV_CLK, and outputs the second control signal CS2 as the gate activation signal ENB_V.

For example, as shown in FIG. 5C , the horizontal control circuit 63 includes a combinational logic circuit 631 , a flip-flop circuit 632 , a fourth one-shot pulse circuit 633 , a fifth one-shot pulse circuit 634 , and an RS latch circuit 635 .

The combinational logic circuit 631 includes a plurality of logic gate circuits and generates a third control signal CS3 based on the counter signal CNT[8:0] generated by the counter circuit 61 , and outputs the third control signal CS3 to the flip-flop circuit 632 .

The flip-flop circuit 632 has a D terminal, a Q terminal, a CK terminal, and an XRST terminal. The third control signal CS3 generated by the combinational logic circuit 631 is input to the D terminal. The second clock signal DIV_CLK is input to the CK terminal. The chip select signal SCS is input to the XRST terminal. The Q terminal is connected to the fourth single-shot pulse circuit 633. The flip-flop circuit 632 keeps the third control signal CS3 at the rising edge of the second clock signal DIV_CLK, and inputs the third control signal CS3 to the fourth single-shot pulse circuit 633.

The fourth one-shot pulse circuit 633 includes a delay circuit and an AND logic gate circuit, and generates a fourth trigger signal TS4 in response to a rising edge of the third control signal CS3 outputted from the flip-flop circuit 632 , and outputs the fourth trigger signal TS4 to the RS latch circuit 635 .

The fifth one-shot pulse circuit 634 includes a delay circuit and a NOR logic gate circuit. The fifth one-shot pulse circuit 634 generates a fifth trigger signal TS5 in response to a falling edge of the chip selection signal SCS, and outputs the fifth trigger signal TS5 to the RS latch circuit 635 .

The RS latch circuit 635 has an S terminal, an R terminal, and a Q terminal. The fourth trigger signal TS4 output from the fourth single-shot pulse circuit 633 is input to the S terminal. The fifth trigger signal TS5 output from the fifth single-shot pulse circuit 634 is input to the R terminal. The RS latch circuit 635 outputs a horizontal start pulse signal SRIN_H from the Q terminal. The operation of the RS latch circuit 635 is well known. For example, when the RS latch circuit 635 inputs an L signal to the S terminal and an H signal to the R terminal, as long as an L signal as the horizontal start pulse signal SRIN_H is output from the Q terminal, and the signal input to the S terminal or the R terminal does not transition, or the S terminal or the R terminal is input with an L signal, the output state is maintained. In addition, when the RS latch circuit inputs an H signal to the S terminal and an L signal to the R terminal, as long as an H signal as the horizontal start pulse signal SRIN_H is output from the Q terminal, and the signal input to the S terminal or the R terminal does not transition, or the S terminal or the R terminal is input with an L signal, the output state is maintained.

For example, as shown in FIG. 5C , the horizontal control circuit 63 includes a combinational logic circuit 636 and a flip-flop circuit 637 .

The combinational logic circuit 636 includes a plurality of logic gate circuits and generates a fourth control signal CS4 based on the counter signal CNT[8:0] generated by the counter circuit 61 , and outputs the fourth control signal CS4 to the flip-flop circuit 637 .

The flip-flop circuit 637 has a D terminal, a Q terminal, a CK terminal, and an XRST terminal. The fourth control signal CS4 generated by the combinational logic circuit 636 is input to the D terminal. The second clock signal DIV_CLK is input to the CK terminal. The chip select signal SCS is input to the XRST terminal. The flip-flop circuit 637 outputs the data activation signal ENB_H from the Q terminal. The flip-flop circuit 637 keeps the fourth control signal CS4 at the rising edge of the second clock signal DIV_CLK, and outputs the fourth control signal CS4 as the data activation signal ENB_H.

Next, an example of the circuit configuration of the conversion circuit 5 in the dot matrix display device 1 of the present embodiment will be described. The conversion circuit 5 includes a vertical conversion circuit 51 and a horizontal conversion circuit 55 .

The vertical conversion circuit 51 performs parallel conversion on the address data A0 to A7 included in the serial signal SI based on the vertical start pulse signal SRIN_V output from the vertical control circuit 62. For example, as shown in FIG.

The shift register circuit 52 operates in synchronization with the first clock signal SCLK. The vertical start pulse signal SRIN_V output from the vertical control circuit 62 is input to the shift register circuit 52 .

For example, as shown in FIG6A , the shift register circuit 52 includes a plurality of stages of trigger circuits 521 connected in series. The plurality of trigger circuits 521 each have a D terminal, a CK terminal, and a Q terminal. The first clock signal SCLK is input to the CK terminal. The vertical start pulse signal SRIN_V output from the vertical control circuit 62 is input to the D terminal of the trigger circuit 521 of the first stage. The plurality of trigger circuits 521 each output vertical shift signals SRV1 to SRVn (in the case of a general term, simply recorded as “SRV”). Here, n is a positive integer determined according to the number of gate signal lines 31. In the present embodiment, n=8. The Q terminal of the trigger circuit 521 of the previous stage is connected to the D terminal of the trigger circuit 521 of the second stage and thereafter. The Q terminals of the plurality of trigger circuits 521 are respectively connected to a plurality of latch activation signal circuits 53.

For example, as shown in FIG. 1 , the multi-stage flip-flop circuit 521 is connected to a plurality of latch activation signal circuits 53 , respectively, and the plurality of latch activation signal circuits 53 is connected to a plurality of latch circuits 54 , respectively.

For example, as shown in FIG6B , the plurality of latch activation signal circuits 53 each include an inverter circuit 531 and a NAND logic gate circuit (hereinafter, also referred to as a NAND circuit) 532. The NAND circuit 532 has two input terminals, and the vertical shift signal SRV output from the flip-flop circuit 521 is input to one input terminal, and the first clock signal SCLK inverted by the inverter circuit 531 is input to the other input terminal. The plurality of latch activation signal circuits 53 each output vertical latch activation signals LTV1 to LTVn (when collectively referred to, simply recorded as "LTV") to the plurality of latch circuits 54.

The plurality of latch circuits 54 respectively have a D terminal, a CK terminal, and a Q terminal, and the vertical latch activation signal LTV output from the latch activation signal circuit 53 connected to the latch circuit 54 is input to the CK terminal. In addition, the serial signal SI supplied from the signal supply device is input to the D terminal. The plurality of latch circuits 54 respectively obtain the address data A0 to A7 included in the serial signal SI during the period when the latch activation signal LTV is an H signal, and maintain the period when the latch activation signal LTV is an L signal. For example, as shown in FIG2 , the plurality of latch circuits 54 respectively output the address data A0 to A7 as the address signals GS0 to GS7 from the Q terminal. In addition, in FIG2 , only the address data A0 output as GS0 and the address data A7 output as GS7 are shown. In GS0 and GS7 shown in FIG2 , the area marked with hatched lines indicates a state that can be either a high level or a low level.

The dot matrix display device 1 includes a decoder circuit 7 and a driver circuit 8. The driver circuit 8 includes a vertical driver circuit 81 and a horizontal driver circuit 82.

The decoder circuit 7 decodes the address signals GS0 to GS7 output from the vertical conversion circuit 51 based on the gate activation signal ENB_V output from the control circuit 6, and generates address decoding signals DEC1 to DEC256 (in the case of a general term, simply recorded as "DEC") for selecting any one of the plurality of gate signal lines 31. The address decoding signal DEC output from the decoder circuit 7 is input to the vertical driver circuit 81.

For example, as shown in FIG8 , the decoder circuit 7 has a plurality of NOR logic gate circuits (hereinafter, also referred to as NOR circuits) 71. In the present embodiment, the decoder circuit 7 has the same number of NOR circuits 71 as the number of gate signal lines 31 (256), and each NOR circuit 71 has 8 input terminals. Each NOR circuit 71 outputs an H signal when all input signals are L signals, and outputs an L signal when at least one of the input signals is an H signal.

Eight signals out of 16 signals composed of the address signals GS0 to GS7 output from the vertical conversion circuit 51 and the inverted signals XGS0 to XGS7 of the address signals GS0 to GS7 are input to each NOR circuit 71. Eight signals of different combinations are input to each of the plurality of NOR circuits 71. There are 2 ⁸ = 256 combinations of eight different signals selected from the 16 signals of the address signals GS0 to GS7 and the inverted signals XGS0 to XGS7. Therefore, by the eight signals input to the decoder circuit 7, an H signal can be output from one of the plurality of NOR circuits 71, and an L signal can be output from the other NOR circuits 71. In the present embodiment, for example, as shown in FIG. 8 , k (k is an integer greater than or equal to 0 and less than or equal to 8) inverter circuits 72 are arranged at the front stage of the eight input terminals of each NOR circuit 71, so that the address signal GS is inverted. For one of the plurality of NOR circuits 71, the inverter circuit 72 is not arranged, and the address signal GS is directly input.

The vertical driver circuit 81 is arranged at the subsequent stage of the decoder circuit 7. For example, as shown in FIG9A, the vertical driver circuit 81 includes a plurality of AND logic gate circuits (hereinafter, also referred to as AND circuits) 811, and the plurality of AND circuits 811 are arranged at the subsequent stages of the plurality of NOR circuits 71 of the decoder circuit 7, respectively.

Each AND circuit 811 has two input terminals, one of which is input with an address decoding signal DEC output from a NOR circuit 71 connected to the AND circuit 811, and the other of which is input with a gate activation signal ENB_V output from the control circuit 6. The output terminals of the plurality of AND circuits 811 are connected to the plurality of gate signal lines 31, respectively.

For example, as shown in FIG9A , a buffer circuit 812 may be configured between a plurality of AND circuits 811 and a plurality of gate signal lines 31. Each AND circuit 811 outputs an H signal when both the address decoding signal DEC and the gate activation signal ENB_V are H signals, and outputs an L signal when at least one of the address decoding signal DEC and the gate activation signal ENB_V is an L signal. For example, as shown in FIG2 , when the gate activation signal ENB_V is activated (is an H signal), the vertical driver circuit 81 can output a gate signal GATE for activating one of the plurality of gate signal lines 31.

In the vertical driver circuit 81 shown in FIG. 9A , an AND circuit 811 is formed of a NAND logic gate circuit and an inverter circuit for inverting the output of the logic gate circuit, thereby suppressing an increase in circuit scale.

The horizontal conversion circuit 55 performs parallel conversion on the image data D0 to D255 included in the serial signal SI based on the horizontal start pulse signal SRIN_H output from the horizontal control circuit 63. For example, as shown in FIG. 7A , the horizontal conversion circuit 55 includes a shift register circuit 56, a plurality of latch activation signal circuits 57, and a plurality of latch circuits 58.

The shift register circuit 56 operates in synchronization with the first clock signal SCLK. The horizontal start pulse signal SRIN_H output from the horizontal control circuit 63 is input to the shift register circuit 56 .

For example, as shown in Fig. 7A, the shift register circuit 56 includes a plurality of stages of flip-flop circuits 561 connected in series. In addition, for example, as shown in Fig. 1, the plurality of stages of flip-flop circuits 561 are connected to a plurality of latch activation signal circuits 57, respectively, and the plurality of latch activation signal circuits 57 are connected to a plurality of latch circuits 58, respectively.

The multi-stage trigger circuits 561 of the shift register circuit 56 respectively have a D terminal, a CK terminal and a Q terminal. The first clock signal SCLK is input to the CK terminal. The horizontal start pulse signal SRIN_H output from the horizontal control circuit 63 is input to the D terminal of the first-stage trigger circuit 561. The multi-stage trigger circuits 561 respectively output horizontal shift signals SRH1 to SRHm (in the case of a general term, simply recorded as "SRH"). Here, m is a positive integer equal to the number of source signal lines 32. In the present embodiment, m=256. The Q terminal of the previous stage trigger circuit 561 is connected to the D terminal of the trigger circuit 561 after the second stage. The Q terminals of the multi-stage trigger circuits 561 are respectively connected to multiple latch activation signal circuits 57.

For example, as shown in FIG7B , the plurality of latch activation signal circuits 57 each include an inverter circuit 571 and a NAND logic gate circuit (hereinafter, also referred to as a NAND circuit) 572. The NAND circuit 572 has two input terminals, and the horizontal shift signal SRH output from the flip-flop circuit 561 is input to one input terminal, and the first clock signal SCLK inverted by the inverter circuit 571 is input to the other input terminal. The plurality of latch activation signal circuits 57 each output horizontal latch activation signals LTH1 to LTHm (in the case of collective reference, simply recorded as "LTH") to the plurality of latch circuits 58.

The plurality of latch circuits 58 respectively have a D terminal, a CK terminal, and a Q terminal, and a horizontal latch activation signal LTH outputted from a latch activation signal circuit 57 connected to the latch circuit 58 is inputted to the CK terminal. In addition, a serial signal SI supplied from a signal supply device is inputted to the D terminal. The plurality of latch circuits 58 respectively obtain image data D0 to D255 included in the serial signal SI during a period when the latch activation signal LTH is an H signal, and maintain a period when the latch activation signal LTH is an L signal. For example, as shown in FIG. 2 , the plurality of latch circuits 58 respectively output image data D0 to D255 as data signals DATA1 to DATA256 from the O terminal. In addition, in FIG. 2 , only the image data D0 outputted as DATA1 and the image data D255 outputted as DATA256 are shown. In DATA1 and DATA256 shown in FIG. 2 , the hatched area indicates a state that can be either a high level or a low level.

The horizontal driver circuit 82 is arranged at the subsequent stage of the horizontal conversion circuit 55. For example, as shown in FIG9B, the horizontal driver circuit 82 includes a plurality of AND logic gate circuits (hereinafter, also referred to as AND circuits) 821, and the plurality of AND circuits 821 are arranged at the subsequent stages of the plurality of latch circuits 58 of the horizontal conversion circuit 55, respectively.

Each AND circuit 821 has two input terminals, one of which is input with a data signal DATA output from a latch circuit 58 connected to the AND circuit 821, and the other of which is input with a data activation signal ENB_H output from the control circuit 6. The output terminals of the plurality of AND circuits 821 are connected to the plurality of source signal lines 32, respectively.

For example, as shown in FIG9B , a buffer circuit 822 may be configured between a plurality of AND circuits 821 and a plurality of source signal lines 32. Each AND circuit 821 outputs an H signal when both the data signal DATA and the data activation signal ENB_H are H signals, and outputs an L signal when at least one of the data signal DATA and the data activation signal ENB_H is an L signal. For example, as shown in FIG2 , when the data activation signal ENB_H is activated (is an H signal), the horizontal driver circuit 82 can output write data signals SIG1 to SIG256 (in the case of collective reference, simply recorded as "SIG") to the plurality of source signal lines 32.

In the horizontal driver circuit shown in FIG. 9B , an AND circuit 821 is formed of a NAND logic gate circuit and an inverter circuit for inverting the output of the logic gate circuit, thereby suppressing an increase in circuit scale.

In the dot matrix display device 1 of the present embodiment, the control circuit 6, in particular the counter circuit 61, operates synchronously with the second clock signal DIV_CLK obtained by dividing the first clock signal SCLK by 2. The counter circuit 61 includes a combinational logic circuit 611 (described in FIG. 5A ) that specifies its operating speed. Therefore, the delay time T_delay in the counter circuit 61 does not depend on the clock period T2 of the second clock signal DIV_CLK, but is determined only by the circuit structure of the counter circuit 61. That is, in the past, the combinational logic circuit 611 in the counter circuit 61 became the speed limiter of the upper limit frequency of the first clock signal SCLK. For example, in the past, the upper limit frequency of the first clock signal SCLK was about 1.5MHz, and it was difficult to make the frequency of the first clock signal SCLK faster than about 1.5MHz. Therefore, the inventors thought that even if the frequency of the first clock signal SCLK is increased in speed, it is sufficient to make the counter circuit 61 operate at the same frequency as before. In order for the counter circuit 61 to operate normally in synchronization with the second clock signal DIV_CLK, it is necessary to satisfy the condition that the delay time T_delay from the reception of the counter signal CNT[8:0] to the generation of the next counter signal NEXT_CNT[8:0] of the combinational logic circuit 611 is less than the clock period T2. According to this condition, the minimum value T2_min of the clock period T2 can be determined. In the dot matrix display device 1 of the present embodiment, for example, as shown in FIG. 10, it can be set to T_delay≤T2_min. Since the second clock signal DIV_CLK is a signal obtained by dividing the first clock signal SCLK by 2, the first clock signal SCLK can speed up the minimum value T1_min of the clock period T1 to T_delay/2. For example, the frequency of the first clock signal SCLK can be set to about 3.0MHz, and the frequency of the second clock signal DIV_CLK can be set to about 1.5MHz.

In previous dot-matrix display devices, the counter circuit operates in synchronization with an external clock signal (equivalent to the first clock signal SCLK) supplied from an external device. Therefore, in order for the counter circuit to operate normally, the minimum value of the period of the external clock signal is equal to the delay time of the counter circuit.

It can be seen from this that in the dot matrix display device 1 of the present embodiment, the frequency of the first clock signal SCLK can be doubled compared to the conventional dot matrix display device. According to the dot matrix display device 1 of the present embodiment, the frequency of the first clock signal SCLK can be increased, so that the transmission time of the serial signal SI can be shortened, and the display control can be accelerated.

In addition, in the dot matrix display device 1 of the present embodiment, the vertical conversion circuit 51 generates the address signal GS as a parallel signal based on the vertical start pulse signal SRIN_V and the address data A included in the serial signal SI input in series. Therefore, it is possible to simplify the wiring structure for inputting the address data A from the outside. In addition, since the vertical conversion circuit 51 converts the serially input address data A into the address signal GS as a parallel signal and outputs it, it is possible to maintain the transmission time of the address signal GS short.

The decoder circuit 7 generates address decoding signals DEC1 to DEC256 supplied to a plurality of (256) gate signal lines 31 based on the address signals GS0 to GS7. Thus, the plurality of gate signal lines 31 can be driven by address signals GS0 to GS7, which are less in number than the number of gate signal lines 31. Therefore, the wiring structure for inputting address data A from the outside can be simplified, and the circuit scale of the vertical conversion circuit 51 can be reduced.

The timing device disclosed in the present invention is a timing device having the dot matrix display device 1 disclosed in the present invention, and is a structure having a time control unit that controls the minimum unit of elapsed time. According to this structure, since the dot matrix display device 1 disclosed in the present invention is capable of high-speed driving, the minimum unit of elapsed time can be widely controlled in 1 second unit, 0.1 second unit, 0.01 second unit, 0.001 second unit, etc. Therefore, the timing device disclosed in the present invention can be applied to stopwatches used in sports competitions such as sports, speed competitions such as car racing and airplane competitions, time display units used in high-speed photography equipment, etc.

The time control unit may also be a program software stored in a storage unit such as a RAM or ROM of a driving element such as an IC or LSI provided inside or outside the dot matrix display device 1. In addition, the time control unit may also be a time control circuit formed on a circuit substrate provided inside or outside the dot matrix display device 1.

FIG. 11 is a schematic front view of a timing device 200 having a dot matrix display device 1 of the present disclosure. The dot matrix display device 1 is assembled in a display unit 201 of the timing device 200. The display unit 201 has display areas 202, 203, and 204. The timing device 200 may be a stopwatch, a digital watch with a stopwatch function, a smart watch with a stopwatch function, etc. The example in FIG. 11 is a digital watch with a stopwatch function. The timing device 200 has a timing start button 205, a timing stop button 206, and a minimum unit change button 207 for the elapsed time on the periphery. Each time the button 207 is pressed, the minimum unit of the elapsed time is cyclically changed in 1 second unit, 0.1 second unit, 0.01 second unit, and 0.001 second unit via the elapsed time control unit 208. The elapsed time control unit 208 is built into the timing device 200. The timing is controlled by the timing start button 205 and the timing stop button 206, but the timing can also be electrically controlled using a human body sensing sensor such as a light sensor or an infrared sensor. In this case, timing can be performed with higher accuracy.

According to the dot matrix display device disclosed in the present invention, the transmission time of address data and image data can be shortened, and the control circuit for controlling the rewrite drive can operate normally. That is, even if the clock frequency of the first clock signal is increased in order to shorten the transmission time of the image data, the control circuit can control the timing of the serial-to-parallel conversion performed by the conversion circuit based on a second clock signal having a lower frequency than the first clock signal, for example, a second clock signal having the same clock frequency as before. As a result, the control circuit can operate normally.

According to the timekeeping device of the present disclosure, since it includes the dot matrix display device of the present disclosure that can be driven at high speed, it is possible to perform a wide range of control over the minimum unit of the elapsed time, such as 1 second unit, 0.1 second unit, 0.01 second unit, 0.001 second unit, etc.

The above detailed descriptions of the various embodiments of the present disclosure are given. In addition, the present disclosure is not limited to the above embodiments, and various changes and improvements can be made without departing from the scope of the present disclosure. Of course, all or part of the above embodiments can be appropriately combined within the scope of non-contradiction.

-Industrial Availability-

The dot matrix display device disclosed in the present invention can be applied to various electronic devices. As such electronic devices, for example, there are automobile route guidance systems (automobile navigation systems), ship route guidance systems, aircraft route guidance systems, instrument indicators for vehicles such as automobiles, partition panels, smart phone terminals, mobile phones, tablet terminals, personal digital assistants (PDAs), cameras, digital cameras, electronic manuals, electronic books, electronic dictionaries, personal computers, copiers, terminal devices for game devices, televisions, product display labels, price display labels, industrial programmable display devices, car audio, digital audio players, fax machines, printers, cash automatic deposit and withdrawal machines (ATMs), vending machines, medical display devices, digital display watches, smart watches, stations, and guidance display devices set up at airports, etc.

-Explanation of symbols-

1 Dot matrix display device

2. Substrate

3 Display

31 Gate signal line

32 Source signal line

33 Pixel Circuit

331 Write switch circuit

332 Latch Circuit

332a, 332b CMOS Inverter

333 Pixel potential generation circuit

334 Liquid crystal element

334a Pixel electrode

334b LCD

334c Counter electrode

4-way frequency divider

41 Trigger Circuit

42 Inverter Circuit

5 Conversion circuit

51 vertical conversion circuit

52 Shift Register Circuit

521 Trigger Circuit

53 Latch activation signal circuit

531 Inverter Circuit

532 Logic Gate Circuit (NAND Circuit)

54 Latch Circuit

55 Horizontal conversion circuit

56 Shift Register Circuit

561 Trigger Circuit

57 Latch activation signal circuit

571 Inverter Circuit

572 Logic Gate Circuit (NAND Circuit)

58 Latch Circuit

6 Control Circuit

61 Counter Circuit

611 Combinational Logic Circuits

612 Trigger Circuit

62 vertical control circuit

621 Combinational Logic Circuits

622 Trigger Circuit

623 First single pulse circuit

624 Second single pulse circuit

625 The third single pulse circuit

626 Logic Gate Circuit (OR Circuit)

627 RS latch circuit

628 Combinational Logic Circuits

629 Trigger Circuit

63 Horizontal control circuit

631 Combinational Logic Circuits

632 Trigger Circuit

633 Fourth single pulse circuit

634 Fifth single pulse circuit

635 RS latch circuit

636 Combinational Logic Circuits

637 Trigger Circuit

7 Decoder Circuit

71 Logic gate circuit (NOR circuit)

72 Inverter Circuit

8 Driver Circuit

81 Vertical driver circuit

811 Logic Gate Circuit (AND Circuit)

812 Buffer Circuit

82 Horizontal driver circuit

821 Logic Gate Circuit (AND Circuit)

822 Buffer Circuit

200 Timing Device

201 Display

202, 203, 204 Display area

205 Chrono start button

206 Chrono stop button

207 Minimum unit change button

208 Time control unit.

Claims (11)

1. A dot matrix display device comprising: A display unit having: a plurality of gate signal lines extending in a first direction; a plurality of source signal lines extending in a second direction intersecting the first direction; and a plurality of pixel circuits arranged corresponding to intersections of the plurality of gate signal lines and the plurality of source signal lines; a conversion circuit that acquires a serial signal input from the outside via a serial interface in synchronization with a first clock signal input from the outside, and converts the acquired serial signal into a parallel signal, the serial signal including address data for specifying a pixel circuit for rewriting image data and the image data supplied to the pixel circuit; and a control circuit that generates a control signal for controlling the timing of serial-to-parallel conversion of the conversion circuit based on a second clock signal having a frequency lower than that of the first clock signal, Each of the plurality of pixel circuits includes a latch circuit for holding the image data. The pixel circuit that does not rewrite the image data performs still image driving using the image data held in the latch circuit, The serial signal includes dummy data not used for rewriting the drive, The dummy data is transmitted to the conversion circuit after the address data and the image data. The transmission period of the dummy data is an activation period of a gate signal supplied to the gate signal line based on a gate signal of an address signal for determining the pixel circuit for rewriting the image data, and the transmission period of the dummy data is an activation period of a source signal supplied to the source signal line based on a source signal of the image data, A transmission period of the dummy data is shorter than a transmission period of the image data. 2. The dot matrix display device according to claim 1, wherein: The device comprises: a clock frequency control unit configured to control the frequency of the first clock signal. 3. The dot matrix display device according to claim 1 or 2, wherein: The device includes a frequency dividing circuit for generating, based on the first clock signal, the second clock signal obtained by frequency-dividing the first clock signal. 4. The dot matrix display device according to claim 1, wherein: have: A first clock signal generating unit, generating the first clock signal; and The second clock signal generating unit generates the second clock signal. 5. The dot matrix display device according to claim 1 or 2, wherein: The control circuit generates the control signal based on a count signal obtained by counting the number of rising edges of the second clock signal. 6. The dot matrix display device according to claim 5, wherein: The control circuit includes a counting circuit that generates the counting signal in synchronization with the second clock signal. 7. The dot matrix display device according to claim 1 or 2, wherein: The conversion circuit has a vertical conversion circuit. The vertical conversion circuit converts the address data included in the serial signal into a parallel signal based on the control signal to generate the address signal. 8. The dot matrix display device according to claim 7, wherein: The vertical conversion circuit has a decoder circuit, The decoder circuit generates an address decoding signal to be supplied to the plurality of gate signal lines based on the address signal. 9. The dot matrix display device according to claim 1 or 2, wherein: The conversion circuit has a horizontal conversion circuit. The horizontal conversion circuit converts the image data included in the serial signal into a parallel signal based on the control signal, and generates a data signal to be supplied to the plurality of source signal lines. 10. The dot matrix display device according to claim 1, wherein: The latch circuit holds a plurality of bits, whereby the pixel circuit performs grayscale display. 11. A timing device, A dot matrix display device according to any one of claims 1 to 10, A time control unit is provided for controlling the minimum unit of elapsed time.