JPS5978543A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS5978543A JPS5978543A JP18838582A JP18838582A JPS5978543A JP S5978543 A JPS5978543 A JP S5978543A JP 18838582 A JP18838582 A JP 18838582A JP 18838582 A JP18838582 A JP 18838582A JP S5978543 A JPS5978543 A JP S5978543A
- Authority
- JP
- Japan
- Prior art keywords
- film
- groove
- resist
- substrate
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 7
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 10
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 230000001678 irradiating effect Effects 0.000 claims description 3
- 230000001590 oxidative effect Effects 0.000 claims description 2
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 2
- 210000003323 beak Anatomy 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- 230000003647 oxidation Effects 0.000 description 9
- 238000007254 oxidation reaction Methods 0.000 description 9
- 241000293849 Cordylanthus Species 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 230000010354 integration Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000011324 bead Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は半導体装置の製造方法、とりわけ、素子間の絶
縁分離の形成方法に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of forming insulation separation between elements.
従来例の構成とその問題点
シリコン基板表面のトランジスタ等を形成する予定の素
子領域を残し、その周辺を酸化して酸化シリコン（以下
、５１０２）を形成し、隣接する素子領域との間を電気
的に絶縁分離する方式ｄ２、ＬＯＧＯ３技術としてよく
知られている。The structure of the conventional example and its problems The element area where transistors etc. are to be formed on the surface of the silicon substrate is left, the periphery is oxidized to form silicon oxide (hereinafter referred to as 5102), and electrical connection is established between the adjacent element areas. The d2 and LOGO3 techniques are well known as the d2 and LOGO3 techniques.
その概略を第１図に示す断面図に従−）で述べる。The outline will be described in accordance with the sectional view shown in FIG.
素子領域として酸化せずに残す基板の表面部分に、まず
、パッドあるいはバッファーと呼ばれるする。素子の作
り込みに必要な素子領域３を画定＼
し、その外側面の絶縁分離を形成する領域のＳｉ３Ｎ４
膜２を除去し、ここに厚い酸化膜４を形成し絶縁分離領
域４とする。First, the surface area of the substrate that is left unoxidized as an element region is called a pad or buffer. Define the element region 3 necessary for device fabrication\ and Si3N4 in the region where insulation isolation is formed on the outer surface of the element region 3.
The film 2 is removed and a thick oxide film 4 is formed thereon to form an insulating isolation region 4.
従来の問題点は、酸化時に横方向酸化も同時に進行する
ことにより、耐酸化マスクである窒化シリコン膜２で規
定される酸化防止領域を侵かして、素子領域３へ捷で酸
化層４が拡がり、いわゆるバーズビーク５が発生するこ
とである。バーズビーり５は、素子領域３でも、絶縁領
域でもなく不要な領域である。つ甘り、その分たり集積
度を１・げることを妨げ、半導体装置１個当りの基板の
面積を大きくするという欠点をもっていることになる。The problem with the conventional method is that lateral oxidation also progresses at the same time as oxidation, which invades the oxidation prevention area defined by the silicon nitride film 2, which is an oxidation-resistant mask, and causes the oxide layer 4 to leak into the element region 3. The problem is that the so-called bird's beak 5 occurs. The bird's bead 5 is neither the element region 3 nor the insulating region, but an unnecessary region. This has the disadvantage of making it difficult to increase the degree of integration by 1.0 mm, and increasing the area of the substrate per semiconductor device.
従って、半導体装置の集積度を上げ、基板の面積を小さ
くするためには、バーズビーり５を抑制することが、一
つの有効な手段となる。尚、６は半導体基板である。Therefore, in order to increase the degree of integration of a semiconductor device and reduce the area of the substrate, suppressing the bird's bead 5 is one effective means. Note that 6 is a semiconductor substrate.
発明の目的
本発明は、バーズビークを抑制し分離領域の拡がりを最
小限になし得る半導体装置の製造方法を供するものであ
る。OBJECTS OF THE INVENTION The present invention provides a method of manufacturing a semiconductor device that can suppress bird's beak and minimize the spread of isolation regions.
発明の構成
本発明は溝部の」二部端部にレジストを残す様に斜方向
から平行光線を照射してレジスト露光をし、このレジス
トをマスクに窒化シリコン膜をエツチングし、この窒化
シリコン膜をマスクにして酸化を行ない溝部に酸化膜を
形成する半導体装置の製造方法である。Structure of the Invention The present invention exposes the resist by irradiating parallel light from an oblique direction so as to leave the resist at the two ends of the groove, etches the silicon nitride film using the resist as a mask, and etches the silicon nitride film. This is a method of manufacturing a semiconductor device in which oxidation is performed using a mask to form an oxide film in a trench.
実施例の説明
本発明の実施例を第２図に示す工程断面図を用いて説明
する。DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described using process cross-sectional views shown in FIG.
半導体基板１ｏの絶縁領域とするべき位置に周知のフォ
トリソグラフィの方法とエツチングの方法により溝１１
を形成する。次に、熱酸化により薄い５ｉｏ２膜１２を
形成し、その」二に既知の減圧ＣＶＤ法により５１３Ｎ
４膜１３を形成する（第２図Ａ）。さらに、重ねてネガ
タイプのフォトレジスト１４を塗付する。この時、フ１
トレジスト１４０表面には溝部１１に沿う窪みをもだせ
、溝１１を完全には埋めてし捷わないようにする（第２
図Ｂ）。ここで、基板表面に対して一定の角αで、かつ
平面で見た溝１１の側壁に対して約４５°である方向か
ら平行光線１５を照射することにより露光する。次に、
同様に反対方向１６から露光を行なう。そして、既知の
方法で現像処理を行なう。Grooves 11 are formed in the positions of the semiconductor substrate 1o to be insulating regions by well-known photolithography and etching methods.
form. Next, a thin 5io2 film 12 is formed by thermal oxidation, and then a 513N film 12 is formed by a known low pressure CVD method.
4 films 13 are formed (FIG. 2A). Furthermore, a negative type photoresist 14 is applied overlappingly. At this time, F1
A depression along the groove portion 11 is formed on the surface of the resist resist 140 so as to completely fill the groove 11 and prevent it from becoming loose.
Figure B). Here, exposure is performed by irradiating parallel light rays 15 from a direction that is at a constant angle α with respect to the substrate surface and approximately 45° with respect to the side wall of the groove 11 when viewed in a plane. next,
Exposure is similarly performed from the opposite direction 16. Then, development processing is performed using a known method.
露光された部分のレジスト１７は残り、未露光のレジス
ト１８は除去される（第２図Ｃ）。残−）だ、フォトレ
ジスト１７をマスクとして８１３Ｎ４膜１３のエツチン
グを行ない、溝１１底面と側面の二部の５ｉ３ＮＡ膜１
３を除去する。次にフォトレジスト１７を除去し、８１
３Ｎ４膜１３をマスクに選択酸化を行なう。酸化は溝１
１を埋める程度になるまで行ない、５ｉ０２層１９を形
成する（第２図Ｄ）。The exposed portions of the resist 17 remain, and the unexposed portions of the resist 18 are removed (FIG. 2C). (Remaining) The 813N4 film 13 is etched using the photoresist 17 as a mask, and the 5i3NA film 1 on the bottom and side surfaces of the trench 11 is etched.
Remove 3. Next, the photoresist 17 is removed and the photoresist 81 is removed.
Selective oxidation is performed using the 3N4 film 13 as a mask. Oxidation is groove 1
The 5i02 layer 19 is formed by performing this process until the 5i02 layer 19 is filled (FIG. 2D).
これにより、バーズビークは溝１１の側面に形成される
が、基板平面の大面積に及ぶことはなくなるＯ
発明の効果
本発明の方法では、横方向への酸化を、溝内にまで伸延
されたＳｌ、Ｎ４膜によって、抑制するため、従来の方
法のようなバーズビークを発生を抑えることが出来、素
子領域と絶縁領域との間に不要な面積が発生することが
なく、高集積化、小型化に富力することができる。As a result, the bird's beak is formed on the side surface of the groove 11, but does not cover a large area of the substrate plane. Effects of the Invention In the method of the present invention, the oxidation in the lateral direction is prevented from oxidizing the Sl that extends into the groove. , the N4 film suppresses the occurrence of bird's beaks that occur in conventional methods, and eliminates the need for unnecessary area between the element region and the insulating region, leading to higher integration and miniaturization. You can become rich and powerful.
第１図は従来の方法を説明するだめの構造断面図、第２
図Ａ−Ｄは本発明の詳細な説明する工程断面図である。
１１ ・・基板に形成した溝、１２ ・５１ｏ２膜（
バッファ一層） 、１３−− Ｓｉ３Ｎ４膜、１４（１
７と１８） ・フォトレジスト、１５．１６・−・・
露光用の光の方向、１７ 露光されたレジスト、１８
・・ 未露光レジスト、１９ ・８１０２層。Figure 1 is a cross-sectional view of the structure to explain the conventional method;
Figures A to D are cross-sectional views illustrating detailed explanations of the present invention. 11 ・Groove formed on the substrate, 12 ・51o2 film (
buffer layer), 13-- Si3N4 film, 14 (1
7 and 18) ・Photoresist, 15.16...
Direction of light for exposure, 17 Exposed resist, 18
・・Unexposed resist, 19 ・8102 layers.
Claims (1)
化シリコン膜を順次形成する工程と、フＡト・レジスト
を塗付し、前記基板に対して斜方向から平行光線を照射
することにより露光し７、前記溝部の上部端部を残して
前記フォト・レジストを除去する工程と、前記フォト・
レジストをマスクに前記窒化シリコン膜大除去し、残存
した前記窒化シリコン膜をマスクにして前記溝部を酸化
する工程を含むことを特徴とする半導体装置の製造方法
。By forming a groove in a substrate, sequentially forming a silicon oxide film and a silicon nitride film on the substrate, applying a photoresist, and irradiating the substrate with parallel light from an oblique direction. exposing the photoresist to light (7) and removing the photoresist leaving the upper end of the groove;
A method for manufacturing a semiconductor device, comprising the steps of: removing a large portion of the silicon nitride film using a resist as a mask; and oxidizing the trench using the remaining silicon nitride film as a mask.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18838582A JPS5978543A (en) | 1982-10-27 | 1982-10-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18838582A JPS5978543A (en) | 1982-10-27 | 1982-10-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5978543A true JPS5978543A (en) | 1984-05-07 |
Family
ID=16222694
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18838582A Pending JPS5978543A (en) | 1982-10-27 | 1982-10-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5978543A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
-
1982
- 1982-10-27 JP JP18838582A patent/JPS5978543A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5106777A (en) * | 1989-09-27 | 1992-04-21 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
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