KR0166489B1 - Device Separation Method of Semiconductor Devices - Google Patents
Device Separation Method of Semiconductor Devices Download PDFInfo
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- KR0166489B1 KR0166489B1 KR1019940027917A KR19940027917A KR0166489B1 KR 0166489 B1 KR0166489 B1 KR 0166489B1 KR 1019940027917 A KR1019940027917 A KR 1019940027917A KR 19940027917 A KR19940027917 A KR 19940027917A KR 0166489 B1 KR0166489 B1 KR 0166489B1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
- H01L21/7621—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region the recessed region having a shape other than rectangular, e.g. rounded or oblique shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
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Abstract
본 발명은 반도체소자의 소자분리 방법에 관한 것으로서, 반도체기판에서 소자분리 영역으로 예정되어 있는 부분을 노출시키는 질화막 패턴을 형성하고 상기 질화막 패턴의 측벽에 질화막으로된 스페이서를 형성하며, 그에 의해 노출되는 반도체기판의 소정두께를 등방성 식각하여 언더컷이 진 트랜치를 형성하여 부피팽창에 따른 스트레스를 감소시키며, 상기 트랜치의 측벽 부분에 질화막 패턴을 형성하여 산화막과 반도체기판의 경계 부분에 산소가 침투하는 것을 방지한 후, 열산화를 실시하여 소자분리 산화막을 형성하였으므로, 반도체기판의 스트레스가 감소되어 격자결함에 따른 누설전류 증가를 방지하여 소자동작의 신뢰성을 향상시킬 수 있으며, 버즈 빅의 크기가 감소되어 고자의 고집적화에 유리하고 공정수율을 향상시킬 수 있다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, comprising forming a nitride film pattern exposing a portion intended for a device isolation region on a semiconductor substrate, and forming a spacer of a nitride film on a sidewall of the nitride film pattern. Isotropic etching of a predetermined thickness of the semiconductor substrate to form trenches undercut to reduce stress due to volume expansion, and to form a nitride film pattern on the sidewall portion of the trench to prevent oxygen from penetrating the boundary between the oxide film and the semiconductor substrate. After the thermal oxidation, the device isolation oxide film is formed to reduce the stress of the semiconductor substrate, thereby preventing leakage current increase due to lattice defects, thereby improving reliability of device operation, and reducing the size of the buzz big. It is advantageous to the high integration of the process and can improve the process yield.
Description
제1a도 내지 제1e도는 본 발명의 일실시예에 따른 반도체소자의 소자분리 공정도.1A through 1E are device isolation process diagrams of a semiconductor device according to an embodiment of the present invention.
제2a도 내지 제2c도는 본 발명의 다른 실시예에 따른 반도체소자의 소자분리 공정도.2A to 2C are device isolation process diagrams of a semiconductor device according to another embodiment of the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 반도체 기판 2 : 산화막1 semiconductor substrate 2 oxide film
3,6 : 질화막 6 : 스페이서3,6: nitride film 6: spacer
5 : 트랜치5: trench
본 발명은 반도체소자의 소자분리 방법에 관한 것으로서, 특히 소자분리 산화막으로 예정되어 있는 부분에 트랜치를 형성하고 상기 트랜치의 테두리 부분상에 질화막 패턴을 형성하여 필드 산화막의 테두리 부분에 발생되는 버즈 빅(bird's beak)의 크기를 감소시켜 반도체기판의 스트레스가 감소되어 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 소자분리 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a device isolation method of a semiconductor device, and in particular, to form a trench in a portion intended as an element isolation oxide film, and to form a nitride film pattern on the edge portion of the trench, thereby producing a buzz big ( The present invention relates to a device isolation method of a semiconductor device capable of reducing the stress of a semiconductor substrate by reducing the size of a bird's beak, thereby improving process yield and reliability of device operation.
일반적으로 반도체소자는 트랜지스터나 캐패시터등과 같은 소자들이 형성되는 활성 영역과, 상기 소자들의 동작이 서로 방해되지 않도록 활성 영역들을 분리시키는 소자분리 영역이 형성되어 있다.In general, a semiconductor device includes an active region in which devices such as a transistor or a capacitor are formed, and an isolation region in which the active regions are separated from each other so that the operation of the devices does not interfere with each other.
최근에 반도체소자의 고집적화 추세에 따라 반도체소자에서 많은 면적을 차지하는 소자분리 영역을 감소시키려는 노력이 꾸준히 진행되고 있다.Recently, with the trend toward higher integration of semiconductor devices, efforts have been made to reduce device isolation regions, which occupy a large area in semiconductor devices.
이러한 소자분리 영역의 제조 방법으로는 질화막 패턴을 마스크로하여 실리콘 반도체 기판을 열산화시키는 로코스(local oxidation of silicon; 이하 LOCOS라 칭함) 방법과, 반도체 기판에 트랜치를 형서한 후 절연물질로 메우는 트랜치(trench) 분리 방법 그리고 별도의 폴리실리콘층을 열산화시키는 세폭스(SEFOX) 등의 방법이 있으며, 그중 LOCOS 방법은 비교적 공정이 간단하여 널리 사용되고 있다.The device isolation region manufacturing method includes a local oxidation of silicon (hereinafter referred to as LOCOS) method of thermally oxidizing a silicon semiconductor substrate using a nitride film pattern as a mask, and filling a trench with an insulating material after forming a trench in the semiconductor substrate. There is a trench isolation method and a SEFOX method for thermally oxidizing a separate polysilicon layer. Among them, the LOCOS method is widely used due to its relatively simple process.
상기 LOCOS 필드 산화막의 제조 방법을 살펴보면 다음과 같다.The manufacturing method of the LOCOS field oxide film is as follows.
먼저, 실리콘으로된 반도체기판의 표면을 열산화시켜 패드산화막을 형성하고, 상기 패드산화막 상에 상기 반도체기판의 소자분리 영역으로 예정된 부분을 노출시키는 질화막 패턴을 형성한 후, 상기 질화막 패턴을 열산화 마스크로 하여 반도체 기판을 소정 두께 열산화시켜 필드 산화막을 형성한다.First, a pad oxide film is formed by thermally oxidizing a surface of a semiconductor substrate made of silicon, and a nitride film pattern is formed on the pad oxide film to expose a predetermined portion to an element isolation region of the semiconductor substrate. Then, the nitride film pattern is thermally oxidized. The semiconductor substrate is thermally oxidized for a predetermined thickness as a mask to form a field oxide film.
이러한 종래의 LOCOS 필드산화막은 활성영역과 필드 산화막 사이의 반도체 기판 경계에 산소가 측면 침투하여 버즈 빅이라는 경사면이 형성된다.In the conventional LOCOS field oxide film, oxygen penetrates into the semiconductor substrate boundary between the active region and the field oxide film to form an inclined surface called buzz big.
상기의 경사면은 필요한 활성영역의 확보나 후속 감광막패턴 형성을 위한 노광공정에서 광을 반사시켜 감광막의 비노광 부분이 노광되어 패턴의 일정부분이 폭이 좁게 형성되는 나칭(notching)이 발생되는 문제점이 있으며, 이러한 문제점은 0.5㎛ 이하의 디자인 롤을 갖는 반도체 소자에서는 더 큰 어려움이 된다.The inclined surface reflects light in an exposure process for securing a required active area or forming a subsequent photoresist pattern, thereby exposing a non-exposed portion of the photoresist to expose a portion of the pattern to have a narrow width. This problem is more difficult in a semiconductor device having a design roll of 0.5 mu m or less.
특히 일차로 형성되는 게이트 전극의 경우에는 필드 산화막의 굴곡에 가장 많은 영향을 받아 소자의 공정수율 및 신뢰성을 저하시킨다.Particularly, in the case of the gate electrode formed primarily, the bending of the field oxide film is most affected to reduce the process yield and the reliability of the device.
이러한 문제점을 해결하기 위하여 0.5㎛ 이하의 디자인 롤을 갖는 밭도체 소자의 제조시에는 상기 LOCOS를 발전시킨 변형 LOCOS 법이나, 다수번의 노광 공정을 진행하는 다층 레지스트(multiple layer resist; 이하 MLR이라 칭함) 방법의 일종인 삼층 레지스트(triple layer resist; 이하 TLR이라 칭함)법이나, LOCOS 공정 후 질화막을 제거하지 않고 화학기상증착(chemical vapor deposition; 이하 CVD라 칭함) 산화막을 전면에 도포하고 건식식각하여 단차를 감소시키는 프레너 에치백(planar etch back) 방법 등이 사용되고 있다.In order to solve this problem, when manufacturing a field conductor device having a design roll of 0.5 μm or less, a modified LOCOS method that has developed the LOCOS, or a multiple layer resist (hereinafter referred to as MLR) which undergoes a plurality of exposure processes is referred to. A three-layer resist (TLR) method, which is a kind of method, or chemical vapor deposition (hereinafter referred to as CVD) oxide film is applied to the entire surface without removing the nitride film after the LOCOS process, and then etched by dry etching. Planar etch back (planar etch back) method for reducing the like is used.
그러나 상기 TLR 방법은 공정이 매우 어렵고 복잡하며, 소자의 결함이 증가되어 신뢰성이 떨어지는 등의 문제점이 있다.However, the TLR method has a problem that the process is very difficult and complicated, and the defect of the device is increased, resulting in poor reliability.
또한 프레너 에치백 방법은 건식 식각에 의해 부산물이 발생하여 오염에 의해 소자의 특성이 저하되고, 공정이 어려운 등의 문제점이 있다.In addition, the planner etchback method has problems such as by-products generated by dry etching, deterioration of device characteristics due to contamination, and difficulty in processing.
본 발명은 상기와 같은 문제점들을 해결하기 위한 것으로서, 본 발명의 목적은 반도체기판에서 소자분리 영역으로 예정되어 있는 부분에 트랜치를 형성하고, 상기 트랜치의 측벽에 질화막 패턴을 형성한 후, 열산화를 실시하여 열산화 마스크인 두꺼운 질화막 패턴에 의한 압력을 분산시키고 버즈 빅을 작게 형성하여 반도체기판의 스트레스를 감소시켜 공정수율 및 소자동작의 신뢰성을 향상시킬 수 있는 반도체소자의 소자분리 방법을 제공함에 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to form a trench in a predetermined portion of the semiconductor substrate as a device isolation region, form a nitride film pattern on the sidewall of the trench, and then perform thermal oxidation. The present invention provides a device isolation method of a semiconductor device capable of dispersing pressure due to a thick nitride film pattern, which is a thermal oxidation mask, and forming a small buzz big to reduce stress on a semiconductor substrate, thereby improving process yield and device operation reliability. .
상기와 같은 목적을 달성하기 위한 본 발명에 따른 반도체소자의 소자분리 방법의 특징은, 반도체기판상에 산화막을 형성하는 공정과, 상기 산화막상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상의 제1질화막을 제거하여 산화막을 노출시키는 제1질화막 패턴을 형성하는 공정과, 상기 제1질화막 패턴의 측벽에 질화막으로된 스페이서를 형성하는 공정과, 상기 스페이서에 의해 노출되어 있는 산화막을 제거하여 반도체기판을 노출시키는 공정과, 상기 노출되어 있는 반도체기판을 등반성식각 방법으로 예정된 깊이로 제거하여 상기 산화막 패턴의 하부에 언더컷이 진 트랜치를 형성하는 공정과, 상기 트랜치에서 내부의 언더컷이 진 부분과 트랜치의 측벽에 제2질화막 패턴을 형성하는 공정과, 상기 제1 및 제2질화막 패턴에 의해 노출되어 있는 트랜치 내부의 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비함에 있다.A device isolation method for a semiconductor device according to the present invention for achieving the above object comprises the steps of forming an oxide film on a semiconductor substrate, forming a first nitride film on the oxide film, and in the semiconductor substrate Forming a first nitride film pattern exposing the oxide film by removing the first nitride film on the portion intended as the device isolation region, forming a spacer made of a nitride film on the sidewall of the first nitride film pattern, and Removing the exposed oxide film to expose the semiconductor substrate, removing the exposed semiconductor substrate to a predetermined depth by a climbing etching method, and forming a trench having an undercut under the oxide pattern; Forming a second nitride film pattern on the undercut portion of the trench and the sidewall of the trench; First and second thermally oxidizing the semiconductor substrate within the trench which are exposed by the nitride film pattern consists in a step of forming an element isolation oxide film.
본 발명에 따른 반도체소자의 소자분리 방법의 다른 특징은, 반도체기판상에 산화막을 형성하는 공정과, 상기 산화막상에 제1질화막을 형성하는 공정과, 상기 반도체기판에서 소자분리 영역으로 예정되어 있는 부분상의 제1질화막과 산화막을 제거하여 반도체기판을 노출시키는 제1질화막 패턴과 산화막 패턴을 형성하는 공정과, 사기 제1질화막 패턴과 산화막 패턴의 측벽에 질화막으로된 스페이서를 형성하는 공정과, 상기 스페이서에 의해 노출되어 있는 반도체기판을 예정된 깊이로 제거하여 상기 질화막 스페이서 하부에 언더컷이 진 트랜치를 형성하는 공정과, 상기 질화막 스페이서에 의해 노출되어 있는 반도체기판을 열산화시켜 소자분리 산화막을 형성하는 공정을 구비함에 있다.Other features of the device isolation method of a semiconductor device according to the present invention include a step of forming an oxide film on a semiconductor substrate, a step of forming a first nitride film on the oxide film, and a device isolation region in the semiconductor substrate. Removing the first nitride film and the oxide film on the portion to form a first nitride film pattern and an oxide film pattern exposing the semiconductor substrate; forming a spacer of a nitride film on the sidewalls of the first nitride film pattern and the oxide film pattern; Removing the semiconductor substrate exposed by the spacer to a predetermined depth to form an undercut trench under the nitride film spacer; and forming a device isolation oxide film by thermally oxidizing the semiconductor substrate exposed by the nitride film spacer. In the provision.
이하, 본 발명에 따른 반도체소자의 소자분리 방법에 관하여 첨부도면을 참조하여 상세히 설명한다.Hereinafter, a device isolation method of a semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings.
제1a도 내지 제1e도는 본 발명의 일실시예에 따른 반도체소자의 소자분리 공정도이다.1A through 1E are device isolation process diagrams of a semiconductor device according to an embodiment of the present invention.
먼저, 실리콘 재질의 반도체기판(1)상에 산화막(2)과 제1질화막(3)을 순차적으로 형성한 후, 상기 반도체기판(1)에서 소자분리 영역으로 예정되어 있는 부분 상측의 제1질화막(3)을 제거하여 상기 산화막(2)을 노출시키는 제1질화막(3) 패턴을 형성한다. 이때 상기 산화막(2)은 열산화 또는 화학기상증착(chemical vapor deposition; 이하 CVD라 칭함) 방법으로, 제1질화막(3)은 CVD 방법으로 형성한다(제1a도 참조).First, the oxide film 2 and the first nitride film 3 are sequentially formed on the semiconductor substrate 1 made of silicon, and then the first nitride film on the upper portion of the semiconductor substrate 1, which is to be an element isolation region, is formed. (3) is removed to form a first nitride film 3 pattern exposing the oxide film 2. In this case, the oxide film 2 is formed by thermal oxidation or chemical vapor deposition (hereinafter, referred to as CVD), and the first nitride film 3 is formed by CVD (see FIG. 1A).
그 다음 상기 제1질화막(3) 패턴의 측벽에 질화막 도포 및 전면 이방성 식각 방법으로 스페이서(4)를 형성한 후, 상기 제1질화막(3) 패턴과 스페이서(4)에 의해 노출되어 있는 산화막(2)을 제거하여 그 하부의 반도체기판(1)을 노출시킨다(제1b도 참조).Next, after forming the spacers 4 on the sidewalls of the first nitride film 3 pattern by applying a nitride film and an anisotropic etching method, the oxide film exposed by the first nitride film 3 pattern and the spacer 4 ( 2) is removed to expose the lower semiconductor substrate 1 (see also FIG. 1b).
그 다음 열산화에 따른 부피 팽창에 의해 격자 결함이 증가되고 이에 따른 접합 누설전류 증가를 방지하기 위하여 등방성식각 방법으로 반도체기판(1)을 소정 두께 제거하여 경사진 측벽을 갖고, 스페이서(4)의 하부로 언더컷(under cut)이 진 트랜치(5)를 형성한다(제1c도 참조).Then, the lattice defect is increased by the volume expansion due to thermal oxidation, and the semiconductor substrate 1 is removed by a isotropic etching method by a predetermined thickness in order to prevent the increase in the junction leakage current. The undercut forms a trench 5 which is undercut (see also FIG. 1C).
그후, 상기 구조의 전표면에 제2질화막(6)을 도포하여 상기 트랜치(5)의 내벽도 감싸도록한 후(제1d도 참조), 상기 제2질화막(6)을 트랜치(5) 내부의 반도체기판(1)이 노출될때까지 상측에서 전면 이방성식각하여 상기 트랜치(5)의 측벽 부분, 즉 산화막(2) 패턴의 언더컷이 진 부분에만 제2질화막(6) 패턴이 남도록 한다. 상기 제2질화막(6) 패턴은 후속 열산화 공정시 산소가 산화막(2) 패턴과 반도체기판(1) 사이의 경계로 침투하는 것을 방지하여 버즈 빅의 크기를 감소시킨다(제1e도 참조).Thereafter, the second nitride film 6 is applied to the entire surface of the structure to cover the inner wall of the trench 5 (see also FIG. 1d), and then the second nitride film 6 is formed inside the trench 5. Anisotropically etch the entire surface from the top until the semiconductor substrate 1 is exposed so that the second nitride layer 6 pattern remains only on the sidewall portion of the trench 5, that is, the undercut portion of the oxide layer 2 pattern. The second nitride film 6 pattern prevents oxygen from penetrating into the boundary between the oxide film 2 pattern and the semiconductor substrate 1 during the subsequent thermal oxidation process, thereby reducing the size of the buzz big (see also FIG. 1e).
그 다음 도시되어 있지는 않으나, 상기 트랜치(5) 내부의 노출되어 있는 반도체기판(1)을 소정두께 열산화시켜 소자분리 산화막을 형성하고, 상기 산화막(2)과 스페이서(4)와 제1 및 제2질화막(3),(6)를 제거하여 소자분리 공정을 완료한다.Next, although not shown, the semiconductor substrate 1 exposed inside the trench 5 is thermally oxidized to a predetermined thickness to form a device isolation oxide film, and the oxide film 2 and the spacers 4 and the first and first layers are formed. The second nitride films 3 and 6 are removed to complete the device isolation process.
제2a도 내지 제2c도는 본 발명의 다른 실시예에 따른 반도체소자의 소자분리 공정도이다.2A to 2C are device isolation process diagrams of a semiconductor device according to another exemplary embodiment of the present invention.
먼저, 반도체기판(1)상에 산화막(2)과 질화막(3)을 열산화나 CVD 방법으로 순차적으로 형성한 후, 상기 반도체기판(1)에서 소자분리 영역으로 예정되어 있는 부분상의 제1질화막(3)과 산화막(2)을 순차적으로 제거하여 반도체기판(1)을 노출시키는 제1질화막(3) 및 산화막(2) 패턴을 형성한다(제2a도 참조).First, the oxide film 2 and the nitride film 3 are sequentially formed on the semiconductor substrate 1 by thermal oxidation or CVD, and then the first nitride film on the portion of the semiconductor substrate 1, which is scheduled as an element isolation region. (3) and the oxide film 2 are sequentially removed to form a pattern of the first nitride film 3 and the oxide film 2 exposing the semiconductor substrate 1 (see also FIG. 2A).
그다음 상기 제1질화막(3) 패턴과 산화막(2) 패턴의 측벽에 질화막 재질의 스페이서(4)를 형성한 후(제2b도 참조), 열산화에 이한 부피 팽창에 따른 스트레스를 고려하여 등방성식각 방법으로 반도체기판(1)을 소정 두께 제거하여 경사진 측벽을 갖는 트랜치(5)를 형성한다. 이때 상기 트랜치(5)는 등방성 식각 방법으로 형성되므로 질화막 스페이서(4)의 하부로 언더컷이 진다(제2c도 참조).Then, a spacer 4 of nitride material is formed on the sidewalls of the first nitride film 3 pattern and the oxide film pattern 2 (see FIG. 2b), and then isotropically etched in consideration of stress due to volume expansion following thermal oxidation. The semiconductor substrate 1 is removed by a predetermined thickness to form a trench 5 having an inclined sidewall. At this time, since the trench 5 is formed by an isotropic etching method, the trench 5 is undercut under the nitride film spacer 4 (see also FIG. 2C).
그후, 도시되어 있지는 않으나, 상기 트랜치(5) 내부의 노출되어 있는 반도체기판(1)을 소정두께 열산화시켜 소자분리 산화막을 형성한다.Thereafter, although not shown, the semiconductor substrate 1 exposed inside the trench 5 is thermally oxidized to a predetermined thickness to form an element isolation oxide film.
이상에서 설명한 바와 같이, 본 발명에 따른 반도체소자의 소자분리 방법은 로코스 공정에서 질화막 패턴의 측벽에 질화막으로된 스페이서를 형성하고, 그에 의해 노출되는 반도체기판의 소정두께를 등방성 식각하여 언더컷이 진 트랜치를 형성하여 부피팽창에 따른 스트레스를 감소시키며, 상기 트랜치의 측벽 부분에 질화막 패턴을 형성하여 산화막과 반도체기판의 경계 부분에 산소가 침투하는 것을 방지한 후, 열산화를 실시하여 소자분리 산화막을 형성하였으므로, 반도체기판의 스트레스가 감소되어 격자결함에 따른 누설전류 증가를 방지하여 소자동작의 신뢰성을 향상시킬 수 있으며, 버즈 빅의 크기가 감소되어 고자의 고집적화에 유리하고 공정수율을 향상시킬 수 있는 이점이 있다.As described above, the device isolation method of the semiconductor device according to the present invention forms a spacer of a nitride film on the sidewall of the nitride film pattern in the LOCOS process, and isotropically etches a predetermined thickness of the exposed semiconductor substrate, thereby reducing the undercut. Forming a trench reduces stress due to volume expansion, and forms a nitride film pattern on the sidewall portion of the trench to prevent oxygen from penetrating the boundary between the oxide film and the semiconductor substrate, and thermally oxidizes the device isolation oxide film. Since the stress of the semiconductor substrate is reduced, it is possible to improve the reliability of the device operation by preventing leakage current increase due to lattice defects, and the size of the buzz big is reduced, which is advantageous for high integration of the high pores and improves the process yield. There is an advantage.
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