JPS5961166A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the deterioration of the characteristics of a region for an enhancement-mode type element on the formation of a region for a depletion- mode type element when manufacturing the semiconductor device of E/D constitution. CONSTITUTION:A high-purity GaAs layer 2, an N type AlGaAs layer 3 and an N type GaAs layer 4 are grown on a semi-insulating GaAs substrate 1 through a MBE method or a NOCVD method. A recessed section 2A reaching the GaAs layer 2 from the surface is formed. A film such as a cover film 6 consisting of a silicon dioxide film is formed, and an N type GaAs layer 7 is formed. A photo- resist film 8 is formed on the formation prearranged region of the depletion- mode type element region. The layer 7 and the layer 4 are patterned, and the cover film 6 and the photo-resist film 8 are removed, thus obtaining the region E for the enhancement-mode type element and the region D for the depletion-mode type element.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field of the Invention The present invention relates to an improvement in a method of manufacturing a semiconductor device having a so-called IE/D configuration having an enhancement mode element and a diplenoid mode element.

Prior Art and Problems As is conventionally known, in a semiconductor device having an E/D configuration, elements having different threshold voltages must be formed on the same semiconductor substrate.

To manufacture such semiconductor devices, enhancement and
A semiconductor substrate for mode type elements is used, and regions for depression mode elements are activated by ion implantation and annealing to form E/D regions.

According to this prior art, by performing the annealing treatment for activation, the enhancement layer that has already been formed
This will damage the area for mode type elements.

In a typical integrated circuit, the enhancement mode element area forms the driving circuit portion of switching transistors, etc., so a deterioration in the characteristics of this area will have a considerable negative effect on the entire semiconductor device. will give.

Purpose of the Invention The present invention provides a method for manufacturing a semiconductor device having an E/D configuration.
This is to prevent the characteristics of the enhancement moat type element area from deteriorating when forming the depression moat type element area.

Structure of the Invention In the present invention, a semiconductor layer, a GaAs layer, etc., which forms a heterojunction, is epitaxially grown on a substrate (or a semiconductor layer) in an enhancement moat type element region for forming a driving transistor. GaAs is newly added to the depletion moat type element region for forming a load transistor or resistor using a semiconductor layer.
This method uses epitaxial growth of the semiconductor layer forming the layer or heterojunction.

Embodiments of the Invention FIGS. 1 to 5 are cross-sectional side views of essential parts of a semiconductor device at key process points for explaining embodiments of the present invention, and the following description will be made with reference to these figures. do.

Refer to the first obstacle ■ MBE (Mole
cu l a r 13 e a m E p
IT axy) method or MOCVD (Met
al Organic Chemical V
High-purity GaA3 layer 2 with a thickness of, for example, 3,000 (persons), n-type AlGaAs 1ii3 with a thickness of, for example, 500 (persons),
An n-type GaAs layer 4 having a thickness of, for example, 300 μm is grown.

The substrate thus obtained is coated with an AlGaAs layer 3 and a Ga layer 3 used for an enhancement mode device.
It is provided with a heterojunction consisting of the As layer 4, and also has an impurity concentration profile suitable for use in an enhancement moat type device. Furthermore, AlGaA
The S layer 3 and the GaAs layer 4 have a doping amount of l x 10"
” (cm-3) of impurities are introduced.

Referring to FIG. 2, the photolithography technique described in 1) is applied, and the substrate is etched through the patterned photoresist film 5 to form a recess 2Δ reaching the GaAs layer 2 from the surface. Incidentally, it is optional to use a silicon dioxide film or the like instead of the photoresist film 5 as the etching mask.

Figure 3 No.) 1(i ■) 1st-Register l-11% After removing 5,
Enhancement 1 - On the area where the Mole type element area is planned to be formed (for example, a cup made of silicon dioxide film)
) 196 is formed.

Specifically, L, for example, chemical vapor phase 11 [product 1 Jlcv
It is preferable to form ``zeta silicon dioxide IIQ'' using the method 1) and then ``C pattern'' it using the usual photolithography technique.

■ Using epitaxial growth techniques such as the M13 method or MOCVI method, the thickness can be increased, for example, by
Forms a A s layer 7 in the n-type of humans. This G
aAs bat 7 is for forming a depression moat type element region, and the temperature i's' at which it is formed is Al (J aΔ
s Ifi 3 and the temperature T for growing the GaAs layer 4
It is desirable that G1 be lower than s. For example, Ts=680
C'C), Ts=580('C).In addition, G
The impurity concentration of aΔSI′Fi7 is ~1,8×10
17 (Cm-').

(2) A photoresist l-film 8 is formed on the region where the depression mode type element region is to be formed by applying the usual plating/lithography technique.

Refer to FIG. 4. Patterning of GaAs Fi 7 and GaGaAsii 4 is performed by applying the etching method. Kaa＼
-IQ 6 J The second portion of the GaAs layer 4 has poor crystallinity and can be easily removed.

■ If the cover film 6 and photoresist film 8 are removed, the enhancement mold type element area E will be removed as shown in the picture.
A region for a depression moat type device is obtained.

See Figure 5 ■ After this, the normal process, for example, mesa, engineering, no f ~
After isolation is performed by oxygen ion implantation or oxygen ion implantation, a source electrode SB, a train electrode DE, a gate electrode GE, and other interconnections are formed to complete the transistor.

The source electrode SE and the drain electrode DE are, for example, A u
C; e/A u, etc., and the gate electrode GE is T
' i / P L / to U etc. respectively.

FIG. 6 is a main part L of a semiconductor device for explaining another embodiment.
/J is a cross-sectional side view, and the same parts as those explained with reference to FIGS. 1 to 5 are indicated by the same symbols.

This embodiment differs from the embodiments described with reference to FIGS. 1 to 5 in that the depletion mode element region 1 is formed of a heterojunction.

In FIG. 6, 11 is a high-purity GaA 3 layer with a thickness of, for example, 1000 μm or more, and 12 is an n-type AlGaΔ5R213 with a thickness of, for example, 600 μm. It is a GaAs layer. Note that the amount of impurities in the AlGaAs layer 12 and GaΔsli+3 is l x ] 0
It is about 18 (cm-3). Needless to say, this impurity concentration profile is adjusted to 1 lil so as to lead to the tiplenon moat transistor.

It is easy to manufacture this embodiment, and instead of growing the n-type GaAs layer 7 in the process shown in FIG.
Once f13 is formed, the same process can be followed.

In this example, since both the enhancement mode transistor and the depletion mode transistor are heterojunction devices, selective dry etching can be used, making it possible to fabricate the gates of both l-transistors at the same time. This simplifies the process and is also effective in making the threshold voltage uniform.

In the present invention, in addition to the embodiments described above, an n-type GaAs layer may be grown by epitaxy and used instead of a semiconductor layer that forms various bondings over several days.

Effects of the Invention In the present invention, when manufacturing a semiconductor device with an E/D configuration, a semiconductor layer for forming an enhancement mode element region is formed on a substrate (or a semiconductor layer), and then,
A recess is formed in the semiconductor layer to expose a part of the surface of the semiconductor layer (or the semiconductor layer), and a semiconductor layer is epitaxially formed to form a region for a depletion moat type element in the recess. 1, and when removing the semiconductor layer for forming the region for the depletion mode type device, the enhancement layer 1-1 and the region for the mode 1 type device cannot be affected by -1-i'/ ! ! J is done in 4 degrees, so this kind of half-zn body F
Lj cannot be damaged by the driving l-run source or the enhancement type element region which is JU& which greatly affects the characteristics of j.

[Brief explanation of the drawing]

Figures 11 to 1 illustrate an embodiment of the present invention.
() - Key points of the 4' conductor device at the key point of the culm 1゛11
FIG. 6 is a side view of a main part of a semiconductor device for explaining another embodiment. In the figure, I is a semi-insulating GaΔS substrate, 2 is 1rIJ
Purity G a As IFi, 3 is n-type A l (J
a A s layer, 4 is an n-type c 2 A s layer, 5 is)
, r l-・shi・dis-IIQ, 6 is a cover film, 7 is an n-type GaAs layer, 8 is a photoresist film, E is an enhancement mode type device area, and D is a depletion mode type device area. , SE is a source electrode, DB is a train electrode, and GE is a gate electrode. Patent Applicant Fujitori Co., Ltd. Representative Patent Attorney Kugobe Tamamushi (3 others) Figure 1 Figure 2 A Figure 3 Figure 4 E D5

Claims (1)

[Claims] When manufacturing a semiconductor device having the structure I/l), a semiconductor layer for forming an enhancement mode 1 type element region is formed on a substrate (or a semiconductor A recess is formed in the body layer to expose the -93 surface of the substrate (or semiconductor layer), and a semiconductor layer is epitaxially grown to form a region for a depression mode type 1 element in the recess. 1. A method for manufacturing a semiconductor device, characterized by including steps.