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JPH0294663A - Semiconductor device and its manufacturing method - Google Patents

Semiconductor device and its manufacturing method

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Publication number
JPH0294663A
JPH0294663A JP63247608A JP24760888A JPH0294663A JP H0294663 A JPH0294663 A JP H0294663A JP 63247608 A JP63247608 A JP 63247608A JP 24760888 A JP24760888 A JP 24760888A JP H0294663 A JPH0294663 A JP H0294663A
Authority
JP
Japan
Prior art keywords
semiconductor
gaas
etched
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63247608A
Other languages
Japanese (ja)
Inventor
Takuji Sonoda
琢二 園田
Kazuo Hayashi
一夫 林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP63247608A priority Critical patent/JPH0294663A/en
Priority to DE3932277A priority patent/DE3932277A1/en
Publication of JPH0294663A publication Critical patent/JPH0294663A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/815—Bodies having stress relaxation structures, e.g. buffer layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y20/00—Nanooptics, e.g. quantum optics or photonic crystals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02387—Group 13/15 materials
    • H01L21/02395—Arsenides
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02455—Group 13/15 materials
    • H01L21/02463—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02494—Structure
    • H01L21/02496—Layer structure
    • H01L21/02505—Layer structure consisting of more than two layers
    • H01L21/02507—Alternating layers, e.g. superlattice
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/02—Structural details or components not essential to laser action
    • H01S5/026—Monolithically integrated components, e.g. waveguides, monitoring photo-detectors, drivers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
    • H01S5/00—Semiconductor lasers
    • H01S5/20—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers
    • H01S5/22—Structure or shape of the semiconductor body to guide the optical wave ; Confining structures perpendicular to the optical axis, e.g. index or gain guiding, stripe geometry, broad area lasers, gain tailoring, transverse or lateral reflectors, special cladding structures, MQW barrier reflection layers having a ridge or stripe structure
    • H01S5/227—Buried mesa structure ; Striped active layer
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/82—Heterojunctions
    • H—ELECTRICITY
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    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
    • H10F39/10—Integrated devices
    • H10F39/103—Integrated devices the at least one element covered by H10F30/00 having potential barriers, e.g. integrated devices comprising photodiodes or phototransistors
    • H—ELECTRICITY
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    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • H10F71/1276—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising growth substrates not made of Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/10—Semiconductor bodies
    • H10F77/14—Shape of semiconductor bodies; Shapes, relative sizes or dispositions of semiconductor regions within semiconductor bodies
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    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/01—Manufacture or treatment
    • H10H20/011—Manufacture or treatment of bodies, e.g. forming semiconductor layers
    • H10H20/013—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials
    • H10H20/0133—Manufacture or treatment of bodies, e.g. forming semiconductor layers having light-emitting regions comprising only Group III-V materials with a substrate not being Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10H—INORGANIC LIGHT-EMITTING SEMICONDUCTOR DEVICES HAVING POTENTIAL BARRIERS
    • H10H20/00—Individual inorganic light-emitting semiconductor devices having potential barriers, e.g. light-emitting diodes [LED]
    • H10H20/80—Constructional details
    • H10H20/81—Bodies
    • H10H20/811—Bodies having quantum effect structures or superlattices, e.g. tunnel junctions
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials

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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Optics & Photonics (AREA)
  • Nanotechnology (AREA)
  • Materials Engineering (AREA)
  • Electromagnetism (AREA)
  • Geometry (AREA)
  • Biophysics (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Semiconductor Lasers (AREA)

Abstract

PURPOSE:To reduce crystal defects of a hetero-epitaxial film by a method wherein a first semiconductor is provided with a semiconductor element formed on a second semiconductor on a region which has been selectively etched partially. CONSTITUTION:An Si epitaxial layer 4 is formed on an Si substrate 1; a superlattice 3, in succession, undoped GaAs 5 and n-type GaAs 6 are grown continuously; a high-temperature annealing operation is executed. After that, the Si substrate 1 and the Si epitaxial layer 4 in a required part are etched selectively by using an etchant such as sulfuric acid or the like in such a way that only Si is etched and that GaAs is not etched. In succession, a protective film 8 is formed; after that, an Si element 9 having a memory function of Si is formed on the Si epitaxial layer 4. Thereby, a peak intensity of photoluminescence in a part where Si in a substratum has been removed and in a part where it has not been removed amounts to 5:1; defects in the part where the Si has been removed can be reduced.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は、互いに格子定数の異なる半導体間でのエピ
タキシ膜（ペテロエピタキシ膜）上に半導体素子を形成
してなる半導体装置およびその製造方法に関し、特に装
置の性能向上に関するものである。[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor device in which a semiconductor element is formed on an epitaxial film (petero epitaxy film) between semiconductors having different lattice constants, and a method for manufacturing the same. , especially regarding improving the performance of the device.

〔従来の技術〕[Conventional technology]

現在量も注目されているヘテロエビ膜としては、Ｓｉ基
板上へ成長したＧａＡｓ膜があり、Ｓｉ素子とＧａＡｓ
素子とを同一基板上に形成し、Ｓｉ素子よりもさらに高
速でかつＳｔと同等の集積度をもたせたＩＣの開発、又
Ｓｔ上にＧａＡｓの太陽電池を作製し、ＧａＡｓ上の太
陽電池より軽量化することが活発に研究されている。A type of heterogeneous film that is currently attracting attention is a GaAs film grown on a Si substrate.
Developed an IC that is faster than a Si element and has the same degree of integration as an St element, and is lighter than a GaAs solar cell by fabricating a GaAs solar cell on an St element. is being actively researched.

以下、Ｓｔ上のＧａＡｓ膜を例にとり、従来のへテロ接
合エビを用いた半導体装置について第５図を用いて説明
する。Hereinafter, a semiconductor device using a conventional heterojunction layer will be explained using FIG. 5, taking a GaAs film on St as an example.

通常、ｓｉとＧａＡｓとは格子定数（Ｓｔを基準として
４％異なる）、並びに熱膨張係数（ＳｔがＧａＡｓの約
４倍大きい）が太き（異なり、Ｓｌ上にＧａＡｓを成長
した場合、それらの差による結晶欠陥がＧａＡｓ中に存
在する。これらの結晶欠陥を低減するために、通常は第
５図に示す如（、Ｓｉ基板１とＧａＡＳ２との間に、結
晶欠陥がＧａＡｓ　Ｚ中へ侵入するのを防ぐためのＧａ
Ａｓ　／　Ａ　Ｉ　Ｇ　ａ　Ａ　ｓもしくはＱ　ａ　Ａ
　ｓ　／　Ｉ　ｎ　Ｇ　ａ　Ａ３等による超格子層３を
挿入している。現状では上記超格子を導入し、かつ成長
後高部アニールすることにより、最も良いＧａＡＳ結晶
が得られている。Normally, Si and GaAs have a large lattice constant (4% different from St) and a large coefficient of thermal expansion (St is about 4 times larger than GaAs). Crystal defects due to differences exist in GaAs. In order to reduce these crystal defects, as shown in FIG. Ga to prevent
As / A I G a A s or Q a A
A superlattice layer 3 made of s/In Ga A3 or the like is inserted. At present, the best GaAS crystal can be obtained by introducing the above-mentioned superlattice and annealing the upper part after growth.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら、それでも従来のへテロエビ膜では結晶欠
陥密度が１ｏ　ｂ　ｃＩａ−１と多く、ヘテロエビ膜を
用いた半導体装置を作製する場合、例えばＳｌ上にＧａ
ｐｓを成長させて光学的素子を形成する場合、実使用上
、このヘテロエビ膜の結晶欠陥密度を１０３ｃｍ−”以
下にする必要があり、更に大幅な結晶欠陥の低減化を必
要とするという問題点があった。However, the crystal defect density in the conventional hetero-Episode film is as high as 1obcIa-1, and when manufacturing a semiconductor device using the hetero-Episode film, for example, Ga
When growing PS to form an optical element, in practical use, it is necessary to reduce the crystal defect density of this heteroepic film to 10 cm or less, and there is a problem in that it is necessary to further significantly reduce the crystal defects. was there.

本発明は上記問題点を解消するためになされたもので、
Ｓｔ基板上に成長されたＧａＡｓ膜等、ヘテロエピ膜の
結晶欠陥を大幅に減少し、実使用上充分な特性を有する
ヘテロエビ膜を用いた半導体装置およびその製造方法を
提供することを目的とする。The present invention was made to solve the above problems, and
It is an object of the present invention to provide a semiconductor device using a heteroepitaxial film, such as a GaAs film grown on a St substrate, which has sufficient characteristics for practical use, and a method for manufacturing the same.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る半導体装置およびその製造方法は、Ｓｔ等
の第１の半導体上に第１の半導体と格子定数の異なるＧ
ａＡｓ等の第２の半導体を成長し、第１の半導体を選択
エツチングにより部分的に除去し、この第１の半導体を
エッチ除去した部分の第２の半導体上に素子を形成する
ようにしたものである。A semiconductor device and a method for manufacturing the same according to the present invention provide a first semiconductor such as St, and a first semiconductor having a lattice constant different from that of the first semiconductor.
A device in which a second semiconductor such as aAs is grown, the first semiconductor is partially removed by selective etching, and an element is formed on the second semiconductor in the area where the first semiconductor is etched away. It is.

〔作用〕[Effect]

本発明においては、下地のＳｔ等第１の半導体を選択エ
ッチした部分上のＧａＡｓ等第２の半導体上にＧａｐｓ
素子等の半導体素子を形成することにより、ＧａＡｓ等
第２の半導体は下地半導体の影響をほとんど受けること
がないので格子定数の差に起因する第２の半導体の結晶
欠陥を大幅に低減できる。In the present invention, Gaps are formed on the second semiconductor such as GaAs on the portion where the first semiconductor such as the underlying St is selectively etched.
By forming a semiconductor element such as a semiconductor element, the second semiconductor such as GaAs is hardly affected by the underlying semiconductor, so crystal defects in the second semiconductor caused by differences in lattice constants can be significantly reduced.

〔実施例〕〔Example〕

以下、本発明の実施例を図について説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図は本発明の第１の実施例による半導体装置を示し
、図において、１はＳｔ基板、３はＧａＡ　ｓ　／　Ａ
　Ｉ　Ｇ　ａ　Ａ　ｓ　、　Ｇ　ａ　Ａ　ｓ　／　Ｉ　
ｎ　Ｇ　ａ　Ａ　ｓ　。FIG. 1 shows a semiconductor device according to a first embodiment of the present invention, in which 1 is an St substrate, 3 is a GaAs/A
I Ga As, Ga As / I
nGaAs.

もしくはＧ　ａ　Ａ　ｓ　／　Ｚ　ｎ　Ｔ　ｅ等の超格
子層、４はＳｉエビ層、５はノンドープＧａＡｓ層、６
はｎ型ＧａＡｓ層、７はＳｉ基板１．Ｓｉエビ層４が選
択的にエツチングされたエツチング孔、８は保護膜、９
はＳｉメモリ素子、１０はＧａＡｓ演算素子である。Or a superlattice layer such as GaAs/ZnTe, 4 is a Si shrimp layer, 5 is a non-doped GaAs layer, 6
is an n-type GaAs layer, 7 is a Si substrate 1. Etched holes in which the Si shrimp layer 4 is selectively etched, 8 is a protective film, 9
1 is a Si memory element, and 10 is a GaAs arithmetic element.

まず、第１図（ａｌに示す如く、Ｓｉ基板ｌ上にＳｉエ
ピＪｉ４を形成し、その後超格子３、続いてノンドープ
ＧａＡｓ５．ｎ型ＧａＡｓ６をＭＢＥ（Ｍｏｌｅｃｕｌ
ａｒ　Ｂｅａａ＋　Ｉ！ｐｉｔａｘｙ）もしくはＭＯＣ
ＶＤ　（Ｍｅｔａｌ　Ｏｒｇａｎｉｃ　Ｃｈｅｍｉｃａ
ｌ　Ｖａｐｏｒ　Ｄｅｐｏｓｉｔｉｏｎ）ｇより連続的
に成長し、高温アニールを行う、その後、必要な部分の
Ｓｉ基板１及びｓｉエビ層４をｓｉのみがエツチングさ
れＧａＡｓはエツチングされないような硫酸等のエッチ
ャントを用いて選択的にエツチングする（同図（ｂｌ）
、続いて、全面に５１０ｇ、ｓｉＮ、もしくはＳｉＯ，
／５ｉＮ（７）保護膜８を形成する（同図（Ｃ１）、続
いて、Ｓｌデバイスを形成すべき部分の保護膜８及びＧ
ａＡｓエピ膜５．６を選択エッチにより除去し、露出さ
れた部分の８１エピ１！４上にＳｔのメモリ機能を持つ
Ｓｔ素子９を作製する（同図（ｄ））。Ｓｉ素子９形成
後、再び全面に上記保護膜と同一の保護膜８を形成する
。しかる後にＧａＡａ素子を形成すべき部分のｎ型Ｇａ
Ａｓ６を選択的に露出させ、その部分にＧａＡｓ演算素
子１０を形成する（同図（８１）、最後に、Ｓｉ素子部
９のボンディングボッドの穴開けを行い、本実施例によ
る半導体装置の製造工程を完了する（同図（ｆ））。First, as shown in FIG.
ar Beaa+ I! pitaxy) or MOC
VD (Metal Organic Chemica
l Vapor Deposition)g, and high-temperature annealing is performed. After that, necessary portions of the Si substrate 1 and the Si layer 4 are etched using an etchant such as sulfuric acid that etches only the Si but not the GaAs. Selective etching (same figure (bl)
Then, 510g of SiN or SiO was applied to the entire surface.
/5iN (7) forming the protective film 8 ((C1) in the same figure), then forming the protective film 8 and G on the part where the Sl device is to be formed.
The aAs epitaxial film 5.6 is removed by selective etching, and an St element 9 having an St memory function is fabricated on the exposed portion of the 81 epitaxial film 1!4 (FIG. 4(d)). After forming the Si element 9, a protective film 8 identical to the above protective film is again formed on the entire surface. After that, the n-type Ga in the part where the GaAa element is to be formed is
As6 is selectively exposed and the GaAs arithmetic element 10 is formed in that part ((81) in the same figure.Finally, a hole is made for the bonding board of the Si element part 9, and the manufacturing process of the semiconductor device according to this example is completed. ((f) in the same figure).

このようにして得られた半導体装置のＧａＡｓ膜５．６
の、下地のＳｉを除去した部分と除去していない部分の
フォトルミネンセンスのピーク強度は５：１となり、こ
れはＳｉを除去した部分で欠陥が減少していることを明
らかに示している。GaAs film 5.6 of the semiconductor device thus obtained
The peak intensity of photoluminescence between the area where the underlying Si was removed and the area where it was not removed was 5:1, which clearly shows that the number of defects is reduced in the area where Si was removed. .

又、ＧａＡｓ素子１０として試作した、ゲート長０．５
μｍ、全ゲート幅２００μｍである電界効果トランジス
タ（ＦＥＴ）の相互コンダクタンス（ｇ、）は５０ｍ５
と、通常のＧａＡｓ上に成長したＧａＡｓＦＢＴと同等
の性能を示した。In addition, a prototype GaAs device 10 was manufactured with a gate length of 0.5.
The transconductance (g, ) of a field effect transistor (FET) with a total gate width of 200 μm is 50 m5
It showed performance equivalent to that of GaAsFBT grown on normal GaAs.

このように、本実施例によれば、Ｓｔを部分的にエツチ
ングすることにより、その部分のＧａＡｓ層を、下地の
Ｓｔの影響をほとんど受けることな（格子定数及び熱膨
張係数の差に起因する結晶欠陥の大幅に低減されたもの
とすることができ、この部分のＧａＡｓ上にＧａＡｓ素
子を形成し、その他の部分に成長したＧａＡｓはこれを
選択エッチしてＳｔを露出し、その部分にＳｉ素子を形
成することにより、Ｓｔ基板上にＳｉ素子と、実使用に
充分な特性を有するＧａＡｓ素子とを同時に形成するこ
とができ、高速演算、大容量メモリの半導体装置が得ら
れる。In this way, according to this example, by partially etching the St, the GaAs layer in that part is hardly affected by the underlying St (due to the difference in lattice constant and coefficient of thermal expansion). A GaAs element is formed on the GaAs in this part, and the GaAs grown in other parts is selectively etched to expose St, and Si is formed in that part. By forming the device, a Si device and a GaAs device having sufficient characteristics for practical use can be simultaneously formed on the St substrate, and a semiconductor device with high-speed operation and large-capacity memory can be obtained.

尚、Ｓｉデバイス９にイオン注入を用いる場合は、Ｇａ
Ａｓエビ成長前に所定領域にイオン注入した後熱処理を
完了し、その後ＧａＡｓエビ成長を行う、又、上記ノン
ドープＧａＡｓ５．ｎ−ＧａＡｓ　５の代わりに太陽電
池もしくはレーザダイオード仕様のエビを形成すれば、
Ｓ１デバイスと太陽電池もしくはレーザダイオードとの
共合が可能である。もちろん、Ｇａｐｓデバイスのみを
作製することも可能であることは言うまでもなく、例え
ば太陽電池の場合には高性能で軽量なＧａＡＳ太陽電池
を作製することができる。Note that when using ion implantation for the Si device 9, Ga
Before the growth of As, ions are implanted into a predetermined region, heat treatment is completed, and then GaAs is grown. If a shrimp with solar cell or laser diode specifications is formed instead of n-GaAs 5,
Coupling of the S1 device with a solar cell or a laser diode is possible. Of course, it goes without saying that it is also possible to manufacture only a Gaps device, and for example, in the case of a solar cell, a high performance and lightweight GaAS solar cell can be manufactured.

又、上記第１の実施例では、ｓｉがあまり抵抗率を大き
くできないことから、Ｓｌ素子９．ＧａＡｓ素子ｌＯか
らＳｉ基板１に若干のリーク電流が流れるが、この点を
改善する装置として第２図に示すものが考えられる。こ
の第２図に示す本発明の第２の実施例では、Ｓｉ基板１
とＳｉエピ層４との間に、５ｉと格子整合する絶縁体で
あるＣａＦ、の層１６を新たに形成し、他は第１の実施
例と同様の構成とする。このようにすれば、上記第１の
実施例の効果に加えて、更にＱ　ａ　Ｆ　を層１６によ
り上記リーク電流を防止することができるという効果が
ある。尚、ＣａＦ、以外に、ＳｒＦ！。In addition, in the first embodiment, since Si cannot increase the resistivity very much, the Sl element 9. Although some leakage current flows from the GaAs element IO to the Si substrate 1, the device shown in FIG. 2 can be considered as a device to improve this point. In the second embodiment of the present invention shown in FIG.
A layer 16 of CaF, which is an insulator lattice-matched to 5i, is newly formed between the layer 5i and the Si epitaxial layer 4, and the other structure is the same as that of the first embodiment. In this case, in addition to the effect of the first embodiment, there is an effect that the leakage current can be prevented by the Q a F layer 16. In addition to CaF, SrF! .

サファイア等を用いても同様の効果が得られる。A similar effect can be obtained by using sapphire or the like.

次に、第３図を用いて本発明の第３の実施例による半導
体装置について説明する。第３図（ａ）は第１図に示し
た装置と同様の工程により選択的にＳｉ基板１及びＳｉ
エビ層４をエツチングした段階を示しており、この後に
エツチングした側に金メツキ層１１を成長しく同図（ｂ
ｌ）、ＧａＡｓエビ上にソース電橋１２．ゲート電極１
３．ドレイン電極１４を有するトランジスタを形成する
（同図（Ｃ））。Next, a semiconductor device according to a third embodiment of the present invention will be described using FIG. FIG. 3(a) shows the Si substrate 1 and the Si substrate being selectively removed by a process similar to that of the apparatus shown in FIG.
This figure shows the stage where the shrimp layer 4 has been etched, and the gold plating layer 11 is then grown on the etched side.
l), source electric bridge on GaAs shrimp 12. Gate electrode 1
3. A transistor having a drain electrode 14 is formed (FIG. 3(C)).

本実施例によれば、上記第１の実施例のようなＧａＡｓ
エビ層の結晶欠陥の低減の効果に加えて、金メツキ層１
１により熱抵抗を低減することも可能であるという効果
があり、特に高出力ＧａＡｓ電界効果トランジスタに有
効である。又、エツチングされた部分をメツキ１１によ
り補強する構造となっており、上記第１の実施例のもの
より強度的にも向上する。According to this embodiment, GaAs as in the first embodiment described above is used.
In addition to the effect of reducing crystal defects in the shrimp layer, the gold plating layer 1
1 has the effect that it is also possible to reduce thermal resistance, and is particularly effective for high-power GaAs field effect transistors. Further, the etched portion is reinforced with plating 11, and the strength is also improved compared to that of the first embodiment.

更に、Ｓｉ基板１及びＳｔエピ４をエツチングして露出
された超格子層３のＧａＡｓ面上にＧａＡｓと格子整合
のとれる材料を結晶成長することも可能である。第４図
はこのような場合の本発明の第４の実施例による半導体
装置の製造工程を示す図である０本実施例ではエツチン
グして露出した面上にＧａＡｓ層５．６を再成長してお
り、上面と再成長した面とに電界効果トランジスタを作
製し、ソース１２．ドレイン１４．ゲート１３をそれぞ
れ貫通孔１５により電気的に接続することにより、同一
面積に２倍の素子を集積することが可能である。又、再
成長エビを太陽電池もしくはレーザダイオード等の仕様
にすることにより、ＧａＡｓ電界効果トランジスタとレ
ーザダイオード。Furthermore, it is also possible to grow crystals of a material that is lattice-matched to GaAs on the GaAs surface of the superlattice layer 3 exposed by etching the Si substrate 1 and the St epitaxial layer 4. FIG. 4 is a diagram showing the manufacturing process of a semiconductor device according to a fourth embodiment of the present invention in such a case. In this embodiment, a GaAs layer 5.6 is regrown on the surface exposed by etching. A field effect transistor is fabricated on the top surface and the regrown surface, and the source 12. Drain 14. By electrically connecting the gates 13 through the through holes 15, it is possible to integrate twice as many elements in the same area. In addition, GaAs field effect transistors and laser diodes can be produced by making regrown shrimp into solar cells or laser diodes.

太陽電池、ペルチェ素子等とを同時に作製することも可
能である。It is also possible to manufacture solar cells, Peltier elements, etc. at the same time.

尚、上記第３．第４の実施例ではＧａＡｓ素子を作製す
る方法についてのみ説明したが、Ｓｌ素子を同時に作製
する方法も上記第１の実施例と同様のプロセスにより可
能であることは言うまでもない。In addition, the above 3. In the fourth example, only the method for manufacturing the GaAs element has been described, but it goes without saying that a method for simultaneously manufacturing the Sl element is also possible using the same process as in the first example.

又、上記実施例では全てＳｔ上のＧａＡＳを例にとり記
述したが、本発明は他の互いに格子定数の異なる材料間
に適用できることは言うまでもない６例えば、［ｎＰ−
ＧａＡｓや、Ｉ　ｎ、　Ｇ　ａ　ｕ−ｘ＞ＡｓのＸ−０
，５３以外のＩ　ｎＧａＡｓ−ＧａＡｓなどの材料が挙
げられる。Furthermore, although all of the above embodiments have been described using GaAS on St as an example, it goes without saying that the present invention can be applied to other materials having different lattice constants.6For example, [nP-
X-0 of GaAs, In, Ga ux > As
, 53, such as InGaAs-GaAs.

〔発明の効果〕〔Effect of the invention〕

以上のように、本発明に係る半導体装置およびその製造
方法によれば、Ｓｔ等の第１の半導体上にＧａＡｓ等の
第２の半導体を成長後、選択的に下地の第１の半導体を
エツチングし、その上部の第２の半導体を用いて素子を
形成するようにしたので、結晶欠陥の少ない高品質なヘ
テロ接合エビ膜上に、ＧａＡｓ上に成長したＧａＡｓ等
のホモ接合エピ膜上に作製した高速ＧａＡｓ素子、高性
能光素子等の素子と同等の性能を有する素子を作製する
ことができる効果がある。As described above, according to the semiconductor device and the manufacturing method thereof according to the present invention, after growing the second semiconductor such as GaAs on the first semiconductor such as St, the underlying first semiconductor is selectively etched. However, since the device is formed using the second semiconductor on top of the second semiconductor, it can be fabricated on a high-quality heterojunction epitaxial film with few crystal defects and on a homojunction epitaxial film such as GaAs grown on GaAs. This has the effect of making it possible to fabricate a device having performance equivalent to that of a high-speed GaAs device, a high-performance optical device, or the like.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の第１の実施例による半導体装置の製造
工程断面図、第２図は本発明の第２の実施例による半導
体装置の製造工程断面図、第３図は本発明の第３の実施
例による半導体装置の製造工程断面図、第４図は本発明
の第４の実施例による半導体装置の製造工程断面図、第
５図は従来のヘテロエピ膜を説明するための断面図であ
る。 図中、１はｓｉ基板、３は超格子層、４はＳｔエビ層、
５はノンドープＧａＡｓ層、６はｎ型ＧａＡｓ層、７は
エツチング孔、８は保護膜、９はＳｔメモリ素子、１０
はＧａＡｓ演算素子、１１は金メツキ層、１２，１３．
１４はそれぞれソース、ゲート、ドレイン電極、１５は
貫通孔である。 尚、図中同一符号は同−又は相当部分を示す。1 is a cross-sectional view of the manufacturing process of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view of a manufacturing process of a semiconductor device according to a second embodiment of the present invention, and FIG. FIG. 4 is a cross-sectional view of the manufacturing process of a semiconductor device according to the fourth embodiment of the present invention, and FIG. 5 is a cross-sectional view of a conventional hetero epitaxial film. be. In the figure, 1 is a Si substrate, 3 is a superlattice layer, 4 is a St shrimp layer,
5 is a non-doped GaAs layer, 6 is an n-type GaAs layer, 7 is an etching hole, 8 is a protective film, 9 is an St memory element, 10
11 is a gold plating layer, 12, 13 .
14 is a source, gate, and drain electrode, respectively, and 15 is a through hole. Note that the same reference numerals in the figures indicate the same or corresponding parts.

Claims (2)

【特許請求の範囲】[Claims] （１）第１の半導体上に該第１の半導体と格子定数の異
なる第２の半導体を成長してなる半導体装置において、 上記第１の半導体が部分的に選択エッチングされた領域
上の上記第２の半導体上に形成された半導体素子を備え
たことを特徴とする半導体装置。(1) In a semiconductor device in which a second semiconductor having a lattice constant different from that of the first semiconductor is grown on a first semiconductor, the first semiconductor is located on a region where the first semiconductor is partially selectively etched. 1. A semiconductor device comprising a semiconductor element formed on a semiconductor of No. 2. （２）第１の半導体上に該第１の半導体と格子定数の異
なる第２の半導体を成長する工程と、上記第１の半導体
を部分的に選択エッチングする工程と、 該選択エッチングした領域上の上記第２の半導体上に半
導体素子を形成する工程とを含む半導体装置の製造方法
。(2) a step of growing a second semiconductor having a lattice constant different from that of the first semiconductor on the first semiconductor; and a step of selectively etching the first semiconductor; and on the selectively etched region. forming a semiconductor element on the second semiconductor.
JP63247608A 1988-09-30 1988-09-30 Semiconductor device and its manufacturing method Pending JPH0294663A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP63247608A JPH0294663A (en) 1988-09-30 1988-09-30 Semiconductor device and its manufacturing method
DE3932277A DE3932277A1 (en) 1988-09-30 1989-09-27 SEMICONDUCTOR DEVICE AND METHOD FOR THEIR PRODUCTION

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63247608A JPH0294663A (en) 1988-09-30 1988-09-30 Semiconductor device and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH0294663A true JPH0294663A (en) 1990-04-05

Family

ID=17166038

Family Applications (1)

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Country Status (2)

Country Link
JP (1) JPH0294663A (en)
DE (1) DE3932277A1 (en)

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WO2010075606A1 (en) * 2008-12-29 2010-07-08 Shaun Joseph Cunningham Improved photo-voltaic device

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US6699395B1 (en) 2000-10-18 2004-03-02 Storage Technology Corporation Method of forming alignment features for conductive devices
US6508674B1 (en) 2000-10-18 2003-01-21 Storage Technology Corporation Multi-layer conductive device interconnection
US6431876B1 (en) * 2000-10-18 2002-08-13 Storage Technology Corporation Conductive trace interconnection
US6657237B2 (en) * 2000-12-18 2003-12-02 Samsung Electro-Mechanics Co., Ltd. GaN based group III-V nitride semiconductor light-emitting diode and method for fabricating the same

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WO2010042981A1 (en) * 2008-10-14 2010-04-22 Shaun Joseph Cunningham Photo-voltaic device
WO2010075606A1 (en) * 2008-12-29 2010-07-08 Shaun Joseph Cunningham Improved photo-voltaic device

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DE3932277A1 (en) 1990-04-05
DE3932277C2 (en) 1992-07-09

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