JPH03276640A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To reduce that chippings and cracks are produced at a dicing operation by a method wherein a compound semiconductor layer is formed on a silicon single-crystal wafer by a heteroepitaxial growth operation, a recessed part formed by selectively etching its dicing region is filled with silicon, the dicing region is cut and pellets are separated. CONSTITUTION:SiO2 is deposited on a GaAs layer 2 which has been formed on an Si single-crystal substrate 1 by a heteroepitaxial growth operation; an SiO2 mask 10 used to form an opening in a dicing region is formed. Then, the GaAs layer 2 is etched by an RIE method by using a chlorine-bised gas; Si of the substrate 1 is exposed; recessed parts 11 to be used as dicing regions are formed. Then, a single-crystal layer is grown in the recessed parts 11 by a selective epitaxial growth operation of Si; the recessed parts 11 are filled completely; dicing regions 12 are formed. Lastly, the SiO2 mask 10 is removed; a MESFET or the like of an LDD structure is integrated in the GaAs layer 2; after that, the dicing regions 12 are cut in the direction of arrows; individual pellets surrounded by an Si sidewall layer 3 are separated.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention relates to a semiconductor device and a method for manufacturing the same.
In particular, it relates to the structure and manufacturing method of a compound semiconductor device formed on a silicon substrate or a composite device of a compound semiconductor device and a silicon semiconductor device.

(Prior Art) Silicon (Si 2 ) is extremely superior as a single crystal substrate for electronic devices. In recent years, other semiconductor materials have been epitaxially grown on the 81 substrate in order to provide additional electronic properties not found in silicon. Conventionally, GaAs/Si is a typical compound semiconductor grown heteroepitaxially on a Si substrate.

However, there is a lattice constant mismatch of about 4% between GaAs and S; For this reason, Ga
When stacking As, warpage of nearly 60 μl occurs, and
Misfit dislocations (dislocations based on lattice mismatch) generated at the interface between the Si wafer and the compound semiconductor layer extend into the compound semiconductor layer, causing deterioration of device characteristics.

In addition, compound semiconductors such as GaAs have weaker interatomic bonding strength than Si semiconductors, so they are prone to chipping (dicing) during dicing (dicinQ), which separates wafers into pellets.
Tipping chips and cracks occur, and dislocations and distortions caused by the dicing fracture layer are factors that reduce the reliability of subsequent devices.

<Problems to be Solved by the Invention> As mentioned above, when compound semiconductors are stacked on an 81 substrate by heteroepitaxial growth, warpage and misfit of the substrate occur due to mismatching of lattice constants between Si and the compound semiconductor. There is a problem that dislocation occurs.

In addition, in compound semiconductors such as GaAs, the interatomic bonding force is
chipping and cracking are likely to occur during dicing, and there are also dislocations and distortions caused by the dicing fracture layer, which deteriorate device characteristics and reliability.
In order to alleviate this problem, attempts have been made to increase the width of the dicing region, but this has the problem of reducing the yield of pellets for wafers.

Furthermore, when an acid-based treatment solution is used for post-treatment after dicing the wafer and separating it into pellets, there is a problem in that compound semiconductors such as GaAs that are not exposed on the sidewalls are etched.

The object of the present invention is to provide a compound semiconductor layer or a silicon layer formed by heteroepitaxial growth on a silicon single crystal substrate.
In a semiconductor device and its manufacturing method in which a compound semiconductor layer including a selective epitaxial layer is used as an element formation region, warpage and dislocation of the substrate are reduced, chipping and cracking during dicing are reduced, and dislocation caused by a dicing fracture layer is reduced. It is an object of the present invention to provide a semiconductor device and a method for manufacturing the same, which can reduce the effects of distortion and strain on an element, thereby improving element characteristics and reliability, and increasing element yield.

[Structure of the Invention] <Means for Solving the Problems and Their Effects> The semiconductor device I of the present invention is made of a silicon single crystal substrate and a compound semiconductor formed on the substrate by epitaxial growth, or a compound semiconductor and a silicon semiconductor. a sidewall layer formed on the substrate by selective epitaxial growth and made of a semiconductor having a diamond structure or a zincblende structure and surrounding a sidewall of the island-like element formation region. This is a semiconductor device characterized by the following.

The sidewall layer surrounding the island-shaped element formation region is a part of the dicing region left on the sidewall of the pellet separated by dicing, and the semiconductor forming the sidewall layer is diamond-structured Si, C5, or It is preferable to use a compound semiconductor having a Ge or zincblende structure, which is different from the element forming region.

Since the compound semiconductor layer in the element formation region on the Si wafer is separated by a dicing region made of a semiconductor of a different composition, warpage and dislocation of the substrate are significantly reduced compared to the conventional technology.

In addition, since the semiconductor in the dicing area is made of a material such as Si, which has stronger mechanical strength than the compound semiconductor in the element forming area, large chippings and cracks do not occur during dicing, and dislocations and distortions caused by the dicing fracture layer do not remain. The remaining sidewall layer is sandwiched between the sidewall layers of Si, etc., and has almost no influence on the compound semiconductor layer in the element formation region. In the post-processing process after dicing, etc.
It can function as a protective film for the element formation region.

The method for manufacturing a semiconductor device of the present invention is described in claim 1.
In the semiconductor device described in Section 1, the manufacturing method is performed when the sidewall layer is made of silicon, that is, when the dicing region is an S-selective epitaxial layer.

That is, the manufacturing method of the present invention includes a step of forming a compound semiconductor layer by heteroepitaxial growth on a silicon single crystal wafer, and selectively etching a dicing region of the compound semiconductor layer or a predetermined portion of the dicing region and an element forming region. A semiconductor device comprising the steps of: forming a recess exposing the wafer surface; filling the recess with silicon by selective epitaxial growth; and cutting a dicing region into pellets. This is the manufacturing method.

(Example) As a first example of the present invention, a case will be described in which an IC (64 kbit SRAM) is manufactured on GaAs-onSI. FIG. 1 is a cross-sectional view of the IC using the present invention.

In the figure, reference numeral 1 is a Si single crystal substrate, and reference numeral 2 is a Ga substrate formed on the substrate 1 by heteroepitaxial growth.
An island-shaped element formation region made of As, and reference numeral 3 denote a sidewall layer made of selective epitaxial Si surrounding the sidewalls of the element formation region 2.

The IC is formed in the element formation region 2, but the main components LDD (LightlyDo
Only a MES FET with a structure of ``ppedDrain'' is illustrated as a representative element. That is, reference numerals 4 and 5 denote a drain region and a source region, respectively, and a channel region 6 sandwiched between the two head regions is provided in the surface layer of the GaAs layer 2. Reference numerals 7, 8 and 9 are train, source and gate electrodes, respectively.

Next, a method for manufacturing the above IC will be explained with reference to FIG.

As shown in FIG.
OCVD (Metal Organic Cheni)
An undoped GaAs layer (
Thickness 1. 2a at 500°C and 700°C
It is formed by two-stage heat treatment at ℃.

Subsequently, vanadium (V)-doped Ga A was
A three-layer (insulating layer) 2b is formed to a thickness of 1.5 μl, and an undoped GaAs layer 2C is formed to a thickness of 1.0 μl.

Reference numeral 2 represents these stacked GaAs layers.
When the warpage of the wafer was measured in this state, it was 58 μι. At this stage, some wafers were extracted and ICs were formed using a conventional manufacturing method for comparison.

Next, as shown in the same figure (b), C
Deposit 5in2 on the GaAs layer by VD method, and
E P (Photo Engraving Pro
cess ) method to open the 5i in the dicing area.
A mask 10 of n2 is formed.

Next, as shown in the same figure (c), using chlorine-based gas,
The GaAs layer 2 is etched by RIE (reactive ion beam etching) to expose the Si of the substrate 1 and form a recess 11 that will become a dicing region. At this time, the IC chip (bellet) size l is 4 ml,
The IQ 11 of the recess 11 is 25 μm. At this stage, the chip size was set to 0.1.1 and 1011 for investigation.
A wafer having a chip size of 41Il was manufactured in parallel with a wafer having a chip size of 41Il.

Next, as shown in FIG.
selective epitaxial growth (800°C, Si C1,...
A single crystal layer is grown to a thickness of 3.5 μm using HCi, H2> to completely fill the recess 11 and form a dicing region 12. Here, the warpage of the wafers including those for investigation and the dislocation density on the surface of the GaAs layer 2 were measured (measurement results will be described later).

Finally, as shown in the same figure (e), a 5in2 mask 10
is removed, and an LDD is formed on the Ga A3 layer 2 by a known method.
After integrating the MES FETs, etc. of the structure, a dicing area (25 μm wide) with a 15 μm wide diamond blade (
The Si selective epitaxial layer 12 is cut in the direction of the arrow shown by the wavy line, and separated into individual pellets surrounded by the Si sidewall layer 3. Next, post-treatment (cleaning with H2SO4, H2O2 liquid) is performed.

Next, the results of an investigation into the relationship between wafer warpage and dislocation density with respect to chip size will be described below with reference to FIG. The test wafer was a wafer that had completed the manufacturing process shown in FIG. 2(d), that is, a 2-inch diameter Si wafer on which a GaAs layer in the element formation region and a Si layer in the dicing region were epitaxially grown. be.

The horizontal axis in FIG. 3 is the chip size on the wafer, which is expressed by the length of the -side of the element formation area (square) separated into islands. Point R on the horizontal axis is the chip size on the wafer. For convenience, the case of a conventional wafer in which a GaAs layer is stacked over the entire surface and the dicing area is not etched is shown. The vertical axis on the left side represents the surface dislocation density (pieces/cn2), and the vertical axis on the right side represents the warpage (μl) of the substrate (2 inch wafer). The broken line a connecting the ○ marks in the figure represents the chip size and surface dislocations. The broken line connecting the density and the points marked with △ indicates the relationship between the chip size and the warp of the substrate.

As is clear from FIG. 3, the wafer of the present invention in which the Ga AS layer is separated into islands by eight layers is
Both surface dislocation density and substrate warpage are significantly reduced compared to conventional wafers in which layers are not separated into islands. Furthermore, in the present invention, the finer the separation, that is, the smaller the chip size, the fewer dislocations and warpage occur.

FIG. 4(a) shows an IC manufactured by removing a part of the wafer and forming it by the conventional manufacturing method at the stage shown in FIG. 2(a).
Figure (b) shows the distribution of the threshold voltage (Vth) of the MBS FET in the MBS FET, and the same figure (b) shows the distribution of Vth according to the manufacturing method of the present invention. ), and the total number of test elements is 274 in the case of the conventional example.
In the case of the example of the present invention, the number is 312.

As is clear from Fig. 4, in the conventional example, 0 to 0.4 (V
) was distributed in the range of 0.2 to 0 in the present invention example.
．． 4 (V) or less, the variation is reduced,
Improved operating characteristics. This is considered to be due to a decrease in dislocation density and strain.

Next, as a second embodiment of the present invention, an AI with a wavelength of 700 nn
We conducted a demonstration using a GaAS visible light emitting diode.
FIG. 5 is a schematic cross-sectional view of this light emitting diode.

Reference numeral 51 indicates the plane orientation (ioo), and the thickness is 300 μm.
It is a Si single crystal substrate. On the substrate 51, MOCVD
A GaAs layer 52 with a thickness of 0.2μ formed by the method
a, n AloAoGa (, @A
sAS layer b and thickness 2.8. un's pA 1 o:n
G a QJ5A three layers 52C are laminated.

Reference numeral 53 denotes the GaAs laminated film (element formation region)
Surrounding 52 is a sidewall layer consisting of a 51 selective epitaxial layer having a thickness of 5 μN. The sidewall layer 53 is a part of the dicing area left on the sidewall of the laminated film 52 when a 2-inch wafer patterned with a chip size of 300×300 μm2 and a dicing area width of 25 μm is diced with a blade of 15 μl width. Reference numeral 54 indicates a p-GaAs layer, and reference numbers 55 and 56 each indicate an Au-GaAs layer.
The electrode is made of Cr and Au.

FIG. 6 shows the current-light output characteristics of the above-mentioned light emitting diode, where the horizontal axis is the anode current (IA) and the vertical axis is the light output (IIW). Symbol a is the example of the present invention, and b is the conventional example. As is clear from the figure, the 1f flow of the light emitting diode using the present invention is shown.
The light output characteristics are linear up to about 250IIA, but
In the diode using the conventional method, linearity deteriorates from about 160 nA. This difference is considered to be due to the cracks that entered the AiGaAS layer and the difference in dislocation density.

In addition, in the conventional method, GaAs and AJGaAS are brittle, so the dicing region width was set to 50 μm and cutting was performed using a 20 μm wide blade, but in the case of the present invention example in which Si crystal is used in the dicing region, chipping and As cracks are reduced, the dicing area width can be narrowed to 25 μl and the blade width can be narrowed to 15 μm as described above.
This effect manifests itself in increased yield for devices with small chip sizes. For example, when manufacturing 300x300 μm 2 diodes using the 2-inch diameter wafer of the second embodiment, the yield increases by approximately 15%.

Next, a compound semiconductor element and an S
An example of a composite semiconductor device equipped with one semiconductor element will be outlined. FIG. 7 is a sectional view for explaining the main manufacturing process of the device. As shown in FIG. 3A, a compound semiconductor layer 72 is formed on a Si single crystal substrate 71 by heteroepitaxial growth. Next, SiO
2 is deposited, and S in the dicing area and the element forming area is
A 5 in 2 mask 80 having an opening in a portion that will become an i-element formation region is formed. Next, the Ga AS layer which will become the dicing region and the Si element formation region is selectively etched away by RIE to form a recessed portion in which the Si substrate 71 is exposed. Next, the recess is filled by 81 selective epitaxial process to form a dicing region 75 made of S1 single crystal, a Si element formation region 76, and a compound semiconductor element formation region 77. Next, as shown in FIG. 6B, the 5in2 film 80 is removed, a predetermined wafer process is carried out, and the compound semiconductor element 77a and the Si semiconductor element 76a are mounted in their corresponding areas, and then the dicing area 75 is cut. Te5iQ
It separates into pellets surrounded by a wall layer 73.

This device is, for example, OB I C (Opto-Elec).
A hybrid IC (tron+cIC) that has an 81 semiconductor element part and a compound semiconductor element part in the same element.
It can be used to fabricate complex integrated circuits.

As mentioned above, in the present invention, the warpage of the substrate is significantly reduced, making it possible to put heteroepitaxial techniques to use on large-diameter Si substrates, and also enabling reduction projection exposure, which makes it possible to significantly reduce costs. .

In addition, the S1 sidewall layer remaining on the sidewall of the pellet has the function of a protective film, especially when an acid-based processing solution is used during post-processing after device dicing.
a If AS is exposed, it will be etched, but the presence of the S1 sidewall layer can prevent this. Furthermore, the strain and dislocations caused by the fracture layer during dicing cause the Si and Ga sidewalls to deteriorate.
It is absorbed at the AS interface and has the effect of suppressing a decrease in reliability of the element forming region.

[Effects of the Invention] As described in detail so far, according to the semiconductor device and the manufacturing method thereof of the present invention, warpage and dislocation of a substrate in which a compound semiconductor layer is laminated on a Si substrate are reduced, and the substrate is reduced during dicing. It reduces the occurrence of chipping and cracking, reduces the effects of dislocations and distortions caused by the dicing fracture layer on the device, improves device characteristics and reliability, and improves productivity by increasing device yield. It became possible to improve.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention, FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor device according to the first embodiment, and FIG. Ga A
Figure 4 shows the chip size dependence of the dislocation density on the 3rd surface.
The figure shows the GaAs ME of the conventional example and the first example IC.
A diagram showing the distribution of the threshold voltage of S FET, FIG. 5 is a cross-sectional view of the semiconductor device of the second embodiment of the present invention, and FIG. 6 is a current-light output characteristic diagram of the semiconductor device of the second embodiment. FIG. 7 is a sectional view showing the manufacturing process of the composite IC of the present invention. 1.51.71...Si single crystal substrate, 2,52°7
2... Compound semiconductor layer (element formation region), 3゜53
．． 73...5iQ11 wall layer, 11...recessed part,
12°75...Dicing area, 76...81
Semiconductor element formation region, 77... Compound semiconductor element formation region.

Claims (1)

[Scope of Claims] 1. A silicon single crystal substrate, and an island-shaped element formation region made of a compound semiconductor or a compound semiconductor and a silicon semiconductor formed on the substrate by epitaxial growth;
a sidewall layer formed on the substrate by selective epitaxial growth and made of a semiconductor having a diamond structure or a zincblende structure surrounding the sidewall of the island-shaped element formation region. 2. Forming a compound semiconductor layer on a silicon single crystal wafer by heteroepitaxial growth, and selectively etching a dicing region of the compound semiconductor layer or a predetermined portion of the dicing region and the element formation region to expose the wafer surface. The semiconductor according to claim 1, comprising the steps of forming a recess, filling the recess with silicon by selective epitaxial growth, and separating into pellets by cutting a dicing region. Method of manufacturing the device.