JPS5953713B2 - integrated circuit device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device including a non-volatile insulated field effect transistor or a high-density memory cell array constructed using the non-volatile insulated field effect transistor.

Conventionally, semiconductor non-volatile memory devices include, for example, FAMOS (floating gate avalanche mechanism M05) having a floating gate, MNOS (metal nitride oxide semiconductor) containing a silicon nitride film as a gate insulating film, and MAOS (metal PROM (alumina oxide semiconductor) etc.
Programmable read-only memory) devices are known, but all of these devices have drawbacks such as high data write voltage, slow write speed, and difficulty in miniaturization from the viewpoint of voltage resistance. In addition, the number of times data can be read is limited to 108 to 1010 times.

Furthermore, there are also problems with erasing data, such as FAMOS devices requiring ultraviolet rays or X-rays, and MNOS devices also requiring considerably high voltage. Therefore, conventional semiconductor nonvolatile memory elements constructed using such devices have the disadvantages that miniaturization is difficult, there is a limit to increasing the density of the element, and power consumption is large. Furthermore, there is also an inconvenience in handling that data erasing methods differ depending on the type of element. This invention was made in view of the above circumstances, and its purpose is to:
An object of the present invention is to provide a semiconductor nonvolatile memory device that is small in size, has high performance, has low power characteristics, and is easy to use.

In order to achieve such an object, an integrated circuit device according to the present invention uses an insulated field effect transistor in which a source and a drain are formed vertically, and a ferroelectric material is interposed in the gate insulating film. .

Hereinafter, an integrated circuit device according to the present invention will be explained in detail using examples. FIGS. 1a and 1b are a top view and a sectional view taken along the line AN of FIG. 1, showing an embodiment in which an integrated circuit device according to the present invention is applied to an insulated field effect transistor.

Note that the interlayer insulating film shown in FIG. 2B is omitted in FIG. In the figure, an n+ high concentration layer 2 as a source is formed inside a P type silicon substrate 1, and a P type epitaxial layer 3 having a desired concentration and a thickness of 1 to 5 μm is formed on top of the n+ layer 2. An opening 5 is formed from the main surface 4 of the P-type silicon substrate 1, where the P-type epitaxial layer 3 is located, to the n+ high concentration layer 2. It is desirable that the terminal end of the opening 5 be included in the n+ high concentration layer 2 without deviating from it. A ferroelectric film 6 is provided on the side wall of the opening 5 as a gate insulating film. Examples of ferroelectric materials include BaTiO3 and SrTiO.
3. As long as a known ferroelectric material such as a perovskite system such as PLZT, a Rothsiel salt system, or a KDP system is used, and it has stable hysteresis in the spontaneous polarization in the direction perpendicular to the film surface of the ferroelectric film 6, even a single crystal material can be used. It may also be a polycrystalline material. Note that this gate insulating film is not composed only of the ferroelectric film 6, but can also have a sandwich structure or a two-layer structure in combination with, for example, a gate oxide film SiO2 of a normal MOS structure. Further, a highly concentrated layer 7 is formed to include the edge of the opening 5 provided on the main surface 4 of the silicon substrate. This n+ high concentration layer 7 corresponds to a drain, and is arranged in the vertical direction with an appropriate spacing from the n+ high concentration layer 2 as a source. Both n+ high concentration layer 7
, 2 immediately below the side wall of the opening portion becomes the channel region 8. Further, a gate electrode 9 is provided on the ferroelectric film 6 constituting the gate insulating film, and an n+ high concentration layer 10 for taking out the source electrode is formed from the n+ high concentration region 2 to the main surface 4. There is. The drain, gate, and source electrode terminals 11, 12, and 13 are made of a conductor layer such as aluminum, and the detailed structure is not shown in the figure.
They are connected to the drain, gate, and source, respectively, through contact holes provided in the interlayer insulating film. FIG. 2 shows typical operating characteristics of the insulated field effect transistor having the above structure.

In the figure, the horizontal axis is the gate voltage V6, and the vertical axis is the source-drain current 1s0. As is clear from the figure, the 150-V6 characteristic curve exhibits a hysteresis characteristic, and there are two stable states of conduction between the source and drain: conduction and non-conduction. This state is maintained even when the gate voltage is removed, and even when the power is turned off, so it can be applied to nonvolatile memory, which will be described later. Furthermore, these two stable states can be controlled by the gate voltage VG. That is, as shown in FIG. 2, there is a critical gate voltage V6l, and V6>V6
1, the ferroelectric film 6 receives an electric field greater than the coercive electric field and is positively polarized with respect to the silicon interface. As a result, an inversion layer is induced in the channel region 8, and the source and drain become conductive. This conduction state is caused by the gate voltage V
Even if ferroelectric film 6 is removed, it is maintained by the spontaneous polarization of ferroelectric film 6. On the other hand, there is another critical voltage V6O, and by applying a negative voltage V6<V6O, the ferroelectric film 6 is reversed to negative polarization with respect to the silicon interface.
As a result, the inversion layer in the channel region 8 disappears and the source
There is no conduction between the drains. Therefore, the gate voltage V
As long as V6O<V6 and V6l are maintained, the two stable states will not be destroyed and this state will be maintained even after removing the gate voltage. Two critical gate voltages V
6l, VGO is determined by device structure parameters such as the composition, film thickness, and formation conditions of the ferroelectric film 6.

FIGS. 3a and 3b are a top view and an AA'' cross-sectional view of another embodiment in which the integrated circuit device according to the present invention is applied to an insulated field effect transistor, and are the same or equivalent parts as in FIG. 1. The same symbols will be used and detailed explanation will be omitted.

In FIG. 3, the gate insulating film includes a ferroelectric film 6a corresponding to the ferroelectric film 6 in FIG. 1, and a SiO2 insulating film 14.
It is composed of: In this case, the ferroelectric film 6a
is limited to a local area on the side wall of the opening 5, one end of which is n+
Extending over the drain region consisting of the high concentration layer 7,
The other end terminates in the middle of the channel region 8 and is a high concentration resistant layer 2.
It has not reached the source region consisting of. A SiO2 insulating film]4 covers the side wall of the opening 5, including the part where the ferroelectric film 6a extends and the part where the ferroelectric film 6a does not extend. A gate electrode 9 is formed thereon. The composition, thickness, etc. of the ferroelectric film 6a are not particularly different from those of the ferroelectric film 6 shown in FIG. FIG. 4 shows a typical 180-6 characteristic curve of the insulated field effect transistor having the above structure. In FIG. 3, the action of the ferroelectric film 6a is exactly the same as the action of the ferroelectric film 6 in FIG. 1, but since the ferroelectric film 6a covers only a part of the channel region 8, The inversion layer formed by the positive 5 polarization of the ferroelectric film 6a is induced only in the channel region 8a. Therefore, in order for the source and drain to become conductive in this state, as shown in FIG. 4, a voltage of threshold voltage VT that induces an inversion layer in the channel region 8b is applied to the gate. That is, it is necessary to set V6>VT. Here, the threshold voltage Ve is set to a value smaller than the critical gate voltage V6l as explained in FIG. On the other hand, the conditions for inverting the ferroelectric film 6a to negative polarization are the same as in the embodiment shown in FIG.

In this way, in the gate voltage range V6O<V6<V6l that does not destroy the two stable states, the gate voltage range V6O<V6<V1 that achieves a non-conducting state between the source and drain for any stable state Because of the existence of this, the range of applications is wider than that shown in Figure 1. In addition,
In the above-mentioned embodiments, only the case where the ferroelectric film 6a extends over the drain region and does not reach the source region is explained, but conversely, the ferroelectric film 6a extends over the source region. , the above-mentioned operation is exactly the same even in the case where the transistor is located apart from the drain region.

Furthermore, in the above embodiment, the SiO2 insulating film 14 was interposed between the ferroelectric film 6a and the side wall of the opening 5;
After forming the ferroelectric film 6a directly on the side wall of the opening 5, the SiO2 insulating film 14 may be formed thereon. Furthermore, a sandwich structure in which a ferroelectric film is sandwiched between SiO2 insulating films can also be used. FIGS. 5A, 5B, and 5C are a top view, a sectional view taken along the line A--N, and an equivalent circuit diagram thereof, showing an embodiment in which the integrated circuit device according to the present invention is applied to a nonvolatile memory cell array.

That is, two insulated field effect transistors (indicated by 15 in FIG. 5) similar to those shown in FIG.
They are arranged in a matrix of rows and three columns, and the sources 2b made of the n+ high concentration layer in each row have a common continuous structure, and this is used as, for example, a word line 16. Furthermore, the drains 7b made of high concentration layers in each column are made into a common continuous structure, and this is used as, for example, a data line 17. Further, the gate electrodes 9 in each row are commonly connected by a conductor layer 18 made of aluminum, for example, and this is used as a word line 19. In this case, each ferroelectric film 6 and the conductor layer 18 are separated by an interlayer insulating film 20. Further, it is advantageous to avoid a structure in which the drain 7b forming the data line 17 and the conductor layer 18 forming the word line 19 are parallel to each other in order to secure an operating margin. In the nonvolatile memory cell array having the above configuration, data reading and writing operations are performed as follows.

That is, first, among the two stable states of the insulated field effect transistor 5 as explained in FIG. In addition, when not accessing, all data lines 17 and word lines 16 are set in a floating state, and the word line 19 is set in a floating state or within the range of V6O<V6 and V6l. If so, the selected word line 1
6 as the ground level, and the similarly selected data line 17
By supplying a current to the word line 16 and the data line 17, the memory cell at the intersection of the word line 16 and the data line 17, that is, the insulated field effect transistor 15, is selected, and it is determined whether or not a voltage drop occurs on the selected data line 17. Therefore, the conduction or non-conduction state of the insulated field effect transistor 15, that is, the data “1”
, "0" can be identified. In this case, peripheral circuits of the memory cell array, such as a selection circuit for selecting a desired word line and data line, a current supply circuit to the data line, and an output signal detection circuit, are as follows. Known memory circuit technology can be applied.When writing data next, the word line 16 and data line 17 of the selected memory cell are grounded, and the other word lines 16 remain in a floating state. The unselected data line 17 is set to the same potential according to the potential of the word line 19 of the selected memory cell.Then, the potential V6 of the selected word line 19 is set to be equal to or higher than V6l or lower than V6O. By doing so,
゜“1” or “0” is written. Data written in this way does not disappear even when the power is turned off. In other words, non-volatile storage can be realized. Figure 6 shows A, b and C.
These are a top view, an AN sectional view, and an equivalent circuit diagram showing another embodiment in which the integrated circuit according to the present invention is applied to a nonvolatile memory cell array.

This is an example in which insulated field effect transistors 21 having basically the same configuration as that shown in FIG. This is, for example, a word line 16 as a continuous structure. Furthermore, the drains 7C in each column have a common continuous structure, and this is used as, for example, a data line 17. Further, the gate electrodes 9 in each row are commonly connected via an interlayer insulating film 20 by a conductor layer 18 made of, for example, aluminum, and this is used as a word line 19. In the non-volatile memory cell array having the above configuration, all data lines 17 and word lines 6 are set in a floating state or at ground level during non-access, and word lines 19 are set in the range of V6O<V6 and V1. Preferably, V6=0.

Of the two stable states of the insulated field effect transistor 21 as explained in FIG. When performing this, the selected word line 16 is set to the ground level. By supplying a current to the selected data line 17, the intersection points of the selected word line 16 and the selected data line 17 are memorized. A cell, that is, an insulated field effect transistor 21, is selected, and depending on the presence or absence of a voltage drop on the selected data line 17, the cell is in a conductive or non-conductive state, that is, "゜1-゜゜0.
” can be identified. On the other hand, when writing data, the word line 16 and data line 1 of the selected memory cell
7 is set at ground level, and the other word lines 16 and data lines 17 are set in a floating state. Next, set the potential of the word line 19 of the selected memory cell to V6l or higher or V
By making it less than GO, "1" or "0" is written. In this case, the selected word line 16 does not necessarily have to be at ground level, but rather is left in a floating state, which can be expected to increase the write margin. The stored information written in this way does not disappear even when the power is turned off, and nonvolatile storage is realized.
The voltages V6l, V6O, and VT that determine the read and write voltages of such nonvolatile memory are determined by the structural parameters of the insulated field effect transistor 21, especially the ferroelectric film 6.
It is determined by the thickness and composition of a and the thickness of the SiO2 insulating film 14.

For example, the ferroelectric film 6a is made of PLZT to a thickness of 0.5 μm.
By configuring it to about m, V6l=5 to 10 (V)
, a value of V6O=-5 to -10 (V) is obtained. Further, the threshold voltage V1 can be easily set from 0.5 to 1.0 (V
) can be obtained. Further, the time required for writing data is mainly determined by the time required for polarization reversal of the ferroelectric film 6a, and a value of about 0.3 μSec has been obtained for the ferroelectric film 6a having the above-mentioned structural parameters. Note that it is also possible to have a structure similar to the above-described embodiment and to make the source 2C, that is, the word line 16 common to all cell arrays, but in this case, the write margin becomes slightly narrower.

In addition, in the above-mentioned embodiments, only the memory cell array with 2 rows and 3 columns was described, but the present invention is not limited to this, and can be similarly applied to any memory cell array with n rows and m columns. Of course you can get it. Furthermore,
The cell density of the memory cell array in the above embodiment is, for example, 1 to 2.5 Mb/Cm2 based on the 3 μm rule.
, extremely high values of 2 to 4 Mb/Cln2 can be obtained with the 2 μm rule, and 8 to 15 Mb/Cm2 with the 1 μm rule.

As explained above, according to the integrated circuit device of the present invention, the source and drain of the insulated field effect transistor are arranged vertically, and the gate insulating film is interposed with a ferroelectric material. It becomes possible to realize nonvolatile memory with low power consumption and high reliability.

That is, by making the source and drain have a vertical structure,
Not only can the area occupied by the element be reduced, but also the area of wiring constituting the storage plane can be reduced, and extremely high storage cell density can be obtained. Furthermore, by forming the gate insulating film to include a ferroelectric material, the threshold voltage of the field effect transistor can be controlled by utilizing the hysteresis of spontaneous polarization of the ferroelectric material. Therefore, it is possible to write data at a low voltage, the data is held extremely stably, and the write time is short. Therefore, MNOS. F.A.M.
Compared to other conventionally used semiconductor nonvolatile memory elements such as OS, it has various excellent effects such as high speed, low power consumption, high reliability, and ease of use.

[Brief explanation of drawings]

1a and 1b are a top view and an AA'' cross-sectional view of an embodiment of an integrated circuit device according to the present invention, FIG. 2 is an operational characteristic diagram of the integrated circuit device of FIG. 1, and FIGS. 3a and 3 are b
4 is a top view and an AA'' cross-sectional view showing another embodiment of the integrated circuit device according to the present invention, FIG. 4 is an operational characteristic diagram of the integrated circuit device of FIG. 3, and FIGS. A top view showing still another embodiment of the integrated circuit device according to
Cross-sectional view and its equivalent circuit diagram, Fig. 6 A, b and C
FIG. 2 is a top view, a sectional view taken along the line A--N, and an equivalent circuit diagram thereof, showing another embodiment of the integrated circuit device according to the present invention. 1... P-type silicon substrate, 2, 7, 10...
... n+ high concentration layer, 3 ... P type epitaxial layer, 4 ... main surface of P type silicon substrate, 5 ...
...Opening part, 6, 6a... Ferroelectric film, 8
, 8a, 8b...channel area, 9...
・Gate electrode, 11...Drain electrode terminal, 1
2... Gate electrode terminal, 13... Source electrode terminal, 14... SiO2 insulating film, 15,
21...Insulated field effect transistor, ]6,
19... Word line, 17... Data line, 18... Conductor layer, 20... Interlayer insulating film, 2b, 2C... Source, 7b, 7C...
···drain.

Claims (1)

[Scope of Claims] 1. A first high concentration impurity region having a second conductivity type provided in a silicon substrate having a first conductivity type, and a first high concentration impurity region extending from the main surface of the silicon substrate. a second high-concentration impurity region that is in contact with the main surface of the silicon substrate and includes an edge of the opening and has a second conductivity type; and a side wall of the opening. a gate insulating film formed thereon and containing at least a portion of a ferroelectric material, and a gate electrode covering the gate insulating film; and the second high concentration impurity region constitutes the other source or drain, and the first high concentration impurity region and the second high concentration impurity region of the silicon substrate. 1. An integrated circuit device comprising an insulated field effect transistor whose channel region is a region between. 2. A first high concentration impurity region having a second conductivity type provided in a silicon substrate having a first conductivity type, and an opening formed from the main surface of the silicon substrate to the first high concentration impurity region. a second high-concentration impurity region that is in contact with the main surface of the silicon substrate, includes an edge of the opening, and has a second conductivity type; The gate insulating film includes a gate insulating film partially containing a ferroelectric material, and a gate electrode covering the gate insulating film, and the first high concentration impurity region constitutes either a source or a drain. and the second high concentration impurity region constitutes the other one of the source or the drain, and a region between the first high concentration impurity region and the second high concentration impurity region of the silicon substrate. A plurality of insulated field effect transistors serving as channel regions are arranged in a matrix as memory cells, and the first high concentration impurity region of each insulated field effect transistor constituting either a row or a column of the matrix is electrically the second high concentration impurity regions of each insulated field effect transistor constituting the other row or column of the matrix are electrically connected, and the second high concentration impurity region of each insulated field effect transistor forming the other row or column of the matrix is The gate electrodes of each insulated field effect transistor constituting the transistor are electrically connected, and the first high concentration impurity region, the gate electrode, and the second high concentration impurity region are connected to a memory cell selection line and a data readout line. An integrated circuit device comprising a memory cell array as a write line.