KR20240095043A - Non-volatile memory device and its operating method - Google Patents

Abstract

This technology relates to non-volatile memory devices and methods of operating the same. A non-volatile memory device of the present technology includes a memory cell including a write transistor and a ferroelectric read transistor; a write word line connected to the gate terminal of the write transistor; a write bit line connected to the source terminal of the write transistor; a read word line connected to a source terminal of the ferroelectric read transistor; and a read bit line connected to the drain terminal of the ferroelectric read transistor, wherein the drain terminal of the write transistor may be connected to the gate terminal of the ferroelectric read transistor. This technology can realize low-power, high-density, and non-destructive DRAM by realizing 2T0C FeDRAM based on the silicon CMOS process using dielectric materials.

Description

Non-volatile memory device and its operating method}

The present invention relates to a non-volatile memory device and a method of operating the same, and more specifically, to a non-volatile memory device using a ferroelectric material and a method of operating the same.

DRAM (Dynamic Random Access Memory) has a simple structure and is easy to integrate, so it is used as a large-capacity temporary memory device. DRAM forms the mainstream of Korea's semiconductor industry and is a very large product in the semiconductor business.

Meanwhile, DRAM has a problem of information destruction caused by physical overlap of read and write paths. For example, during the reading and writing process, the part where voltage is applied and the part where current flows overlap and the information is destroyed, necessitating a process of rewriting the information in the memory cell. This creates the need for a non-destructive memory operation method.

Additionally, DRAM does not have a long retention time due to the leakage current limit of the capacitor. Unlike SRAM (Static Random Access Memory) or Flash Memory, DRAM experiences a phenomenon in which information stored in memory cells is lost over time (so-called volatility), which is caused by DRAM's memory cells. This is because it consists of one transistor and one capacitor, and natural leakage of data stored in the capacitor occurs. Therefore, in order to prevent data loss, a refresh operation is performed to rewrite the information stored in the memory cell at regular intervals. Refresh can be performed by amplifying data by activating the word line to an active state at least once within the retention time of each memory cell. This refresh consumes additional power.

Accordingly, in order to improve memory device performance, research is needed to enable non-destructive path implementation and increase retention time.

Embodiments of the present invention provide a non-volatile memory technology that solves the disadvantages of existing DRAM, which inevitably has a low retention time and a destructive operation method, by implementing a non-destructive path and using a ferroelectric material.

Meanwhile, other unspecified purposes of the present invention will be additionally considered within the scope that can be easily inferred from the following detailed description and its effects.

A memory cell including a write transistor and a ferroelectric read transistor according to an embodiment; a write word line connected to the gate terminal of the write transistor; a write bit line connected to the source terminal of the write transistor; a read word line connected to a source terminal of the ferroelectric read transistor; and a read bit line connected to the drain terminal of the ferroelectric read transistor, wherein the drain terminal of the write transistor may be connected to the gate terminal of the ferroelectric read transistor.

The drain terminal of the write transistor is connected to the gate terminal of the ferroelectric read transistor at the storage node, so that a polarization direction can be induced in the ferroelectric material of the ferroelectric read transistor when the write transistor is turned on.

The ferroelectric material may be hafnium-zirconium oxide.

The memory cells are formed on silicon CMOS logic circuits integrated through a FEOL process on a silicon substrate, and may be vertically stacked through a BEOL process.

The memory cells may be stacked in the order in which the write transistor is arranged on the ferroelectric read transistor.

ITZO capable of a BEOL process can be applied as a channel layer to the write transistor, and HZO and ITZO capable of a BEOL process can be applied as an insulating layer and a channel layer, respectively, to the ferroelectric read transistor.

In the BEOL process of forming the ferroelectric read transistor, the insulating layer may be formed using ion beam sputtering.

The gate structure of the write transistor has a structure in which a gate electrode as a conductive layer, an insulator film as an insulating layer, and an amorphous oxide semiconductor film as a channel layer are stacked, and the gate structure of the ferroelectric read transistor has a gate electrode as a conductive layer and a ferroelectric as an insulating layer. The film and channel layer may have a structure in which amorphous oxide semiconductor films are stacked.

The ferroelectric film is any one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide), and the amorphous oxide semiconductor film is ITZO ( It may be any one selected from the group consisting of Indium-Tin-Zinc Oxide), IGZO (Indium-Gallium-Zinc Oxide), InO (Indium Oxide), and ZnO (Zinc Oxide).

The ferroelectric read transistor may be a single gate transistor.

The ferroelectric read transistor may be a double gate transistor including a bottom gate and a top gate.

Electrons are accumulated in the channel by the write voltage applied to the bottom gate of the ferroelectric read transistor, and accordingly, an electric field is applied to the ferroelectric material to store polarization, and the stored polarization is maintained by the ferroelectric material to change the operating voltage. Data is stored, and an inversion channel is formed by an erase voltage applied to the bottom gate and the top gate. Accordingly, an electric field is applied to the ferroelectric material to change polarization and erase data.

Additionally, as a method of operating a non-volatile memory device according to an embodiment, the non-volatile memory device includes: a memory cell including a write transistor and a ferroelectric read transistor; a write word line connected to the gate terminal of the write transistor; a write bit line connected to the source terminal of the write transistor; a read word line connected to a source terminal of the ferroelectric read transistor; and a read bit line connected to the drain terminal of the ferroelectric read transistor, wherein the drain terminal of the write transistor is connected to the gate terminal of the ferroelectric read transistor, and the first read bit line is connected to the write word line and the write bit line. Applying a write control voltage to the write transistor and applying a second write control voltage to the ferroelectric read transistor through the read word line and the read bit line to write a polarization direction to the ferroelectric material of the ferroelectric read transistor; and applying a first read control voltage to the write transistor through the write word line and the write bit line and applying a second read control voltage to the ferroelectric read transistor through the read word line and the read bit line to achieve the polarization. It may include reading data from the drain current of the ferroelectric read transistor that varies depending on direction.

This technology enables non-destructive path implementation that solves the problem of information being destroyed due to overlapping read and write paths of a memory device.

Additionally, this technology solves the problem of additional power consumed due to refresh due to the short retention time of existing DRAM.

This technology also solves the integration problem at the same time.

Additionally, this technology can expand the memory window by effectively applying voltage to the ferroelectric.

In addition, unlike existing DRAM, this technology has a long data retention time and is non-volatile, enabling low-power and high-efficiency operation with lower power consumption.

In addition, this technology can achieve high integration by using it as a storage device for multi-level cells that can store multiple states rather than the two states of 1 or 0 in existing DRAM, as the operating voltage can be adjusted to various states. there is.

1 shows a schematic diagram of one memory cell of a non-volatile memory device according to one embodiment.
Figure 2 shows a top view and a cross-sectional view of one memory cell of a non-volatile memory device according to one embodiment.
Figure 3 shows a cross-sectional view of a monolithic 3D integrated structure of 2T0C FeDRAM according to one embodiment.
Figure 4 shows write and read operations of a 2T0C FeDRAM cell according to one embodiment.
Figure 5 shows an example of a cell array implementation of 2T0C FeDRAM according to an embodiment.
Figure 6 shows a cross-sectional and top view of a 3D integrated 2T0C FeDRAM cell according to one embodiment.
Figure 7 is a graph comparing the characteristics of 2T0C FeDRAM according to an embodiment and a conventional DRAM type.
Figure 8A shows a structural diagram of a 2T0C FeDRAM cell using a double gate according to one embodiment.
FIG. 8B shows the transfer curve of the FeFET used in the read transistor of the 2T0C FeDRAM of FIG. 8A for each case according to the body potential.
Figure 8C is a schematic diagram of the operating principle of an amorphous oxide semiconductor film-based FeFET according to an embodiment.
Figure 8D is a schematic diagram of the write state and erase state of an amorphous oxide semiconductor film-based FeFET according to an embodiment.
Figure 9 shows the results of non-volatile characteristics and durability characteristics of FeFET used in a read transistor of 2T0C FeDRAM according to an embodiment.
Figure 10 shows non-volatile results of multi-level state 2T0C FeFRAM according to one embodiment.
The attached drawings are intended as reference for understanding the technical idea of the present invention, and are not intended to limit the scope of the present invention.

The above objects, other objects, features and advantages of the present invention will be easily understood through the following preferred embodiments related to the attached drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to enable the disclosed content to be more thorough and complete and to sufficiently convey the spirit of the present invention to those skilled in the art, without any intention other than to provide convenience of understanding.

In this specification, when it is mentioned that certain elements or lines are connected to the target element block, it includes not only direct connection but also indirect connection to the target element block through some other element.

In addition, the same or similar reference signs in each drawing indicate the same or similar components as much as possible. In some drawings, the connection relationships between elements and lines are only shown for effective explanation of technical content, and other elements or circuit blocks may be further provided.

Each embodiment described and illustrated herein may also include its complementary embodiment, and details regarding the general operation of the display device and circuits or elements for performing such general operation are provided in order not to obscure the gist of the present invention. Please note that this is not explained in detail.

1 shows a schematic diagram of one memory cell of a non-volatile memory device according to one embodiment. As shown in FIG. 1, the memory cell has a 2T0C structure and includes a write transistor (Wtr) and a ferroelectric read transistor (Rtr). The write transistor (Wtr) may be a Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET). The ferroelectric read transistor (Rtr) may be a Ferroelectric Field-Effect Transistor (FeFET). This is FeDRAM (Ferroelectric DRAM), which uses ferroelectric materials instead of the capacitors used in existing Si CMOS-based DRAM. The disadvantages of existing DRAM, which has a low retention time and a destructive operation method, are solved by implementing a non-destructive path, and a ferroelectric material with a theoretically infinite retention time is used.

As shown in the figure, as metal lines, a write word line (WWL), a write bit line (WBL), a read word line (RWL), and a read bit line (RBL) are connected to each transistor. Specifically, the write word line (WWL) is connected to the gate terminal of the write transistor (Wtr), and the write bit line (WBL) is connected to the source terminal of the write transistor (Wtr). The read word line (RWL) is connected to the source terminal of the ferroelectric read transistor (Rtr), and the read bit line (RBL) is connected to the drain terminal of the ferroelectric read transistor (Rtr).

And, the two transistors are connected to each other with the storage node (SN) in between. In detail, the drain terminal of the write transistor (Wtr) is connected to the gate terminal of the ferroelectric read transistor (Rtr) at the storage node (SN).

The 2T0C FeDRAM shown in the figure uses a ferroelectric material, which maintains polarization in the ground state below the Curie temperature, and is applied as an insulating layer (Cox, Rtr) of the read transistor of the FeDRAM. Due to the ferroelectric material applied as this insulating layer, the storage of information in 2T0C FeDRAM takes place in the read transistor, and once stored, the information has an expected retention value of about 10 years due to the characteristics of the ferroelectric material.

As a ferroelectric material, Hf-based ferroelectric material can be applied. For example, any one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide) may be applied.

ITZO (Indium-Tin-Zinc Oxide), a type of oxide semiconductor, may be applied as the channel layer of each transistor. ITZO has low leakage current and high mobility, making it an advantageous material for low-power operation. Meanwhile, ITZO is an example, and various amorphous oxide semiconductors such as IGZO (Indium-Gallium-Zinc Oxide), InO (Indium Oxide), and ZnO (Zinc Oxide) may be applied.

Additionally, various conductive materials may be applied to the metal materials used in the write word line (WWL), write bit line (WBL), read bit line (RBL), and read word line (RWL) of the 2T0C FeDRAM as needed.

Figure 2 shows a top view and a cross-sectional view of one memory cell of a non-volatile memory device according to one embodiment. First, referring to FIG. 2A, the source of the write transistor (Wtr) corresponds to the write bit line (WBL), and its gate corresponds to the write word line (WWL). The source of the read transistor (Rtr) corresponds to the read word line (RWL), and its drain corresponds to the read bit line (RBL). The drain of the write transistor (Wtr) and the gate of the read transistor (Rtr) are connected to each other through a storage node (SN), and a device structure that can minimize the resistance of this storage node (SN) is presented. .

Referring to FIG. 2B, the gate structure included in the write transistor (Wtr) has a stacked shape of a gate electrode (Gate) as a conductive layer, an insulator film (Insulator) as an insulating layer, and an oxide semiconductor film (ITZO) as a channel layer. . The gate structure included in the ferroelectric read transistor (Rtr) has a stacked shape of a gate electrode (Gate) as a conductive layer, a ferroelectric film (HZO) as an insulating layer, and an oxide semiconductor film (ITZO) as a channel layer. The reference symbol HZO is used as an insulating layer to emphasize Hafnium-Zirconium Oxide, a ferroelectric material, and the reference symbol ITZO is used as a channel layer to emphasize Indium-Tin-Zinc Oxide, an amorphous oxide semiconductor. It is only used to emphasize and is not necessarily used to limit the presented material. For example, in the case of HfLaO, HfSiO or HfAlO instead of HZO, HLO, HSO or HAO can be used as reference symbols, and instead of ITZO In the case of IGZO, InO, or ZnO, IGZO, InO, or ZnO may be used as reference symbols.

According to one embodiment, the two transistors Wtr and Rtr may be deposited through the same process. Both the write transistor (Wtr) and the ferroelectric read transistor (Rtr) may be disposed on the insulating layer pattern (Insulator) of a silicon CMOS logic circuit (Si CMOS Logic IC). In other words, 2T0C FeDRAM is a device suitable for the silicon CMOS process and can be deposited through a process using a silicon CMOS logic circuit.

Figure 3 shows a cross-sectional view of a monolithic 3D integrated structure of 2T0C FeDRAM according to one embodiment. As shown in the figure, a silicon CMOS logic circuit can be integrated on a silicon substrate through a FEOL (Front End of Line) process, and bit cells can be stacked thereon through a BEOL (Back End of Line) process. For this purpose, ITZO and HZO capable of BEOL processing can be applied to each transistor.

Figure 4 shows write and read operations of a 2T0C FeDRAM cell according to one embodiment. Figure 4a relates to a write operation, and Figure 4b relates to a read operation.

First, referring to FIG. 4A, in the case of a write operation, the first write control voltage is applied to the write transistor (Wtr) through the write word line (WWL) and the write bit line (WBL) and the read word line (RWL) and the read bit. The second write control voltage is applied to the ferroelectric read transistor (Rtr) through the line (RBL) to write the polarization direction to the ferroelectric material (Cox, Rtr) of the ferroelectric read transistor (Rtr). For example, 1 V may be applied to the write word line (WWL), 1 V to the write bit line (WBL), 0 V to the read bit line (RBL), and 0 V to the read word line (RWL). In this case, A channel layer is formed in the write transistor (Wtr) due to the write word line (WWL), and the ferroelectric material (Cox, Rtr) of the ferroelectric read transistor (Rtr) is formed through the channel layer of the write transistor (Wtr) due to the write bit line (WBL). ) information can be stored in polarized form. Even if no voltage is applied thereafter, the information stored in polarized form can be maintained.

Referring to FIG. 4b, in the case of a read operation, the first read control voltage is applied to the write transistor (Wtr) through the write word line (WWL) and the write bit line (WBL) and the read word line (RWL) and the read bit line The second read control voltage is applied to the ferroelectric read transistor (Rtr) through (RBL) to obtain the drain current of the ferroelectric read transistor (Rtr) that varies depending on the polarization direction of the ferroelectric material (Cox, Rtr) of the ferroelectric read transistor (Rtr). Read data. For example, -2 V can be applied to the write word line (WWL), 0 V to the write bit line (WBL), 0.8 V to the read bit line (RBL), and 0 V to the read word line (RWL). In this case, due to the voltage applied to the write word line (WWL), a voltage potential barrier is created between the write transistor (Wtr) and the ferroelectric read transistor (Rtr), preventing unexpected reverse operation, and in this state, the Carriers move from the read bit line (RBL) through the channel layer induced by polarization, and current is read. At this time, the read current varies depending on the presence or absence of polarization, and through this, it is possible to determine whether the device has been written.

Note that in the above-described writing and reading processes, the part where voltage is applied and the part where current flows do not overlap at all. The structural characteristics of the 2T 0C FeDRAM according to this embodiment enable a non-destructive read method to be realized.

Figure 5 shows an example of a cell array implementation of 2T0C FeDRAM according to an embodiment. 2T0C FeDRAM, which consists of a write transistor (Wtr) and a ferroelectric read transistor (Rtr), can be externally driven in an active matrix manner through two metal lines (M1 and M2). Reference symbols M1_1 and M1_2 are referred to as M1. Reference numerals M2_1, M2_2, and M2_3 are referred to as M2. The following description will be based on one cell (MC) indicated by a dotted line in the drawing.

The first metal line (M1_1) is electrically connected to the gates of the write transistors (Wtr). By applying a voltage higher than the threshold to the first metal line M1, a channel layer of the write transistors Wtr can be formed. The first metal line (M1_1) may correspond to the write word line (WWL) described above.

In the above, the description is centered on the first metal line (M1_1) on the left side of the drawing, but the same explanation can also be applied to the first metal line (M1_2) on the right side of the drawing.

The second metal lines (M2_1, M2_2, M2_3) are electrically connected to the sources of the write transistors (Wtr), the sources of the read transistors (Rtr), and the drains of the read transistors (Rtr). The second metal line (M2_1) at the middle of the drawing is connected to the sources of the write transistors (Wtr), the second metal line (M2_2) at the bottom of the drawing is connected to the sources of the read transistors (Rtr), and the second metal line (M2_2) at the bottom of the drawing is connected to the sources of the read transistors (Rtr). 2 The metal line (M2_3) is connected to the drains of the read transistors (Rtr). The second metal lines (M2_1, M2_2, M2_3) may store information in the read transistor (Rtr) during the writing process and read the stored information during the reading process. In the drawing, the middle second metal line (M1_1) is connected to the above-described write bit line (WBL), in the drawing, the lower second metal line (M1_2) is connected to the above-mentioned read word line (RWL), and in the drawing, the upper second metal line ( M1_3) may each correspond to the above-described read bit line (RBL).

The space between the first metal line (M1) and the second metal line (M2) is filled with a passivation material, and the metal material constituting the first metal line (M1) and the second metal line (M2) is used as needed. A variety of conductive materials can be applied.

Figure 6 shows a cross-sectional and top view of a 3D integrated 2T0C FeDRAM cell according to one embodiment. Figure 6a is a cross-sectional view, and Figure 6b is a top view.

First, as shown in FIG. 6A, in a 2T0C FeDRAM cell, the ferroelectric read transistor of the FeFET and the write transistor of the FET can be vertically integrated. At this time, we note that a high-density general-purpose memory device can be achieved by applying 3D integration by applying ITZO and HZO capable of BEOL processing. In other words, HZO can be applied as a ferroelectric material in FeFET and ITZO can be applied as an oxide semiconductor material, and ITZO can be applied as an oxide semiconductor material in FET. Meanwhile, for example, an Al ₂ O ₃ thin film with a thickness of 10 nm can be used as an insulating material in the FET.

According to one embodiment, when performing 3D integration, HZO is deposited using an ion beam sputter, which allows an additional annealing process at a relatively low temperature, rather than depositing HZO using Atomic Layer Deposition (ALD). You can. This is advantageous for ITZO's three-dimensional process, which requires low-temperature processes.

As shown in Figure 6b, in a 2T0C FeDRAM cell, the write transistor of the FET may be placed on the ferroelectric read transistor of the FeFET. The first metal line connected to the gate of the FET extends in the y direction in the drawing. The second metal line located at the top of the drawing connected to the drain of the FeFET extends in the x-direction in the drawing. The second metal line located at the middle of the drawing connected to the source of the FET extends in the x-direction in the drawing. And, the second metal line located at the bottom of the drawing connected to the source of the FeFET extends in the x-direction in the drawing. Meanwhile, the connection portion between each transistor and the metal line is marked with an

Figure 7 is a graph comparing the characteristics of 2T0C FeDRAM according to an embodiment and a conventional DRAM type.

Referring to FIG. 7, 1T-1C DRAM has a low retention time and a destructive read method, and also has low integration. In the case of 2T DRAM, it has lower retention time and integration than 1T-1C, but since it uses the gain of the transistor, a non-destructive method was implemented by separating the physical paths for reading and writing. Compared to the 1T-1C type and 2T type, AOS 2T DRAM has the highest retention time by using an amorphous oxide semiconductor, and has non-destructive data by using the gain of a transistor. Additionally, bit cells can be integrated in 3D using the BEOL process, increasing the level of integration. In the case of 2T-0C FeDRAM according to one embodiment, it can be confirmed that it is non-destructive and has a retention time of a unit that is incomparable to the three structures above. Additionally, the degree of integration is very high.

Figure 8A shows a structural diagram of a 2T0C FeDRAM cell using a double gate according to one embodiment. FIG. 8B shows the transfer curve of the FeFET used in the read transistor of the 2T0C FeDRAM of FIG. 8A for each case (Body Potential Fixed and Float Body) according to the body potential. The Body Potential Fixed corresponds to an embodiment in which a double gate is applied, and the Float Body corresponds to an embodiment in which a single gate is applied. Additionally, FIG. 8C is a schematic diagram of the operating principle of an amorphous oxide semiconductor film-based FeFET according to an embodiment, and FIG. 8D is a schematic diagram of the write state and erase state of an amorphous oxide semiconductor film-based FeFET according to an embodiment. .

As shown in FIG. 8A, by configuring the read transistor of the 2T0C FeDRAM as a double gate, the electric field can be applied more efficiently to the HZO.

In detail, looking at the principle with reference to FIGS. 8C and 8D, when a (+) voltage is applied to the gate, electrons in the channel are accumulated, and thus an electric field is efficiently applied to HZO and polarization is stored. The polarization of HZO is maintained by ferroelectricity, which changes the operating voltage (Vth) and stores data. However, the amorphous oxide semiconductor used as the channel layer is an n-type semiconductor with many electrons and almost no holes, and has a large band gap and an inversion channel ( This may cause problems in which an inversion channel is not formed and voltage is not efficiently applied to the HZO. In other words, it may cause problems with poor erase. To solve this problem, a top gate is placed on the channel, and a voltage is applied to the top gate, so that the electric field effectively acts on the HZO, changing the polarization of the HZO, making erasing possible. It becomes. In other words, in the case of a single gate, the voltage cannot be efficiently applied to the HZO because the inversion channel is not properly formed, but in the case of a double gate, the voltage can be efficiently applied to the HZO through the voltage applied to the top gate. When the transistor in the cross section shown on the left of FIG. 8A is a single gate, a double gate is formed by forming a passivation layer (Al ₂ O ₃ ) over the source and drain and placing a top gate on top, like the transistor in the cross section shown on the right. can be implemented. The source and drain below the passivation layer can be connected to external terminals through via holes, etc. Meanwhile, in the cross section shown on the right, the lower gate is not shown for convenience of explanation, but the same gate as in the cross section shown on the left may be arranged between HZO and P+ Si to be configured as a lower gate.

As shown in FIG. 8B, it can be seen that by configuring the read transistor of the 2T0C FeDRAM with a double gate, erase can be improved and the memory window can be expanded by effective voltage application of the ferroelectric. The drawing shows an embodiment in which the memory window (MW) is expanded from 0.5V to 1.5V. By expanding the memory window, the number of data states (states) that can be written and read can increase. In other words, it is possible to secure a large memory window due to the double gate.

Figure 9 shows the results of non-volatile characteristics and durability characteristics of FeFET used in a read transistor of 2T0C FeDRAM according to an embodiment. The voltage situation applied to the FeFET is shown on the left side of the figure. Through this, 2T0C FeDRAM, unlike existing DRAM, is expected to use less power due to its longer data retention time. As a result, it can be seen that low-power driving is possible and has non-volatile characteristics. According to this, the device can have durability that does not change its characteristics despite repeated operations. In other words, even in FeFETs composed of double gates, non-volatile characteristics and durability due to increased data retention time can be confirmed.

Figure 10 shows non-volatile results of multi-level state 2T0C FeFRAM according to one embodiment. As shown in the figure, due to the characteristics of FeFET, the drain current of the read transistor can be maintained for approximately 1000 s or more during a read operation in 2T0C FeDRAM. 2T0C FeDRAM can adjust the operating voltage to various states. As a result, it is possible to achieve high efficiency relative to area by using it as a multi-level state storage device that can store multiple states rather than the two states of 1 or 0 in existing DRAM. It also has the potential to be used as a neuromorphic device such as a synapse that mimics the human brain.

According to the above-described embodiment, a new material and structure of DRAM can be provided. Unlike existing DRAM, 2T0C FeDRAM according to one embodiment has a high retention time, so it has lower power usage, which enables low-power, high-efficiency operation unlike existing DRAM. In the structure proposed by 2T0C FeDRAM according to one embodiment, the physical voltage application directions for reading and writing do not overlap, so information is not destroyed, and thus, unlike existing DRAM, non-destructive driving is possible. In addition, FeDRAM using amorphous oxide semiconductors and ferroelectrics can be highly integrated in three dimensions.

As described above, the present invention has been described with specific details such as specific components and limited embodiments and drawings, but this is only provided to facilitate a more general understanding of the present invention, and the present invention is not limited to the above embodiments. , those skilled in the art can make various modifications and variations from this description. Accordingly, the spirit of the present invention should not be limited to the described embodiments, and the scope of the patent claims described later as well as all things that are equivalent or equivalent to the scope of this patent claim shall fall within the scope of the spirit of the present invention. .

Wtr: write transistor
Rtr: Ferroelectric read transistor
WWL: Write word line
WBL: write bitline
RWL: read word line
RBL: Read bit line
SN: storage node
M1, M1_1, M1_2: 1st metal line
M2, M2_1, M2_2, M2_3: 2nd metal line

Claims (16)

A memory cell including a write transistor and a ferroelectric read transistor;
a write word line connected to the gate terminal of the write transistor;
a write bit line connected to the source terminal of the write transistor;
a read word line connected to a source terminal of the ferroelectric read transistor; and
A read bit line connected to the drain terminal of the ferroelectric read transistor,
A drain terminal of the write transistor is connected to a gate terminal of the ferroelectric read transistor. According to paragraph 1,
A drain terminal of the write transistor is connected at a storage node to a gate terminal of the ferroelectric read transistor to induce a polarization direction in the ferroelectric material of the ferroelectric read transistor when the write transistor is turned on. According to paragraph 2,
A non-volatile memory device, wherein the ferroelectric material is hafnium-zirconium oxide. According to paragraph 2,
The memory cell is a non-volatile memory device formed on a silicon CMOS logic circuit integrated through a FEOL process on a silicon substrate and vertically stacked through a BEOL process. According to clause 4,
The memory cells are stacked in the order in which the write transistor is placed on the ferroelectric read transistor. According to clause 5,
A non-volatile memory device in which ITZO capable of a BEOL process is applied as a channel layer to the write transistor, and HZO and ITZO capable of a BEOL process are applied as an insulating layer and a channel layer, respectively, to the ferroelectric read transistor. Non-volatile memory device. According to clause 6,
In the BEOL process of forming the ferroelectric read transistor, the insulating layer is formed using ion beam sputtering. According to paragraph 1,
The gate structure of the write transistor has a structure in which a gate electrode as a conductive layer, an insulator film as an insulating layer, and an amorphous oxide semiconductor film as a channel layer are stacked,
A gate structure of the ferroelectric read transistor has a structure in which a gate electrode as a conductive layer, a ferroelectric film as an insulating layer, and an amorphous oxide semiconductor film as a channel layer are stacked. According to clause 8,
The ferroelectric film is any one selected from the group consisting of HZO (Hafnium-Zirconium Oxide), HfLaO (Hafnium-Lanthanum Oxide), HfSiO (Hafnium-Si Oxide), and HfAlO (Hafnium-Aluminium Oxide),
The amorphous oxide semiconductor film is any one selected from the group consisting of Indium-Tin-Zinc Oxide (ITZO), Indium-Gallium-Zinc Oxide (IGZO), Indium Oxide (InO), and Zinc Oxide (ZnO). According to paragraph 2,
A non-volatile memory device, wherein the ferroelectric read transistor is a single gate transistor. According to paragraph 2,
The non-volatile memory device wherein the ferroelectric read transistor is a double gate transistor including a bottom gate and a top gate. According to clause 11,
Electrons are accumulated in the channel by the write voltage applied to the bottom gate of the ferroelectric read transistor, and accordingly, an electric field is applied to the ferroelectric material to store polarization, and the stored polarization is maintained by the ferroelectric material to change the operating voltage. Data is stored,
A non-volatile memory device in which an inversion channel is formed by an erase voltage applied to the bottom gate and the top gate, and an electric field is accordingly applied to the ferroelectric material to change polarization and erase data. A method of operating a non-volatile memory device, comprising:
The non-volatile memory device,
a memory cell including a write transistor and a ferroelectric read transistor;
a write word line connected to the gate terminal of the write transistor;
a write bit line connected to the source terminal of the write transistor;
a read word line connected to a source terminal of the ferroelectric read transistor; and
A read bit line connected to the drain terminal of the ferroelectric read transistor,
The drain terminal of the write transistor is connected to the gate terminal of the ferroelectric read transistor,
A first write control voltage is applied to the write transistor through the write word line and the write bit line, and a second write control voltage is applied to the ferroelectric read transistor through the read word line and the read bit line to perform the ferroelectric read operation. writing the polarization direction into the ferroelectric material of the transistor; and
A first read control voltage is applied to the write transistor through the write word line and the write bit line, and a second read control voltage is applied to the ferroelectric read transistor through the read word line and the read bit line to change the polarization direction. A method of operating a non-volatile memory device comprising; reading data from a drain current of the ferroelectric read transistor that varies depending on. According to clause 13,
A method of operating a non-volatile memory device, wherein the ferroelectric read transistor is a single gate transistor. According to clause 13,
A method of operating a non-volatile memory device, wherein the ferroelectric read transistor is a double gate transistor including a bottom gate and a top gate. According to clause 13,
Electrons are accumulated in the channel by the write voltage applied to the bottom gate of the ferroelectric read transistor, and accordingly, an electric field is applied to the ferroelectric material to store polarization, and the stored polarization is maintained by the ferroelectric material to change the operating voltage. Data is stored,
A non-volatile memory device in which an inversion channel is formed by an erase voltage applied to the bottom gate and the top gate, and an electric field is accordingly applied to the ferroelectric material to change polarization and erase data.

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