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JPS5953700B2 - Implementation method - Google Patents

Implementation method

Info

Publication number
JPS5953700B2
JPS5953700B2 JP55031210A JP3121080A JPS5953700B2 JP S5953700 B2 JPS5953700 B2 JP S5953700B2 JP 55031210 A JP55031210 A JP 55031210A JP 3121080 A JP3121080 A JP 3121080A JP S5953700 B2 JPS5953700 B2 JP S5953700B2
Authority
JP
Japan
Prior art keywords
chip
plate
lead
opening
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP55031210A
Other languages
Japanese (ja)
Other versions
JPS5712542A (en
Inventor
賢造 畑田
勇 北広
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP55031210A priority Critical patent/JPS5953700B2/en
Publication of JPS5712542A publication Critical patent/JPS5712542A/en
Publication of JPS5953700B2 publication Critical patent/JPS5953700B2/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/12Mountings, e.g. non-detachable insulating substrates
    • H01L23/14Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
    • H01L23/142Metallic substrates having insulating layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16245Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241Disposition
    • H01L2224/24135Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24137Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73267Layer and HDI connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/922Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222Sequential connecting processes
    • H01L2224/92242Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • H01L2924/1815Shape
    • H01L2924/1816Exposing the passive side of the semiconductor or solid-state body
    • H01L2924/18162Exposing the passive side of the semiconductor or solid-state body of a chip with build-up interconnect
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/05Insulated conductive substrates, e.g. insulated metal substrate
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/182Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】 ラジオ、テレビ、ビア゛オテープレコーダ等の電子機器
は、小型、薄型化の方向にある。
DETAILED DESCRIPTION OF THE INVENTION Electronic devices such as radios, televisions, and audio tape recorders are becoming smaller and thinner.

このために、これら電子機器を構成する電子部品も、例
えば抵抗器にあつては両端にリード線を有したソリッド
抵抗から数mm角のセラミック基板に抵抗体層を印刷し
たチップ抵抗へと変つていつた。更にコンデンサにして
も同様の数mm角の電解層を積層したチップコンデンサ
に変つた。又、ICの実装においてもDILタイプのパ
ッケージから薄型、小型化されたフラットパック型のパ
ッケージが使用される様になつてきた。これら小型、薄
型化された電子部品を用いた実装によつて電子機器は徐
々に小型、薄型化が実現されてきているが、近年ICの
実装個数が増大するにつれて、前記ICの実装方法は問
題視されてきた。
For this reason, the electronic components that make up these electronic devices have changed from solid resistors with lead wires at both ends to chip resistors, which have a resistor layer printed on a ceramic substrate several millimeters square. It was. Furthermore, capacitors also changed to chip capacitors, which were made by laminating electrolytic layers several millimeters square. Furthermore, in the packaging of ICs, flat pack type packages, which are thinner and smaller, have come to be used instead of DIL type packages. Electronic devices are gradually becoming smaller and thinner through mounting using these smaller and thinner electronic components, but as the number of ICs mounted has increased in recent years, the method of mounting the ICs has become problematic. has been looked at.

ICそのものはSiチップ上に回路機能が半導、体技術
によつて組み込まれたものであつて、前記Siチップの
大きさが、実際のICの大きさである。このIC(例え
ばSiチップ)の大きさでは、プリント基板等に実装す
る時に、取扱いが著しく困難であるから前記Siチップ
に設けられた電極端子を拡大し、取扱いが容易な様にD
IL型やフラットパック型が用いられるのである。とこ
ろが、このために実装面積が前記Siチップよりも著し
く大きくなる。例えば5mm角で60ピン程度のLSI
の場合、フラットパック型でパッケージすると、その実
装面積は22×22mmの大きさとなりSiチップの約
20倍にも達して、ICの実装個数の増大に伴ない電子
機器の実装平面積が増大する事になる。本発明は、IC
、チップ抵抗、チップコンデンサ等の電子部品を高密度
にしかも薄型に実装する事を目的とする。
The IC itself has circuit functions built into a Si chip using semiconductor technology, and the size of the Si chip is the actual size of the IC. The size of this IC (for example, a Si chip) makes it extremely difficult to handle when mounted on a printed circuit board, etc., so the electrode terminals provided on the Si chip were enlarged and D
IL type and flat pack type are used. However, for this reason, the mounting area becomes significantly larger than that of the Si chip. For example, a 5mm square LSI with about 60 pins
In this case, when packaged in a flat pack type, the mounting area is 22 x 22 mm, which is about 20 times that of a Si chip, and as the number of ICs mounted increases, the mounting area of electronic devices increases. It's going to happen. The present invention is an IC
The purpose is to mount electronic components such as chip resistors, chip capacitors, etc. in a high-density and thin manner.

第1図は従来の実装方法で比較的高密度と思われる実装
方法を説明する。
FIG. 1 illustrates a conventional mounting method that is considered to have relatively high density.

第1図では特にICの’実装を主体に詳述する。厚さ1
〜3mmのセラミック基板1上にスクリーン印刷法によ
りAu、Agあるいは銀・パラジウムの配線体2を形成
する (第1図a)。
In FIG. 1, the details will be mainly focused on the implementation of the IC. Thickness 1
A wiring body 2 of Au, Ag or silver/palladium is formed on a ceramic substrate 1 of ~3 mm by screen printing (FIG. 1a).

次にCu層3を形成する (第1図b)。前記Cu層3
は抵抗加・熱、スパッター等の真空蒸着法や電気メッキ
法により数10〜数100μmの厚さに形成されるもの
である。前記Cu層3を光蝕刻法により任意の形状パタ
ーン3゛を設ける(第1図c)。次に電極端子5を有す
るICチツプ4を前記セラミツタ基板1上に導電性接着
剤等で固定する(第1図d)。Cuパターン3″および
ICチツプ4が載置されたセラミツク基板上にポリイミ
イド樹脂層6を設ける(第1図e)。前記ポリイミイド
樹脂層6の形成は、前記1Cチツプよりも厚いポリイミ
イド樹脂フイルムを前記1Cチツプ上より加熱、加圧す
る事によつて第1図eの構造を得るか、他の形成方法と
して液状のポリイミイド樹脂を、回転塗布する事によつ
て形成しても良い。次に前記1Cチツプ4の電極端子5
上およびCuパターン3″上の前記ポリイミイド樹脂6
を開孔して開孔部7,8を形成させる(第1図f)。
Next, a Cu layer 3 is formed (FIG. 1b). The Cu layer 3
is formed to a thickness of several 10 to several 100 μm by resistive heating, vacuum evaporation methods such as sputtering, or electroplating methods. A pattern 3' having an arbitrary shape is formed on the Cu layer 3 by photolithography (FIG. 1c). Next, the IC chip 4 having the electrode terminals 5 is fixed onto the ceramic substrate 1 with a conductive adhesive or the like (FIG. 1d). A polyimide resin layer 6 is provided on the ceramic substrate on which the Cu pattern 3'' and the IC chip 4 are mounted (FIG. 1e).The formation of the polyimide resin layer 6 involves the formation of a polyimide resin film that is thicker than the 1C chip. The structure shown in Fig. 1e may be obtained by applying heat and pressure from above the 1C chip, or alternatively, it may be formed by spin coating a liquid polyimide resin. Chip 4 electrode terminal 5
The polyimide resin 6 on top and Cu pattern 3″
The holes are opened to form the openings 7 and 8 (FIG. 1f).

開孔部7,8の形成は、前記ポリイミイド樹脂6上に感
光性樹脂を塗布した光蝕刻法によつて実施できる。開孔
部7,8が形成された面に蒸着法によりCr−Cu膜を
被着し、前記開孔部7,8同志を接続する様に光蝕刻法
により配線パターン9を形成する事により第1図gの構
造を得る。
The openings 7 and 8 can be formed by a photoetching method in which a photosensitive resin is applied onto the polyimide resin 6. A Cr-Cu film is deposited by vapor deposition on the surface where the openings 7 and 8 are formed, and a wiring pattern 9 is formed by photoetching to connect the openings 7 and 8. Obtain the structure shown in Figure 1g.

ICチツプの実装がチツプの状態で実装されるので高密
度の実装が実現できるが次の様な欠点がある。1万一、
ICチツプが不良の場合1Cチツプの交換が出来ない。
Since the IC chips are mounted in the chip state, high-density packaging can be achieved, but there are the following drawbacks. 10,000,
If the IC chip is defective, the 1C chip cannot be replaced.

2第1図gの構造を得るのにプロセス,の工数が多すぎ
て、歩留りが低下する。
2. The number of process steps required to obtain the structure shown in FIG. 1g is too large, resulting in a decrease in yield.

3更にセラミツク基板の厚みを必要とするために実装体
の厚みが増加する事になる。
3. Furthermore, since the thickness of the ceramic substrate is required, the thickness of the mounted body increases.

本発明は従来のこの様な欠点を一掃せんとするものであ
る。
The present invention aims to eliminate these conventional drawbacks.

第2図において本発明を詳述する。こ金属板(例えば0
.1〜0.3mm程度のNi板)40にあらかじめIC
、チツプ部品が挿入される開孔部41,4「をパンチン
グ法又は光蝕刻法等で形成する(第2図a)。次に前記
金属板40の一面もしくは金属フイルム(例えば5〜3
5μm程度3のCu板)42の一面板に接着剤43を塗
布し、前記金属板40と金属フイルム42とを貼り合せ
る(第2図b)。前記金属フイルム42上に感光性樹脂
を塗布し、この上から所望のリード配線パターンを形成
したマスクを用いて紫外線を照射4,し、現像、更に前
記金属フイルム42を化学蝕刻し第2図Cの如くのリー
ド配線42″を形成させる。前記工程において金属フイ
ルム42上に感光性樹脂を塗布する際、開孔部41,4
「側の金属フイルムにも感光性樹脂を塗布しておけば、
リード配線パターンの化学蝕刻の際に、開孔部41,4
1″側から蝕刻が進行するのを防ぐ事が出来る。前記感
光性樹脂としては、比較的解像度が7高いポジ型感光性
樹脂(例えばシツプレイ社製のAZ−1350J)を使
えば、化学蝕刻後の前記感光性樹脂の除去はアセトンの
如き有機溶剤で容易に除去出来るものである。又前記金
属フイルムがCuフイルムであれば蝕刻液としては塩化
第二鉄の溶フ剤が適切である。次に半田バンプ等44,
44″を有するIC45″、チツプ部品45を前記金属
板46の開孔部41,41″に挿入し、前記半田バンプ
等44,44″と、リード配線42″とを位置合せし、
加熱した治具20,2『(温度300〜400℃)によ
り加圧21,21″する。この動作により、前記半田バ
ンプ等44,44″とリード配線42″とは半田づけさ
れ固定されるものである(第2図d)。最後にエポキシ
樹脂あるいはシリコーン樹脂等の保護膜22,22″を
塗布し、硬化させれば第2図eの構造を得る事が出来る
。又、本発明の場合、前記したNi板を用いクロスオー
バの配線を実施する事が出来る。第3図でこれを説明す
る。所定の開孔部を有するNi板上の第3図の90およ
び9『に相当する部分のみ、接着剤を塗布しないで、金
属フイルムを貼り合せる。すなわちマスク材を用いてス
クリーン印刷的に前記接着剤43を塗布する。しかるの
ち、リード配線パターンの形成が終れば、リード配線5
42″および42″″をNi板4『上に半田づけ固定す
れば、前記リード配線42″と42″″とが前記Ni板
4『によつて電気的に接続する事が出来る。本発明にお
いて、Ni板はFesBs.SuS等の導電性を有し、
機械的強度を有するものであれば、Ni板に限定するも
のではなく、前記Ni板は最終完成工程での実装体の基
体となり、実装体の機械的補強を行なうものである。又
、金属フイルムはCu.Bs.Al等の金属でも構成出
来るものである。第4図は第2図の平面図である。
The invention is explained in detail in FIG. This metal plate (e.g. 0
.. 1-0.3mm Ni plate) 40 in advance.
Openings 41, 4'' into which chip parts are inserted are formed by punching or photoetching (FIG. 2a).Next, one side of the metal plate 40 or a metal film (for example, 5 to 3
An adhesive 43 is applied to one side of the Cu plate (Cu plate) 42 having a thickness of about 5 μm, and the metal plate 40 and the metal film 42 are bonded together (FIG. 2b). A photosensitive resin is applied onto the metal film 42, irradiated with ultraviolet rays using a mask with a desired lead wiring pattern formed thereon, developed, and further the metal film 42 is chemically etched, as shown in FIG. 2C. Lead wiring 42'' is formed as shown in FIG.
``If you apply photosensitive resin to the metal film on the side,
During chemical etching of the lead wiring pattern, the openings 41, 4
It is possible to prevent etching from progressing from the 1" side. If a positive photosensitive resin with a relatively high resolution of 7 (for example, AZ-1350J manufactured by Shipley) is used as the photosensitive resin, it is possible to prevent etching from progressing from the 1" side. The photosensitive resin can be easily removed using an organic solvent such as acetone.Furthermore, if the metal film is a Cu film, a ferric chloride solvent is suitable as the etching solution. solder bumps etc. 44,
Insert an IC 45'' having a diameter of 44'' and a chip component 45 into the openings 41, 41'' of the metal plate 46, align the solder bumps etc. 44, 44'' and the lead wiring 42'',
The heated jigs 20, 2'' (temperature 300 to 400°C) apply pressure 21, 21''. Through this operation, the solder bumps 44, 44'' and the lead wiring 42'' are soldered and fixed. (Fig. 2 d).Finally, a protective film 22, 22'' of epoxy resin or silicone resin is applied and cured to obtain the structure shown in Fig. 2 e. Further, in the case of the present invention, crossover wiring can be implemented using the above-mentioned Ni board. This will be explained in FIG. A metal film is bonded to only the portions corresponding to 90 and 9'' in FIG. 3 on the Ni plate having predetermined openings without applying adhesive. That is, the adhesive 43 is applied by screen printing using a mask material. After that, when the formation of the lead wiring pattern is completed, the lead wiring 5
By soldering and fixing 42'' and 42'' on the Ni plate 4', the lead wirings 42'' and 42'' can be electrically connected by the Ni plate 4'. In the present invention, the Ni plate is FesBs. Has conductivity such as SuS,
The Ni plate is not limited to the Ni plate as long as it has mechanical strength, and the Ni plate serves as the base of the package in the final completion process and mechanically reinforces the package. Moreover, the metal film is Cu. Bs. It can also be made of metal such as Al. FIG. 4 is a plan view of FIG. 2.

Ni板11上には、あらかじめICl8やチツプ部品1
7を挿入するための開孔部12を有している。前記Ni
板11上には接着剤層14を介してリード配線13″が
形成される。前記リード配線13″は前記開孔部12に
おいて挿入されるIC]8やチツプ部品17の電極端子
と対応する位置まで、配線を延在した構造であり、更に
リード配線13″″の如く、開孔部12を横断した構造
に形成されるものである。前記開孔部12に延在したリ
ード配線はICl8の電極端子上のバンプ19やチツプ
部品17の電極端子上のバンプ16と接合されている。
又、Ni板11のリード配線13″の形成されていない
反対面に機械的強度を増すための基体とを一体に構成さ
れ、前記基体上に形成した回路群,と、外部回路とを接
続するための基本と構成された回路を外部回路と接続す
るための端子35が形成されている。
ICl8 and chip parts 1 are placed on the Ni plate 11 in advance.
It has an opening 12 for inserting the holder 7. Said Ni
Lead wires 13'' are formed on the plate 11 via an adhesive layer 14.The lead wires 13'' are located at positions corresponding to the electrode terminals of the IC 8 and chip component 17 inserted in the opening 12. This is a structure in which the wiring extends up to the opening 12, and is further formed to cross the opening 12, like the lead wiring 13''''. The lead wires extending into the openings 12 are connected to bumps 19 on the electrode terminals of the ICl 8 and bumps 16 on the electrode terminals of the chip component 17.
Further, a base for increasing mechanical strength is integrally formed on the opposite surface of the Ni plate 11 on which the lead wiring 13'' is not formed, and a circuit group formed on the base is connected to an external circuit. Terminals 35 are formed for connecting the basic and configured circuit to an external circuit.

前記外部端子35には、延在したリード配線13″″が
半田づけ固定されている。点線36は前記Ni板11の
不要部分を切断する位.置を示すものである。本発明の
更に効果的な製法として、例えば第5図に示す如くNi
板11の開孔部12に延在したリード配線13″が折れ
曲がつてしまい、ICやチツプ部品のバンプと接続出来
ないという事故を妨,ぐために、第6図に示す如く、例
えば0.1〜0.3mm程度の絶縁板35を前記リード
配線13″上に置き、接着剤36で固定すれば、前述し
た如くの事故を防止できるものである。
An extended lead wire 13'' is fixed to the external terminal 35 by soldering. The dotted line 36 indicates the point where the unnecessary portion of the Ni plate 11 is cut. This indicates the location. As a more effective manufacturing method of the present invention, for example, as shown in FIG.
In order to prevent an accident in which the lead wiring 13'' extending into the opening 12 of the plate 11 is bent and cannot be connected to the bump of an IC or chip component, a wire of 0.1 mm, for example, is used as shown in FIG. By placing an insulating plate 35 of about 0.3 mm on the lead wiring 13'' and fixing it with an adhesive 36, the above-mentioned accident can be prevented.

次に本発明の第2図の実施例を量産的に生産する場合の
概略を第3図で説明する。
Next, an outline of mass production of the embodiment of the present invention shown in FIG. 2 will be explained with reference to FIG. 3.

あらかじめ送り用の穴50を形成したNi板51はガイ
ドローラ52によつてステツプ153に送りこまれ、所
望の形状をしたパンチングマシン54によつてIC、チ
ツプ部品を挿入するための開孔部55を形成する。次の
ステツプ1156において例えば35μm厚の接着剤を
塗布したCu箔57をガイドローラ58と59の間を通
過させる事により前記Ni板51と貼り合せる。ステツ
プ11160においては感光性樹脂61をノズル62よ
り隣接させたガイドローラー63,63″に滴下し、前
記Cu箔57上に一定の膜厚を塗布せしめ、ステツプI
64で前記感光性樹脂を赤外線ランプ65で乾燥させる
。ステツプV66はマスク露光工程で、Cuリード配線
を形成させるためのパターン67を有するマスク68を
前記感光性樹脂を塗布したNi板5]上に接着せしめ、
紫外線ランプ69によつて紫外光70を照射させる。ガ
イドローラ7]によつて露光された感光性樹脂膜を有す
るNi板51はステツプVI72へ送りこまれる。前記
Ni板51は現像液73を満したタンク74中を通過す
る事により、感光性樹脂によるCuリード配線のパター
ン75を現出させ、ステップNII76において、現像
により膨潤した前記感光性樹脂パターン75を赤外線ラ
ンプJモVより硬化せしめる。次にステップ′VlIl7
8において前記感光性樹脂パターン75を蝕刻用のマス
クとして、露出しているCu箔をエツチング除去する。
エツチング用の液はノズル79より噴射されるものであ
る。ステツプX84は、IC、チツプ部品の電極端子上
に設けた半田バンプとCuリード配線85とを半田づけ
する工程である。IC86、チツプ抵抗87、チツプコ
ンデンサ88は各々専用のトレイ86″,87″, 8
8″は各々の開孔部55下に搬送され、加熱した治具8
9が降下し、半田づけを行なうもので゛ある。IC、チ
ップ陪b品の半田づけされたものは、更に裏面に保護用
の樹脂を塗布し、硬化せしめた後ステツブ.X[90の
工程へと運ばれ、型抜き用のパンチングマシン91によ
り、92の如く最終的な形状に切断されるものである。
この様に本発明の構成は、一貫した量産システムを構成
する事ができるものである。本発明は基板配線の作成工
程とチツプ部品を前記基板配線に固定する工程とが全く
別々の工程で行なわれる、いわゆる並列工法である。
A Ni plate 51 with a feed hole 50 formed in advance is sent to a step 153 by a guide roller 52, and a punching machine 54 having a desired shape forms an opening 55 for inserting an IC or chip component. Form. In the next step 1156, a Cu foil 57 coated with an adhesive having a thickness of, for example, 35 μm is passed between guide rollers 58 and 59 to be bonded to the Ni plate 51. In step 11160, the photosensitive resin 61 is dropped from the nozzle 62 onto the adjacent guide rollers 63, 63'', and is coated on the Cu foil 57 to a certain thickness, and then in step I.
At 64, the photosensitive resin is dried with an infrared lamp 65. Step V66 is a mask exposure step in which a mask 68 having a pattern 67 for forming Cu lead wiring is adhered onto the Ni plate 5 coated with the photosensitive resin;
Ultraviolet light 70 is irradiated by an ultraviolet lamp 69. The Ni plate 51 having the exposed photosensitive resin film is sent to step VI72 by the guide roller 7. The Ni plate 51 passes through a tank 74 filled with a developer 73 to reveal a Cu lead wiring pattern 75 made of photosensitive resin, and in step NII76, the photosensitive resin pattern 75 swollen by development is removed. Harden with infrared lamp JMoV. Next step 'VlIl7
In step 8, the exposed Cu foil is removed by etching using the photosensitive resin pattern 75 as an etching mask.
The etching liquid is sprayed from a nozzle 79. Step X84 is a process of soldering the Cu lead wire 85 to the solder bump provided on the electrode terminal of the IC or chip component. The IC 86, chip resistor 87, and chip capacitor 88 are placed in dedicated trays 86'', 87'', and 8, respectively.
8'' is conveyed under each opening 55 and heated jig 8
9 descends and performs soldering. For soldered ICs and chip products, a protective resin is further applied to the back side, and after hardening, the step. It is transported to the process of X[90 and cut into the final shape as shown in 92 by a punching machine 91 for die cutting.
In this way, the configuration of the present invention allows a consistent mass production system to be configured. The present invention is a so-called parallel construction method in which the step of creating board wiring and the step of fixing chip components to the board wiring are performed in completely separate steps.

第1図に示した例は、基板とチツプ部品を載置し、ポリ
イミイド樹脂で埋設、次いで前記チツプ部品の電極端子
上を開孔し、全面に金属膜を蒸着、光蝕刻法により配線
パターンを形成する事によつて、完成する、いわゆる直
列工法である。例えば、2つの工程からなる場合の歩留
り (各々の工程の歩留りを90%と仮定する)を比較
すれば、直列工法の場合、0.9X0.9=0.81で
最終81%の歩留りとなるのに対し、並列工法の場合、
1−(4).1×0.1)0.99で最終歩留りは99
%となる。この様に本発明の構成では、著しく高い歩留
りを提供出来るものである。第1図の従来例の構成にあ
つては、万一、前記71Cやチツプ部品の不良品を搭載
した場合、不良品のチツプのみを取りはずし、交換する
事が出来ない、何故ならば、前記1Cやチツプ部品を交
換するためには、ポリイミイド樹脂から前記1Cやチツ
プ部品を堀り起こさねばならない。
In the example shown in Fig. 1, a substrate and a chip component are mounted, buried in polyimide resin, holes are made on the electrode terminals of the chip component, a metal film is deposited on the entire surface, and a wiring pattern is formed using photolithography. This is the so-called serial construction method, which is completed by forming. For example, if we compare the yield in the case of two processes (assuming the yield in each process is 90%), in the case of the serial method, the final yield is 81% (0.9 x 0.9 = 0.81). In contrast, in the case of parallel construction method,
1-(4). 1 x 0.1) 0.99 and the final yield is 99
%. As described above, the configuration of the present invention can provide an extremely high yield. In the configuration of the conventional example shown in Fig. 1, if a defective chip component such as the 71C is mounted, it is not possible to remove and replace only the defective chip, because the 1C In order to replace the 1C and chip parts, it is necessary to excavate the 1C and chip parts from the polyimide resin.

このために、ICやチツプ部品の配線パターンは完全に
破損してしまう。更に新しいIC、チツプ部品と交換し
えたとしても、最初のポリイミイド樹脂で埋設する工程
から開始しなければならないから、殆んどの場合、1チ
ツプの不良であつても全体を基板ごと不良としなければ
ならない、このために製造歩留りが著しく低下し、製造
コストが著しく高くなるものであつた。ところが本発明
の製造方法であれば、チツプ部品とリードとの接合部を
再度加熱治具で加熱する事により容易に着脱し、良品と
交換出来るものである。又、IC等を第]図の例以外の
方法で基板に搭載する場合、例えば、もつとも一般的で
あるフイルムキヤリア方式(;よると、ICチツプの電
極端子上のバンプとリードを接合する工程、更に前記I
Cチツプの電極端子から延在したリードを配線基板に接
合する工程が必要であるばかりか、前記延在したリード
を配線基板に接合するための接合面積が必要となる。
As a result, the wiring patterns of ICs and chip components are completely damaged. Furthermore, even if the IC or chip parts can be replaced with a new one, the process must start from the initial embedding process with polyimide resin, so in most cases, even if one chip is defective, the entire board must be treated as defective. Therefore, the manufacturing yield was significantly lowered and the manufacturing cost was significantly increased. However, with the manufacturing method of the present invention, by heating the joint between the chip component and the lead again using a heating jig, the chip component can be easily attached and detached and replaced with a good product. In addition, when mounting an IC, etc. on a board by a method other than the example shown in Fig. Furthermore, the above I
Not only is a process necessary for bonding the leads extending from the electrode terminals of the C chip to the wiring board, but also a bonding area is required for bonding the extended leads to the wiring board.

この接合面積の必要性はそのまま実装密度を低下させる
事になるから、高密度の実装が行なえなくな・る。これ
に対し、本発明はICチツプ上の電極端子とリードとの
接合のみで良いから、従来必要としていた、配線基板上
での接合面積が不必要であるから、その分だけ高密度の
実装を行なえるものである。前記接合面積は一般にリー
ド長さを最低2mmとすれば2×(LSIチツプ周辺長
)iの分だけ必要となるものである。更に本発明の構成
であれば、金属フイルムを構成回路の外部導出端子(第
4図35)として利用出来るため、新たに外部導出端子
を付加する必要がないから、工数が少なく、低価格な実
装体を提供出来るものである。又、本発明はNi板を実
装体の基体として用いる一方。
The need for this bonding area directly reduces the packaging density, making it impossible to perform high-density packaging. On the other hand, the present invention requires only the connection between the electrode terminals on the IC chip and the leads, which eliminates the need for the bonding area on the wiring board, which was required in the past. It can be done. Generally, if the lead length is at least 2 mm, the bonding area is required to be 2×(LSI chip peripheral length) i. Furthermore, with the configuration of the present invention, since the metal film can be used as an external lead-out terminal (Fig. 4, 35) of the component circuit, there is no need to add a new external lead-out terminal, resulting in less man-hours and low-cost mounting. It is something that can provide a body. Further, the present invention uses a Ni plate as the base of the mounting body.

この基体上に直接金属フイルムによるリード配線パター
ンを形成するものである。本発明は単にNi板上に金属
フイルムを貼合せる事により基体およびリード配線を形
成するものであるから従来例に示しこ如くの高価なポリ
イミイド樹脂を使用しないから著しく安価な実装体を実
現出来る一方、ポリイミイド樹脂等への開孔工程等を必
要としないから、更に低価格な実装体を提供出来るもの
である。
A lead wiring pattern is formed directly on this substrate using a metal film. Since the present invention forms the base and lead wiring simply by laminating a metal film on a Ni plate, it does not use expensive polyimide resin as shown in the conventional example, so it is possible to realize an extremely inexpensive mounting body. Since there is no need for a process of forming holes in polyimide resin or the like, it is possible to provide a mounting body at a lower cost.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図a−gは従来の高密度化した実装方法の説明図、
第2図a−eは本発明の一実施例を示す断面説明図、第
3図は本発明の応用例を示す断面図、第4図は本発明の
完成品の一例の平面図、第5図、第6図は本発明の応用
例の説明図、第7図a−cは本発明の量産工程の一例を
示す斜視図である。 40・・・・・・金属板、41,4「・・・・・・開孔
部、42・・・・・・金属フイルム、42″・・・・・
・リード配線、45・・・・・・チツプ部品、45″・
・・・・・IC。
Figures 1a-g are explanatory diagrams of the conventional high-density mounting method;
2A to 2E are cross-sectional explanatory views showing one embodiment of the present invention, FIG. 3 is a cross-sectional view showing an application example of the present invention, FIG. 4 is a plan view of an example of a finished product of the present invention, and FIG. 6 are explanatory diagrams of an application example of the present invention, and FIGS. 7 a to 7 c are perspective views showing an example of a mass production process of the present invention. 40...Metal plate, 41,4"...Opening part, 42...Metal film, 42"...
・Lead wiring, 45... Chip parts, 45''・
...IC.

Claims (1)

【特許請求の範囲】[Claims] 1 金属フレームに開孔部を形成する工程と、前記金属
フレーム上に絶縁性を有する接着層を形成する工程と、
前記金属フレーム及び前記開孔部上に前記接着層を用い
て金属フィルムを形成する工程と、前記金属フィルムを
光蝕刻法により、配線パターンおよび前記配線パターン
と連続し、前記開孔部に突出したリードを形成する工程
と、前記開孔部に素子片を挿入し、前記開孔部に突出し
たリードと前記素子片とを接合する工程と、前記金属フ
レームを所定の形状に切断する工程とからなる実装方法
1. A step of forming an opening in a metal frame, and a step of forming an insulating adhesive layer on the metal frame,
a step of forming a metal film using the adhesive layer on the metal frame and the opening; and a step of forming the metal film into a wiring pattern, which is continuous with the wiring pattern and protrudes into the opening, by a photoetching method. A step of forming a lead, a step of inserting an element piece into the opening, a step of joining the lead protruding into the opening and the element piece, and a step of cutting the metal frame into a predetermined shape. implementation method.
JP55031210A 1980-03-11 1980-03-11 Implementation method Expired JPS5953700B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55031210A JPS5953700B2 (en) 1980-03-11 1980-03-11 Implementation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55031210A JPS5953700B2 (en) 1980-03-11 1980-03-11 Implementation method

Publications (2)

Publication Number Publication Date
JPS5712542A JPS5712542A (en) 1982-01-22
JPS5953700B2 true JPS5953700B2 (en) 1984-12-26

Family

ID=12325062

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55031210A Expired JPS5953700B2 (en) 1980-03-11 1980-03-11 Implementation method

Country Status (1)

Country Link
JP (1) JPS5953700B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS627399A (en) * 1985-07-02 1987-01-14 Matsushita Electric Ind Co Ltd Motor driving device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS627399A (en) * 1985-07-02 1987-01-14 Matsushita Electric Ind Co Ltd Motor driving device

Also Published As

Publication number Publication date
JPS5712542A (en) 1982-01-22

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