JPS5947462B2 - Lead configuration for semiconductor devices - Google Patents
Lead configuration for semiconductor devicesInfo
- Publication number
- JPS5947462B2 JPS5947462B2 JP340677A JP340677A JPS5947462B2 JP S5947462 B2 JPS5947462 B2 JP S5947462B2 JP 340677 A JP340677 A JP 340677A JP 340677 A JP340677 A JP 340677A JP S5947462 B2 JPS5947462 B2 JP S5947462B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- lead frame
- leads
- semiconductor devices
- resin
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Description
【発明の詳細な説明】
本発明は、プレス加工法を用いて成形する樹脂封止型半
導体装置用リードフレームの構造に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a lead frame for a resin-sealed semiconductor device that is molded using a press method.
従来、半導体装置用リードフレームには種々のリードパ
ターンがあり、各々のリードパターンに対してリードフ
レームプレス型、素子マウント装置、ワイヤボンディン
グ装置及び樹脂封止金型が各々のリードパターンに応じ
て設計され製作されている。Conventionally, lead frames for semiconductor devices have various lead patterns, and lead frame press molds, element mounting equipment, wire bonding equipment, and resin sealing molds are designed for each lead pattern. It has been manufactured.
このように半導体装置の組立に必要な設備は、リードフ
レームのリードパターンの種類数に比例して増加するの
で設備数が多くなり、結局製品のコスト高の原因になる
。As described above, the equipment required for assembling a semiconductor device increases in proportion to the number of types of lead patterns of the lead frame, resulting in an increase in the number of equipment, which ultimately causes an increase in the cost of the product.
本発明は上記の状況に鑑みてなされたもので、半導体装
置の組立に用いる諸設備を兼用できるようにした樹脂封
止型の半導体装置用リードフレームの構造を提供するも
のである。The present invention has been made in view of the above-mentioned situation, and provides a resin-sealed lead frame structure for semiconductor devices that can be used in combination with various equipment used for assembling semiconductor devices.
本発明の実施例を、第１図および第２図のリードフレー
ムの部分平面図を用いて説明する。Embodiments of the present invention will be described using partial plan views of lead frames shown in FIGS. 1 and 2. FIG.
第１図に示すように金属薄板を順次打ち抜いて、半導体
素子載置部１および２、内部リード３、外部リード４、
タイバー５を備えたリードフレームを形成する。この際
内部および外部リードは樹脂封止される樹脂巾寸法に納
まる範囲で必要本数（第１図の場合は４本）を配置して
成形する訳であるが、本発明はこのリード成形工程を最
終工程としないで、この完成されたリードフレームを更
にリード本数の異なる他のリードフレームとして使用す
るために同一金型にポンチを取り付けるだけで第１図に
示すリードのうち不必要となる内部リード３’を切断除
去Ｌ、この工程を最終工程として第２図に示すリードフ
レームを成形するようにしたものである。この方法によ
れば、同一金型の最終工程部分にポンチを取り付けるか
取り付けないかによって、第１図に示す４本リードのリ
ードフレーム又は第２図に示す３本リードのリードフレ
ームのように異なるリードパターンを持つリードフレー
ムが形成できる。As shown in FIG. 1, thin metal plates are punched out in order, semiconductor element mounting parts 1 and 2, internal leads 3, external leads 4,
A lead frame with tie bars 5 is formed. At this time, the necessary number of internal and external leads (four in the case of Fig. 1) are arranged and molded within the range of the resin width dimension to be resin-sealed. In order to use this completed lead frame as another lead frame with a different number of leads without doing the final process, you can simply attach a punch to the same mold, which will eliminate unnecessary internal leads among the leads shown in Figure 1. 3' is cut and removed L, and this step is the final step to form the lead frame shown in FIG. 2. According to this method, depending on whether or not a punch is attached to the final process part of the same mold, a lead frame with four leads as shown in Figure 1 or a lead frame with three leads as shown in Figure 2 will be different. A lead frame with a lead pattern can be formed.
このようにプレス金型を共用して成形されたリードフレ
ームは、さらに素子マウント装置、ワイヤボンディング
装置も共用できる。これを第３図ａ、ｂ、ｃに示すリー
ドパターンの平面図で説明すると、ａ、ｂ図に示す４本
リードのリードフレームは必要に応じて素子載置部１お
よび２のいずれにも半導体素子６を載置できるようにし
たもので、半導体素子６を載置してボンディングワイヤ
Ｔで内部リード３との間を結線したものである。又ｃ図
は３本リードのリードフレームを用いた場合である。す
なわちｃ図のリードパターンに適用できる装置はａ図の
リードパターンにはそのまま適用できるし又ｂ図のリー
ドパターンの場合も簡単に位置合わせをし直すだけで適
用できる。さらに第１図および第２図のリードフレーム
を樹脂封止する場合も同一の封止金型を共用できること
はもちろんである。その後、リードフレームから切り離
して完成した樹脂封止型半導体装置の平面図を第４図Ａ
，ｂに示す。ａ図は４本リードのリードフレーム、ｂ図
は３本リードのリードフレームを用いたものでｂ図の中
央の外部リードは樹脂封止前に切断除去されている。以
上述べたように、従来ならばプレス成形から樹脂封止に
至るまでそれぞれのリードフレームに合わせた製造設備
が必要であつたのに対し、本発明によれば同一の設備を
共用できるのでその経済的効果は大きい。なお本発明は
、外部リード数が４本のリードフレームを３本のリード
フレームに共用した場合を説明したが、一般に封止樹脂
巾内に納まる本数を持つたリードフレームから不必要な
本数を除去すれば、何種類もの共用するリードフレーム
が得られる。A lead frame molded using a common press mold in this way can also be used in common with an element mounting device and a wire bonding device. To explain this using the plan view of the lead pattern shown in FIG. 3a, b, and c, the four-lead lead frame shown in FIGS. The semiconductor element 6 is placed thereon and connected to the internal leads 3 using bonding wires T. Figure c shows a case where a lead frame with three leads is used. In other words, a device that can be applied to the lead pattern shown in Figure C can be applied as is to the lead pattern shown in Figure A, and can also be applied to the lead pattern shown in Figure B by simply repositioning. Furthermore, it goes without saying that the same sealing mold can be used in the case of resin-sealing the lead frames shown in FIGS. 1 and 2. Figure 4A shows a plan view of the completed resin-sealed semiconductor device after it is separated from the lead frame.
, b. Figure a uses a lead frame with four leads, and figure b uses a lead frame with three leads.The external lead in the center of figure b is cut and removed before resin sealing. As mentioned above, whereas in the past, manufacturing equipment was required for each lead frame from press molding to resin encapsulation, the present invention allows the same equipment to be shared, making it more economical. The effect is significant. In the present invention, a case has been described in which a lead frame with four external leads is shared by three lead frames, but in general, unnecessary numbers can be removed from a lead frame whose number fits within the sealing resin width. In this way, you can obtain lead frames that can be used in many different ways.
特に集積回路のようにリード数の多いり−ドフレームに
適用すればその効果は極めて大きい。The effect is particularly great when applied to a board frame with a large number of leads, such as an integrated circuit.
第１図および第２図は本発明の実施例を説明するリード
フレームの部分平面図、第３図Ａ，ｂ，ｃは前記リード
フレームの使用状態を説明する部分平面図、第４図Ａ，
ｂは前記リードフレームを樹脂封止して成形した半導体
装置の平面図である。
１，２・・・素子載置部、３，３５・・・内部リード、
４・・・外部リード、５・・・タイバー、６・・・半導
体素子、７・・・ボンデイングワイャ。1 and 2 are partial plan views of a lead frame illustrating an embodiment of the present invention, FIGS. 3 A, b, and c are partial plan views illustrating how the lead frame is used, and FIGS. 4 A,
b is a plan view of a semiconductor device molded by resin-sealing the lead frame. 1, 2... Element mounting part, 3, 35... Internal lead,
4... External lead, 5... Tie bar, 6... Semiconductor element, 7... Bonding wire.
Claims (1)
出用リードを前記幅広部同志が対向するように直線状に
配置し、前記対向する幅広部の横に電極導出用リードの
金属細線接続部を配置せしめたことを特徴とする半導体
装置用リード構成。1. Two external lead-out leads having wide parts at their tips capable of mounting an element are arranged in a straight line so that the wide parts face each other, and a thin metal wire of an electrode lead is placed next to the opposing wide parts. A lead configuration for a semiconductor device characterized by having a connecting portion arranged.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP340677A JPS5947462B2 (en) | 1977-01-13 | 1977-01-13 | Lead configuration for semiconductor devices |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP340677A JPS5947462B2 (en) | 1977-01-13 | 1977-01-13 | Lead configuration for semiconductor devices |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5388575A JPS5388575A (en) | 1978-08-04 |
| JPS5947462B2 true JPS5947462B2 (en) | 1984-11-19 |
Family
ID=11556493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP340677A Expired JPS5947462B2 (en) | 1977-01-13 | 1977-01-13 | Lead configuration for semiconductor devices |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5947462B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62102355U (en) * | 1985-12-19 | 1987-06-30 |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58194382A (en) * | 1982-05-08 | 1983-11-12 | Matsushita Electric Ind Co Ltd | Electrode structure for semiconductor device |
| JPS59107150U (en) * | 1982-12-31 | 1984-07-19 | ロ−ム株式会社 | Small transistor lead frame |
-
1977
- 1977-01-13 JP JP340677A patent/JPS5947462B2/en not_active Expired
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62102355U (en) * | 1985-12-19 | 1987-06-30 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5388575A (en) | 1978-08-04 |
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