JPH01216563A - Manufacture of lead frame - Google Patents
Manufacture of lead frameInfo
- Publication number
- JPH01216563A JPH01216563A JP4318788A JP4318788A JPH01216563A JP H01216563 A JPH01216563 A JP H01216563A JP 4318788 A JP4318788 A JP 4318788A JP 4318788 A JP4318788 A JP 4318788A JP H01216563 A JPH01216563 A JP H01216563A
- Authority
- JP
- Japan
- Prior art keywords
- leads
- lead frame
- solder plating
- lead
- outer leads
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims description 11
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000000465 moulding Methods 0.000 claims description 3
- 238000007747 plating Methods 0.000 abstract description 12
- 229910000679 solder Inorganic materials 0.000 abstract description 10
- 239000000463 material Substances 0.000 abstract description 6
- 238000005476 soldering Methods 0.000 abstract description 6
- 238000003825 pressing Methods 0.000 abstract description 3
- 238000004080 punching Methods 0.000 abstract description 3
- 239000002184 metal Substances 0.000 abstract 2
- 239000004065 semiconductor Substances 0.000 description 10
- 230000007547 defect Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000007789 sealing Methods 0.000 description 4
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 238000007665 sagging Methods 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 235000015067 sauces Nutrition 0.000 description 1
- 238000007493 shaping process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Die Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本几明は、リードフレームの製造方法に係り、特に、そ
のアウターリードの形状加工法に関する。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to a method for manufacturing a lead frame, and particularly to a method for shaping the outer lead thereof.
IC,LSI等の半導体装置の実装に際して用いられる
リードフレームは、鉄系あるいは銅系等の金属材料から
なる板状体をプレス加工又はエツチングにより所望のパ
ターンに成形することによって形成される。Lead frames used for mounting semiconductor devices such as ICs and LSIs are formed by forming a plate-shaped body made of iron-based or copper-based metal material into a desired pattern by press working or etching.
通常、リードフレームは、第2図に示す如く、半導体集
積回路チップ(以下半導体チップ)を搭載するダイパッ
ド11と、ダイパッドを取り囲むように配設せしめられ
た複数のインナーリード12とインナーリード12を一
体的に連結するタイバー13と、各インナーリードに連
結せしめられタイバーの外側に伸張するアウターリード
14と、タイバー13を両サイドから支持するサイドパ
ー15.16と、ダイパッド11を支持するサポートパ
ー17とから構成されている。Usually, as shown in FIG. 2, a lead frame integrates a die pad 11 on which a semiconductor integrated circuit chip (hereinafter referred to as a semiconductor chip) is mounted, and a plurality of inner leads 12 arranged to surround the die pad. The tie bars 13 are connected to each other, the outer leads 14 are connected to each inner lead and extend to the outside of the tie bars, the side pars 15 and 16 support the tie bars 13 from both sides, and the support pars 17 support the die pad 11. It is configured.
このようなリードフレームを用いて実装せしめられる半
導体装置は第3図に示す如くであり、リードフレーム1
のダイパッド11上に、半導体チップ2を搭載し、この
半導体チップのポンディングパッドとリードフレームの
インナーリード12とを金線あるいはアルミ線のボンデ
ィングワイヤ3によって結線し、更にこれらを樹脂やセ
ラミック等の封止材料4で封止した後、タイバーやサイ
ドバーを切断し、アウターリードを所望の形状に折り曲
げて完成せしめられる。A semiconductor device mounted using such a lead frame is shown in FIG.
A semiconductor chip 2 is mounted on the die pad 11 of the semiconductor chip, and the bonding pads of this semiconductor chip and the inner leads 12 of the lead frame are connected with bonding wires 3 made of gold or aluminum wire, and these are further bonded with a bonding wire made of resin, ceramic, etc. After sealing with the sealing material 4, the tie bars and side bars are cut and the outer leads are bent into a desired shape to complete the process.
ところで、このようなリードフレームはプレス加工で成
型する場合、帯状材料をリードフレーム打抜用金型内で
連続的に打ち抜くことにより製造されるため、打ち抜か
れたリード表面は第4図(a)に示すように抜きダレd
に起因して凸面形状となる一方裏面は抜きばりbが生じ
る。By the way, when such a lead frame is molded by press working, it is manufactured by continuously punching out a band-shaped material in a lead frame punching die, so the punched lead surface is as shown in Figure 4 (a). As shown in d
Due to this, the surface has a convex shape, while a burr b is formed on the back surface.
ところで、アウターリードは、封止後、または封止前に
ほぼ全面に半田メツキが施され所望の形状に折り曲げら
れて、プリント基板などの外部回路に接続される。Incidentally, after or before sealing, the outer lead is soldered over almost the entire surface, bent into a desired shape, and connected to an external circuit such as a printed circuit board.
しかし、半田メツキに際し第4図(b)に示すようにこ
の抜きダレ部分には半田18がつきにくく、プリント基
板などの外部回路への接続に際し半田付は不良が発生す
ることがある。However, during solder plating, as shown in FIG. 4(b), the solder 18 is difficult to adhere to the sagging portion, and a soldering failure may occur when connecting to an external circuit such as a printed circuit board.
(発明が解決しようとする課題)
本発明は、前記実情に鑑みてなされたもので、半田付は
不良の発生を招くことなく、信頼性の高いリードフレー
ムを提供することを目的とする。(Problems to be Solved by the Invention) The present invention has been made in view of the above-mentioned circumstances, and an object of the present invention is to provide a highly reliable lead frame without causing defects in soldering.
そこで本発明のリードフレームの製造方法ではアウター
リードをコイニングする工程を付加するようにしている
。Therefore, in the lead frame manufacturing method of the present invention, a step of coining the outer lead is added.
アウターリードをコイニングする工程を付加することに
より、プレス工程で生じたアウターリードの抜きダレに
よる角部の丸みを除去し、幅方向断面の形状がほぼ四角
形となるようにしているため半田メツキは均一に付着す
る。このため、プリント基板などの外部回路への接続に
際し半田付は不良が発生することもなく信頼性の^い半
導体装置を提供することが可能となる。By adding the process of coining the outer lead, the rounded corners caused by the sagging of the outer lead caused by the pressing process are removed, and the shape of the cross section in the width direction is almost square, so the solder plating is uniform. Attach to. Therefore, it is possible to provide a highly reliable semiconductor device without causing soldering defects when connecting it to an external circuit such as a printed circuit board.
以下、本発明の実施例について、図面を参照しつつ詳細
に説明する。Embodiments of the present invention will be described in detail below with reference to the drawings.
本発明実施例の方法によって形成されたリードフレーム
は、平面図としては、第2図に示したものと同様の構造
を有しているが、アウターリードをコイニング後
ウターリードの断面形状が、上記コイニングによりほぼ
四角形となっている。The lead frame formed by the method of the embodiment of the present invention has a structure similar to that shown in FIG. 2 in plan view, but after coining the outer lead, the cross-sectional shape of the outer lead is This makes it almost rectangular.
次に、このリードフレームの製造方法について説明する
。Next, a method for manufacturing this lead frame will be explained.
まず、帯状材料の中央部に、第1の金型を装着し、プレ
ス加工を行なうことにより、タイバー13よりも内側す
なわちインナーリード12側をバターニングする。(第
1図(a))
次いで、この帯状材料を180°回転せしめ、両側部に
第2の金型を装着し、プレス加工を行なうことにより、
アウターリード14側をバターニングする。(第1図(
b)および第1図(C))ここで第1図(C)は第1図
(b)のA−Alli面図である。First, a first mold is attached to the center of the strip material and press working is performed to pattern the material on the inner side of the tie bar 13, that is, on the inner lead 12 side. (Fig. 1 (a)) Next, this strip-shaped material is rotated 180 degrees, second molds are attached to both sides, and press working is performed.
Buttering the outer lead 14 side. (Figure 1 (
b) and FIG. 1(C)) Here, FIG. 1(C) is an A-Alli plane view of FIG. 1(b).
続いてこの第2の金型内で、アウターリード14をパリ
を潰す程度にコイニング後
化し断面がほぼ四角形となるようにする。(第1図(d
))
そして最後に、アウターリード14を半田メツキ液中に
浸漬し表面に半田メツキ1116を形成する。(第1図
(e))
このようにして形成されたリードフレームは、素子チッ
プの搭載、ワイアボンディング、樹脂封止などの工程を
経た後、プリント基板上の回路パターンに接続されるが
、アウターリードの表面全体に均一なメツキ層が形成さ
れるため半田付は不良が発生することもなく信頼性の高
いものとなる。Next, in this second mold, the outer lead 14 is coined to the extent that the edges are crushed so that the cross section becomes approximately square. (Figure 1(d)
)) Finally, the outer lead 14 is immersed in a solder plating liquid to form a solder plating 1116 on the surface. (Fig. 1(e)) The lead frame formed in this way is connected to the circuit pattern on the printed circuit board after going through processes such as mounting the element chip, wire bonding, and resin sealing. Since a uniform plating layer is formed on the entire surface of the lead, soldering is highly reliable without causing defects.
なお、実施例では、半田メツキ工程を素子チップのW1
@に先立ち行うようにしたが、゛アウターリードのコイ
ニング後であればいつでも良く樹脂封止後に行うように
しても良い。In addition, in the example, the solder plating process was performed on W1 of the element chip.
Although this is done prior to @, it may be done at any time after the coining of the outer leads and after resin sealing.
また、実施例で°はタイバーを境界として、2つの金型
を用いて、プレスを行ったが、1つの金型で一度に全体
の形状を形成するようにしてもよい。Further, in the embodiment, pressing was performed using two molds with tie bars as boundaries, but the entire shape may be formed at once with one mold.
更に、コイニングは、表裏どちらから行なってもよい。Furthermore, coining may be performed from either side.
加えて、成型順序についても、実施例に限定されること
なく外側、内側の順に成型するようにしてもよい。In addition, the order of molding is not limited to the example, and the molding may be performed in the order of outside and inside.
以上説明してきたように、本発明のリードフレームの製
造方法によれば、アウターリードをコイニングして((
るため、アウターリード表面に形成される半田メツキ層
は均一となり、外部回路との接続に際し半田付は不良の
発生をなくし半導体装置の信頼性の向上をはかることが
可能となる。As explained above, according to the lead frame manufacturing method of the present invention, the outer leads are coined ((
Therefore, the solder plating layer formed on the surface of the outer lead becomes uniform, eliminating the occurrence of soldering defects when connecting to an external circuit, and making it possible to improve the reliability of the semiconductor device.
第1図(a)乃至第1図(e)は本発明実施例のリード
フレームの製造工程図、第2図は通常のリードフレーム
を示す図、第3図は通常の!P導体装置を示す図、第4
図(a)および第4図(b)は従来例のリードフレーム
のアウターリードを示す断面図である。
1・・・リードフレーム、2・・・半導体チップ、3・
・・ワイヤ、4・・・封止材料、°11・・・ダイパッ
ド、12・・・インナーリード、13・・・タイバー、
14・・・アウターリード、15.16・・・サイドバ
ー、17・・・サポートバー、18・・・メツキ層、d
・・・抜きダレ、b・・・抜きパリ。
第1図(b)1(a) to 1(e) are manufacturing process diagrams of a lead frame according to an embodiment of the present invention, FIG. 2 is a diagram showing a normal lead frame, and FIG. 3 is a diagram showing a normal lead frame! Diagram showing the P conductor device, No. 4
FIG. 4(a) and FIG. 4(b) are cross-sectional views showing outer leads of a conventional lead frame. 1...Lead frame, 2...Semiconductor chip, 3.
... wire, 4 ... sealing material, °11 ... die pad, 12 ... inner lead, 13 ... tie bar,
14... Outer lead, 15.16... Side bar, 17... Support bar, 18... Plating layer, d
...without sauce, b...without paris. Figure 1(b)
Claims (1)
ーリードをコイニングするコイニング工程とを 含むことを特徴とするリードフレームの製造方法。[Claims] A step of molding a lead frame including a plurality of inner leads, outer leads extending from the inner leads, and tie bars connecting these by a press working method, and coining of the outer leads. A method for manufacturing a lead frame, comprising the steps of:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4318788A JPH01216563A (en) | 1988-02-25 | 1988-02-25 | Manufacture of lead frame |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4318788A JPH01216563A (en) | 1988-02-25 | 1988-02-25 | Manufacture of lead frame |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH01216563A true JPH01216563A (en) | 1989-08-30 |
Family
ID=12656912
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4318788A Pending JPH01216563A (en) | 1988-02-25 | 1988-02-25 | Manufacture of lead frame |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH01216563A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0425059A (en) * | 1990-05-16 | 1992-01-28 | Nec Kyushu Ltd | Lead frame for semiconductor device and its production |
USRE43443E1 (en) | 1992-03-27 | 2012-06-05 | Renesas Electronics Corporation | Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two |
CN112018058A (en) * | 2020-09-08 | 2020-12-01 | 济南南知信息科技有限公司 | Power inverter module and manufacturing method thereof |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62198143A (en) * | 1986-02-26 | 1987-09-01 | Shinko Electric Ind Co Ltd | Lead frame |
JPS6313358A (en) * | 1986-07-04 | 1988-01-20 | Hitachi Ltd | Manufacture of semiconductor device and lead frame used for said manufacture |
-
1988
- 1988-02-25 JP JP4318788A patent/JPH01216563A/en active Pending
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS62198143A (en) * | 1986-02-26 | 1987-09-01 | Shinko Electric Ind Co Ltd | Lead frame |
JPS6313358A (en) * | 1986-07-04 | 1988-01-20 | Hitachi Ltd | Manufacture of semiconductor device and lead frame used for said manufacture |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0425059A (en) * | 1990-05-16 | 1992-01-28 | Nec Kyushu Ltd | Lead frame for semiconductor device and its production |
USRE43443E1 (en) | 1992-03-27 | 2012-06-05 | Renesas Electronics Corporation | Leadframe semiconductor integrated circuit device using the same, and method of and process for fabricating the two |
CN112018058A (en) * | 2020-09-08 | 2020-12-01 | 济南南知信息科技有限公司 | Power inverter module and manufacturing method thereof |
CN112018058B (en) * | 2020-09-08 | 2021-09-24 | 南京宏景智能电网科技有限公司 | Power inverter module and manufacturing method thereof |
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