JPS594339Y2 - Memory storage subsystem including interlaced series rotating memory storage elements - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION This invention relates to data processing apparatus, and more particularly to the use of memory storage subsystems employing memory storage elements that are accessed in a serial rotation manner.

The use of memory storage elements having a serially rotating character has been fairly well known.

Memory storage devices with the same functionality have been created using a number of different electromechanical and semiconductor technologies.

A common relevant feature here is the serial rotatability of these storage elements, defined as the feature in which each successive cell periodically approaches and leaves the access location of the memory storage element in a time-dependent manner (and possibly physically). be.

This characteristic determines the average time required to access a given cell based on the rotational speed of the memory storage element.

The length of time required to complete one complete revolution is called cycle time.

The average time required to access one cell given this characteristic is called average rotational waiting time.

Because it is desirable to reduce the average rotational latency, it is common practice to increase the rotational speed (ie, reduce the cycle time) of memory storage devices.

It is necessary to add that increasing the rotational speed comes with practical constraints such as increasing the input power, increasing the load on the physical and electrical components, and reducing the signal-to-noise ratio. be.

Since transfer time is the length of time it takes for a memory storage element to rotate from accessing one cell to accessing the next consecutive addressable cell, increasing rotational speed reduces transfer time. It will also happen.

In many cases, the rotational speed that ideally reduces the average rotational latency within acceptable limits of power, pressure, and signal-to-noise ratio will reduce the transfer time sufficiently to
The human output of the main access computer called PU (
Ilo) was found to affect capacity.

Extremely short transfer times also cause priority conflict problems between the 110 devices.

A common technique used to solve the problem of insufficient transfer time at ideal rotational speeds is called interlacing.

Physically consecutive cells within an interlay or memory storage element are recording means that are not sequentially addressed by the CPU.

A very simple example is how to sequentially address every second physical cell within a memory storage element (this is
(referred to as 1-to-1 interlacing).

This method doubles the transfer time without affecting the rotation time, and therefore does not affect the rotation waiting time.

When this interlacing method is applied, it sequentially addresses every third, fourth, or Nth physically consecutive storage cell depending on the desired relationship of rotational speed and transfer time.

The technique uses rotating memory storage elements, typically interlaced, to cause the CPU to transfer addresses and select the first cell in a block of consecutively addressable cells.
Coincide with the memory storage subsystem initiating the transfer of the requested data at the same time that the first addressed cell rotates past the access location of the memory storage element.

If the request from the CPU is a truly random address that is made asynchronously to the memory storage element cycle, the average rotational latency will be 1/2 of the memory storage element cycle time.

The present invention allows the transfer of a data block from a cell (other than the first) within the required data block by providing a means of predicting the address of the first cell to be transferred, thereby allowing the effective This reduces the average rotational waiting time.

In the present invention, a memory storage subsystem having interlaced series rotating memory storage elements utilizes an apparatus for maintaining the current rotational location of the memory storage elements.

Such devices are typically counters that are reset to an initial value when the first cell passes the memory storage element access location and increment as each successive cell rotates past the memory storage element access location.

In early electromechanical series rotating memory storage devices, the exact instant rotational speed was determined by electromechanical means, and the counter was synchronized to the memory storage device by any means.

This structure is called asynchronous to distinguish it from the synchronous nature of modern semiconductor memory storage devices, where the update of the counter and the immediate rotation rate are set to the same time reference.

A memory storage subsystem according to the present technology need only compare the value of this counter with the requested address transferred by the CPU.

If equality is determined by this comparison, the CPU begins accessing the memory storage element.

The present invention increments the value of the counter by providing the memory storage subsystem with the address of the next physically contiguous cell to be rotated into the memory storage element access location, and compares the counter with the address transferred in the CPU's access request. calculates the next physically accessible cell in the requested data block and transfers this calculated address to the CPU.

The CPU then begins accessing the memory storage element from a cell other than the first in the desired data block.

The present invention will be described based on an example using a generalized series rotating memory storage element of small capacity employing 4:1 interlacing.

After this explanation, a discussion will be made to explain the effects of using the same memory storage element that employs 2:1 interlacing.

Finally, we will discuss the effects of using a memory storage element with a larger capacity.

Figure 1 shows the general arrangement and shows the central processing unit (CP)
U) 10 is connected to the improved memory storage subsystem MSS 14 via lines 11.12.13.

Line 11 is used to transfer commands to MSS 14;
Line 12 is used to transfer replies from MSS 14 to CPU 10.

The multi-core cable 13 is connected to the CPU 1 via the buffer 26.
A bidirectional path for transferring data between MSE 24 and MS 814, buffer 26 blocks data from going to and from serially rotating memory storage element MSE 24 so that the transfers occur synchronously.

The function and nature of buffer 26 is well known and will not be described in detail here.

Data access to MSE 24 is at access location AP2
This is done via 5.

Line 41 is a bidirectional data line between buffer 26 and AP 25.

Oscillator O8C23 oscillates with a natural period approximately equal to the transfer time of MSE 24.

08C23 is synchronized with the rotation of MSE 24 by a synchronization signal provided via line 40.

As mentioned above, synchronizing the 08C23 from the MSE24 is typical of electromechanical memory storage devices.

If MSE24 is to be embodied in a semiconductor device,
It will probably work in sync with 08C23.

Since the invention is equally applicable to both structures, only the former will be shown here.

The waveform shaper WFS 22 receives the 0 signal via line 39.
It only converts the sine wave output of the 8C23 into a digital pulse train which is transferred to the counter 21 via line 38.

The pulse train advances the counter 21 once for each transfer, making it possible to maintain the address (or number) of the cell of the MSE 24 adjacent to the AP 25.

FIG. 2a functionally represents the format of MSE 24, which consists of 16 cells having addresses (or numbers) from 0 to 15.

These cells are arranged sequentially on the MSE 24, and when the memory storage element is rotated in the direction shown by the arrow,
Memory storage element access location AP25 is from 0 to 1
The 16 addresses up to 5 are sequentially accessed.

This is a form of non-interlaced series rotating memory storage element.

Figure 2b shows the format of counter 21, which is used to address the 16 cells of the memory storage element shown in Figure 2a.

When the cell located at address O rotates to AP25,
Counter 21 is cleared (ie all bit positions are set to O).

This happens when counter 21 counts one past 15 (all bit positions set to 1).

The memory storage element rotates past address 0 and moves to address 1.
When you move to the cell located at , the number of the counter increases (i.e., 1 is added to the binary number of the counter)
The quantor configuration represented by bit position 2° is set to 1 and bit positions 2'', 22 and 23 are all set to 0.

The counter is incremented in this way for each transfer until it reaches 15 (i.e. 2°, 21.22 and 23
are all set to 1).

At this point, AP 25 accesses the cell at address 15.

During the next transfer period, the memory storage element rotates to
25 is adjacent to the cell at address 0 and continues to rotate until the counter is cleared.

This completes one cycle of MSE 24, which then repeats again.

The function of the counter is to keep track of the addresses of the cells accessed by the AP 25 from time to time, and to keep track of the addresses of the cells accessed by the AP 25 at the same time.
4 to indicate one of the 16 cells.

Table A below shows the relationship between the 16 cell addresses of MSE 24 in Figure 2a and the 16 possible values of the counter in Figure 2b.

The reference column indicates each cell that AP 25 sequentially accesses from A to P and provides a convenient means of specifically representing one of the 16 entries in Table A.

The data in counter 21 is expressed as a binary number every 4 bit positions.

The last column is the memory storage element access pointer AP
25 represents the decimal address of the cell of the memory storage element located at 25.

FIG. 3a represents a memory storage device having 16 cells employing 4-to-1 interlacing.

This configuration uniquely represents the 16 cells of the memory storage device, but provides physically non-contiguous addresses.

As previously discussed, the interlaced configuration represents an increase in transfer time relative to non-interlaced memory storage elements without changing the rotational speed or average rotational latency.

The format shown in FIG. 3a is referred to as 4-to-1 interlaced because it represents an increase in transfer time of approximately a factor of 4 over a non-interlaced format using physically similar memory storage elements.

The memory storage element access location is indicated at AP25.

FIG. 3b represents a counter 21 configured to maintain the rotational position of a memory storage element configured similarly to FIG. 3a.

This sets the counter shown in Figure 2b to bit position 2°.
and 22, which is the same as bit positions 21 and 23 reversed.

Figure 3C illustrates this inverse relationship more clearly by showing a counter as in Figure 2b.

That is, the increment of the counter is performed at bit position 22 rather than at bit position 2°.

Table B is formatted similarly to Table A by designating by reference numbers A through P the parts accessed sequentially by AP 25.

4 to 1 of 16 cell memory storage elements formatted in Figure 3a by comparing Tables B and A.
This shows the effect of interlacing.

To further illustrate this example, the 16
Let us assume a memory storage element based on a memory storage element with 1 cells (ie 16 cells of memory storage with 4-to-1 interlacing).

The data written to and accessed in the 16 cells of the memory storage element are in four blocks of four consecutively addressed cells, with addresses O through 3 forming block 0, and addresses 4 and 3 forming block 0. 7 to 7 form block 1, addresses 8 to 11 form block 2, and addresses 12 to 15 form block 3.

This type of restriction on access to memory storage elements is generally common.

In FIG. 1, when CPU 10 desires to access a block of four cells from MSE 24, CPU 10 accesses the requested address of the first cell in the block (i.e. address 0+-prower 20 address 4+block 1, Address 8+-Block 2, Address 12+Block 3
) is transferred to DISA 15 via line 11.

FIG. 4a is transferred via line 11 to DISA 15.

FIG. 4a shows the phonimat of the address transferred via line 11 to DISA 15. FIG.

This contains four bit positions sufficient to identify (or address) one of the 16 cells of MSE 24.

The four bits at that address are the block number BN (i.e. one of four blocks in the MSE 24) and the word number WN (i.e. the number one of four cells in the block of four cells displayed). ).

As shown in FIG. 5a, DISA 15 receives RBN as the requested block number, RWN as the requested word number, and the requested address via line 11.

DISA 15 separates the requested block number RBN and forwards it to 1NT 16 via line 30 (see Figure 5e) and to C0M 17 via line 31 (see Figure 5C).

See also FIG.

It can be said that the contents of counter 21 correspond to the format of FIG. 4a.

Figure 3C, which is the format of the counter, is MSE 2
By comparing with Figure 4a the format of the address on 4 is that it is the block number BN, i.e. the field that is incremented in number (bit positions 22 and 23).
It will be understood that

By referring to Table B, it will be seen that the format in FIG. 4a can be used to represent the value of counter 21.

Counter 21 transfers its contents to DISB 20 via line 37 as shown in FIG.

DISB 20 disassembles the address (number of counter 21), transfers the block number to C0M17 via line 35 (see Figure 5C), and transfers the word number to line 36 (see Figure 5C).
(see Figure 5d) to ADDlB.

Figure 5b details the DISB 20 functionality.

As described above, the contents of the counter 21 are represented by the memory word number MWN and the memory block number MBN.

DISB 20 receives the MWN and MBN via line 37.

DISB 20 disassembles this address and MB
Transfer N to C0M17 via line 35 (see Figure 5C) and MWN to ADD via line 36 (see Figure 5D).
Transfer to IB.

FIG. 5C shows that the function of C0M17 is to compare the requested block number RBN with the memory block number MBN.

The RBN is received from DISA 15 via line 31 and the MBN is received from DISB 20 via line 35.

FIG. 5C shows C0M17 passing RBN via line 31 to M
It is shown that the BN is received via line 35.

A comparison by C0M17 is made to determine whether RBN is less than or equal to MBN or whether RBN is greater than MBN.

C0M17 sets line 33 to true if RBN<MBN
and set.

If RBN>MBN, C0M17 sets line 33 to false F.

As shown in FIG. 1, ADDlB senses line 33 from C0M17.

If line 33 is true, ADDlB is connected to DIS via line 36.
B Add 1 to the number received from 20.

If line 33 is false, ADDlB is connected to DI via line 36.
Do not add 1 to the number received from SB 20.

ADDlB transfers the qualified or unqualified number via line 32 to 1NT16.

Figure 5d shows the functionality of ADDlB in detail.

ADDlB receives memory word number MWN via line 36.

ADDlB adds 1 to MWN if line 33 is correct, and does not add 1 to MWN if line 33 is incorrect.

The quantity MWN rice that can be modified is 1NT1 via line 32
Transferred to 6.

As shown in FIG. 1, INT 16 connects to DI via line 30.
The quantity received from SA15 and the quantity received from ADDlB on line 32 are integrated, and the result is transferred to CPU 10 via line 12.

FIG. 5e details the functionality of 1NT16.

1NT 16 receives the requested block number RBN from DISA 15 via line 30 and the memory word number MWN which may be modified from ADDlB via line 32.

1NT16 integrates these two numbers and calculates CPU1
0 accesses the next address of MSE 24 within the same block of four addresses requesting via line 11, which is then accessed by AP 25.

The next calculated address consists of the required block number RBN and the optionally modified memory word number MWN, which is transferred to the CPU 10 via line 12.

Table C contains one requested address (i.e. 10□).

) for each possible value (i.e., memory address) of counter 21 is given a resulting address (i.e., the next address).

It will be appreciated that the embodiment described above is capable of generating the correct next address for each possible value (ie, memory address) of counter 21.

This requires creating 15 additional clothes formatted as in Table C.

In the embodiment shown here, each data block is an MSE.
It is applicable to memory storage devices formatted in such a way as to make 24 complete rotations.

In some cases, it is desirable to employ an interlaced format where a complete block is located at a portion of the rotation.

FIG. 6a shows an MSE 24 having 16 cells formatted with a 2-to-1 interlace.

In this example a complete block of four cells is MSE 24
It is giving within a thousand revolutions.

FIG. 6b shows the memory storage element access location AP25.
The format of the counter 21 representing the address of the cell located in is shown.

Note that the most significant bit position (ie, bit position 23) has increased.

The table shows each possible value that counter 21 can take as MSE 24 rotates.

As mentioned above, this two-to-one interlaced format locates a block of four cells within a + rotation of the MSE 24, which is a claimed block featuring a slightly different embodiment than the present invention. 4 cells are MSE 2
4, two situations can occur depending on the relative timing of the requests and the rotation of MSE 24.

Upon request, the + of MSE 24 containing the requested block is rotated through AP 25, or it is not.

In the former case, the present invention operates in much the same way as the previously described embodiments.

In the latter case, MWN US1 is always the first cell in the requested block.

In other words, the transfer of the requested block to the CPU is done by the MSE 24 at the time the request is received.
If not rotated through P 25, CPU-2's transfer of the requested block can always occur from the first cell in that block.

This can be realized very easily as shown in FIG.

FIG. 7 is a detailed diagram of a portion of the MSS 14 as shown in FIG.

The difference is that C0M17 is an additional function and line 42 has been added.

Additional functionality for C0M17 is that the requested block is currently A
The purpose is to measure whether or not the MSE 24 is located in the rotating part of the MSE 24 passing through the P25.

If C0M17 is the requested data block, the current AP
25 and is not within the rotating portion of MSE 24, C0M17 sends a signal to 1NT16 via line 42 to turn off all MWN rice.
Set to .

In this example, C0M17 compares the least significant bits of RBN and MBN.

If they are equal (i.e. 2°RBN = 1
=2°MBN or 2°BRMN20-2°MBN),
The requested data block has passed through AP 25 and is within the currently rotating portion of MSE 24 (ie, line 42 + false), and the MNW is determined as before.

If 2°RBN≠2°MBN, C0M17
notifies 1NT16 by setting line 42 as true.

As a result, the MWN whose INT1B is zero is transferred to the CPU 10.

The results of this addition function are shown in the example in Table E.

Note that this is constructed similarly to Table C, except that the state of line 42 is shown.

Whenever line 42 is true, MNW is zero.

Whenever line 42 is false, MWN is determined as described above (i.e., if RBN>MBN then M
If WN rice = MWNoRBN < MBN, then MWN rice = M
WN+1).

The invention presented herein is an interlaced series rotating memory storage device MS with a capacity of 16 cells or more.
Memory storage subsystem MSS1 with E24
It is easy to understand that this can also be applied to 4.

In one example of an MSE 24 with a capacity of 2M, the address format used to identify one cell of 2M cells (i.e., the requested address,
The memory address and next address) are shown in FIG. 4b.

The 2M cells of MSE 24 are formed as 2M-8 blocks with less than 2N cells per block.

Address format is M-N bit block number, BN
(i.e. RBN or MBN) and N-bit word number, WN (i.e. RWN, MWN or MWN)
generate.

16 arranged as 4 blocks divided by 4 cells
The embodiments described above in detail for the memory storage cell MSE 24 use an address format as in FIG. Although it is used, the block is M
occupies the entire rotation of SE 24).

Therefore, it will be readily understood by those skilled in the art that the present invention can be applied to a memory storage subsystem having 2M cells arranged in 2M-8 blocks each having 2N cells. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a diagram illustrating an improved serial rotating memory storage subsystem interfaced to a central processing unit. FIG. 2a is a diagram illustrating the format of a non-interlaced series rotating memory storage element. FIG. 2b shows the format of a counter for maintaining the rotational position of the memory storage element in FIG. 2a. FIG. 3a is a diagram illustrating the format of a serially rotating memory storage device employing 4-to-1 interlacing. Figure 3b shows the format of a counter for maintaining the rotational position of the memory storage element of Figure 3a. FIG. 3C shows an alternative format for a counter for maintaining the rotational position of the memory storage element of FIG. 3a. Figure 4a shows 1 arranged in 4 blocks each consisting of 4 words.
FIG. 3 illustrates an address word format using six cell memory storage elements. FIG. 4b shows an address word format using 2M cell memory storage elements arranged in M-N blocks of N words. FIG. 5a is a diagram illustrating disassembly of the improved memory storage subsystem element DISA. FIG. 5b is a diagram illustrating the disassembly function of the improved memory storage subsystem element DISB. FIG. 5C is a diagram illustrating the comparison functionality of the improved memory storage subsystem element COM. FIG. 5d is a diagram illustrating the selective addition functionality of the improved memory storage subsystem device ADD. FIG. 5e is a diagram illustrating the integrated functionality of the improved memory storage subsystem element INT. FIG. 6a is a diagram illustrating the format of a 16 cell series rotating memory storage device employing 2-to-f interlacing. Figure 6b is a diagram illustrating the format of a counter for maintaining the rotational location of the memory storage element in Figure 6a. Figure 7 shows element C0 in the format used in Figure 6a.
It is a figure which shows the modified operation|movement of M17. 10...Central processing unit (CPU), 14.
...Memory storage subsystem (MSS),
15...DISA, 16...INT,
17...COM, 18...ADD, 2
0...DISB, 21...Counter, 23...Oscillator, 24...Memory storage element (MSE).

Claims (2)

[Scope of utility model registration request] (1) A central processing unit (CPU) coupled to a memory storage subsystem that includes interlaced series rotating memory storage elements having a capacity of 2M cells.
), wherein the cells are synchronously accessible only at a memory storage access location as they rotate near the memory storage access location, and the cells of the interlaced serially rotating memory storage elements are block blocks. arranged as 2M-9 blocks with 2N cells each, and the 2N cells of each block.
cells are responsively coupled to the interlaced series rotating memory storage element and arranged in the data processing apparatus, wherein the cells are spaced equidistantly over a rotation of the interlaced series rotating memory storage element; a device 21 for maintaining the address of a cell proximate to an element access location; and any of the 2N cells of one of the 2M-8 blocks responsively coupled to said CPU and to be accessed by said CPU. a first transfer means 11 for transferring an address from said CPU to said memory storage subsystem; and an address determination device 15.16.17, 18.20 responsively coupled to said first transfer means, comprising: the request address transferred from the CPU, a request block number identifying one of the 2M-8 blocks to be accessed and a request identifying one of the 2N cells within the request block number; a first disk assembly device 15 responsively coupled to the address maintenance device for disassembling into word numbers, the address of the cell proximate to the memory storage element access location in one of the 2M-9 blocks; a second disk assembly device 20 responsive to the first and second disk assembly devices for assembling the cells into a memory block number identifying the memory block number and a memory word number identifying one of the 2N cells within the memory block number; a comparator 17 operably coupled to compare the requested block number with the memory block number; and a comparator 17 responsively coupled to the comparator and the second disk assembly device, the a device 18 for selectively incrementing the memory word number by one only when the comparator indicates that the requested block number is present; a device 16 for integrating with the memory word number, which may be modified by a selective addition device, to produce a determined address to be transferred to the CPU;
is responsively coupled to the address determining device and the CPU, for forwarding the determined address to the CPU, and for causing the determined address to cause the CPU to select the CPU of the one of the 2M-8 blocks; A second transfer means 12 that allows access to cells other than the requested address transferred from
and the memory storage subsystem. (2) Utility Model Registration In the data processing device according to claim 1, the memory storage subsystem is characterized in that M=4 and N=2.