JPS5937728A - Pattern generating circuit - Google Patents

Abstract

PURPOSE:To generate such a pattern with a specific period that a successive (L+i)-bit pattern appears only once within one period, by providing an L-stage maximum-length sequence pseudo-random pattern generator and a logical circuit which receives the output of the pattern generator and outputs an (i)-bit signal succeeding to L bits. CONSTITUTION:An L-bit pattern outputted by the L-stage M-sequence PN generator 1 which has a means set in an initial state is inputted to an (L+1)-bit (i=1, 2-N-L) pattern detecting circuit 4. The output signal of the L-stage M- sequence PN generator 1 is supplied to the logical circuit 3, which outputs an (i)-bit pattern which is out of phase with the L-bit pattern and determined univocally by the L-bit pattern. Namely, the (i) bits correspond to the (i)-bit pattern following a forecasted L-bit PN pattern. This L-bit pattern and (i)-bit pattern are detected to initialize the L-stage M-sequence PN generator 1 and logical circuit 3.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a slam generation circuit that generates a PN sequence with a specific period by adding a feedback loop to an uncircuit that generates a maximum flame sequence pseudo-random bang (M-sequence PN bang), and particularly relates to a The present invention relates to a bang generation circuit that generates a bang consisting of a plurality of consecutive bits or a bang that appears only once within one cycle of a PN sequence.

Generally, in time-division multiple access satellite communication systems, at the time of initial connection, a low-power signal is transmitted continuously with a period of N sequences equal to the number of bits in one frame, and this signal is assigned to the local station. When receiving in the time slot set, a part of the PN signal sent by the own station is received. This reception P
By comparing the N signal and the transmitted PN signal, transmission time information for that station can be obtained. This is the so-called low power transmission axilon method.

The PN sequence with a repetition period equal to one frame period, which is used in this low-power transmission acquisition method, must be a PN sequence that has the property of appearing only once in one period, such as a bang consisting of consecutive multiple bits. There is. A circuit that generates a bang with such characteristics is an L-stage (L is an integer) M-sequence I) pattern that detects the L bits of the output of the N generator and sets the M-sequence PN generator to its initial state. method (L-bit bang detection set method) was used.

FIG. 1 is a block diagram of a conventional pattern generation circuit.
This shows the configuration of a circuit that sets . In this circuit, a part of the output PN pattern of the M sequence I)N generator 1 with a period of 2L-t is taken out and connected to the button detection circuit 2 to create a pattern with a specific period (N bits). ing. In this case, in order to prevent the continuous L-pit button newly created in the connected part from appearing in other parts, it is necessary to carefully select the button to be detected and the button to be connected. , it took a lot of effort to select the button, there were only a very limited number of button types, and as a result, the pattern detection circuit and set circuit were complicated. .

A first object of the present invention is to provide a bang generation circuit that can easily detect a repeated bang of a specific cycle that does not appear twice within the same cycle.

A second object of the present invention is to provide a bang generation circuit that can easily obtain a set of drums that appear twice in the same cycle and that are set to repeat a specific cycle. .

A third object of the present invention is to provide a button generation circuit that can generate continuous N-bit bumps in any part of an M-sequence PN pattern with a length of 2L-1.

The configuration of the bang generation circuit of the present invention includes a maximum length sequence pseudo-random bang generator with L stages (L is a natural number) that can be set as an initial bang, and an output of L bits of this pattern generator. A logic circuit that outputs the i-pit signal that follows the L-bit of this pattern generator whose phase is different from that of the pit output, and the i-bit output signal of this logic circuit and the L-bit output of the MJn pattern generator. Enter the signal (7) L -t-! (1) An L-1-1 bit slam detector detects a match between a no-button and a predetermined no-button, and when this no-button detector detects a match, the no-button occurrence 2 diagnosis and the logic circuit are set to a predetermined initial state. The present invention is characterized in that it includes an initial setting means for making a -hit along with the nobutan, and forms a specific periodic pattern in which a continuous L+t pit pattern appears only once within a - period.

The present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram of an embodiment of the present invention.

L stage M series 11P with means to set to initial state
The L pit output from the N generator 1 is input to the L-bit (i=1, 2, . . . NL) detection circuit 4. In addition, the output signal of the 4-series PN generator 1 of the s II stage is input to the logic circuit 3, and the i1% L bit button has a different phase from the i1% L bit button, and the i pit node is uniquely determined by the L pit node. Output. In other words, this i-pit is converted into a 1-bit pattern that comes after the L-bit PN pattern that has been previously set to 11111.

Detecting this L bit bang and i bit pattern, L stage M
By setting the sequence PN generator 1 and the logic circuit 3 to their initial states, it is possible to obtain periodic repetition of the button.

For example, consider the case where L=5. Figure 3 is L
= 5, this 5-stage M-sequence PN button generator generates a PN pattern with a maximum period of 31 bits, but this PN pattern yields a multi-period 16-bit button. Suppose we want to form a circuit.

In the conventional L-bit slam detection set method, as shown in FIG.
When set to 101, N=16 (16-bit HMA11 pattern J) repeats from the 14th to the 29th of the 31-bit PN pattern in Figure 3, and from 5 consecutive bits within one cycle. Narubatan only appears once. A button with such properties is selected by finding a button among the 31-bit M-sequence PN buttons that differs in only the first 1 bit among 5 consecutive bits with a mutual phase difference of 16 bits. . In Figure 3, i
], 011 and Oi O11 are the only ones that satisfy the above conditions. In this way, among the M sequence nodes in L stages, the phase difference between each other is N bits, and among consecutive L bits, only the first 1 pit differs from each other is M sequence 1) 1 out of N pattern periods. It only appears once. Therefore, the N-bit cycle pattern obtained in this manner is the only limited part of the M-sequence PN pattern.

On the other hand, according to the present invention, L=5. If the number of detection bits for N=16 is 7, then i=2. As shown in FIG. 5, if a detection pattern 1oioooo is detected and a set pattern 111.1100 hits one hit, the pattern of consecutive 7 bits in one cycle is a 16-bit cycle pattern that appears only once. can get. Of these detection bits, 5 bits can be obtained from the output of M-sequence PN generator 1, and the remaining 2 bits can be obtained from the M-sequence PN generator 1.
It can be easily obtained by a shift register that shifts the final stage output of the generator 1 by 2 bits. Furthermore, an exclusive OR circuit can be used in place of this shift register.

In addition, if the new pattern that is created by splicing is an M-series continuous 7-bit pattern, it is sufficient to check whether that pattern is included in the extracted N-bit pattern. If it is not, there is no need to search among the M series patterns. Furthermore, by increasing the number of bits to be detected (L+i), the M sequence P
Any part of the N patterns can be extracted and used as a specific periodic pattern. For example, the operation of the clock synchronization circuit can be facilitated by making an acquisition using the iJN pattern in a portion containing a relatively large number of 1010 patterns.

Once the PN pattern to be extracted is determined, the necessary value of 1 is determined, but as 1 increases, the scale of the detection circuit also increases accordingly, so the minimum value of i that requires general prudence is selected.

In addition, in the explanation of FIG. 3, L=5. Explanation of the case where N=16 1. However, in general, the present invention is still applicable when both N are natural numbers.

In the low-power transmission acknowledgment method, the pattern generation circuit according to the present invention is used to transmit a pattern using the pattern generation circuit according to the present invention. By detecting the distance IWft
You can get information.

As explained above, according to the present invention, it is possible to obtain a retrospective pattern of a specific period in which the same pattern does not occur twice within a period, but the detected pattern tfc can easily obtain a set pattern. It is possible to generate a continuous N-bit pattern of any part of the M-sequence PN pattern.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a conventional bang generation circuit, Fig. 2 is a circuit block diagram of an embodiment of the present invention, Fig. 3 is a pattern diagram of a 4-series PN button to 5 stages, and Fig. 4 is a 5-stage M series. FIG. 5 is a button diagram of an example of a detection and set pattern of a 5-stage M series according to the present invention. In the figure, 1...M-sequence PN generator, 2...
. . . L bit bang detection circuit, 3 . . . logic circuit, 4 . . . L+i bit bang detection circuit.

Claims (1)

[Claims] The L-stage (L is a natural number) maximum flame series pseudo-Randano-battan generator that can be set as an initial batan is input, and the L-bit output of this batan generator is input, and the phase is different from the output of this L-bit. A logic circuit that outputs an i (i is a natural number) bit signal after the L pit of this bang generator, a 1-bit output signal of this logic circuit, and an L-bit output signal of the bang generator are input. an L+i pit bang detector for detecting a match between Shiko's L+i bit bangs and a predetermined bang; and initial settings for setting the above-mentioned bang generator and the logic circuit to predetermined initial beats when the bang detector detects a match. 1. A bang generating circuit, comprising means for forming consecutive L+i pit bangs or a specific periodic bang that appears only once within a - period.