JP2765682B2 - CSK communication device - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a method and apparatus for spread spectrum (SS) communication, in particular, code shift keying (Code Shift Keying).
The present invention relates to a CSK communication apparatus in which a data demodulation method in a shift keying (CSK) modulation scheme is improved.

[Prior Art] The SS communication method has been widely applied to power line communication in addition to satellite communication and mobile communication. A conventional SS communication method will be described with reference to FIGS. 14 and 15. On the transmitting side, an output a of a PN (pseudo noise) code sequence generator 1 is subjected to an EX-OR operation (signal c) by a transmission data b and an E-OR circuit 2 (signal c), and then transmitted to a transmission path by an amplifier 3 as a transmission signal. On the receiving side, the received signal is amplified by the amplifier 4 and then synchronized by the correlator 6.
The output data d of the code sequence generator 5 is correlated, the correlation value (signal e) is compared with a predetermined function by the comparator 7, and the received data f is demodulated.

The transmission path may be a wireless, wired, or other transmission medium. Therefore, in many cases, the transmission signal is not only sent directly to the transmission medium, but also converted into a signal suitable for transmitting the transmission medium and sent. Also, power line communication requires an interface that is separated from commercial power. In the following, a connection portion with a transmission medium that performs such signal conversion and separation functions is referred to as a reception interface and a transmission interface.

[Problems to be Solved by the Invention] In the conventional communication system, the PN sequence generated by the synchronous PN code sequence generator 5 on the receiving side must be synchronized with the PN sequence on the transmitting side. Need to be searched. If there is no problem in the transmission characteristics of the transmission path, a peak is detected in the correlation waveform at the synchronization point. However, in the case of transmission lines with extremely poor transmission characteristics, such as power line communication, and in which there is a dip point in the transmission band, the deterioration of the correlation waveform progresses, and the positive / negative relationship of the correlation values is reversed, and the data 1,0 May be wrong. Further, there is a disadvantage that synchronization cannot be maintained due to deterioration of the waveform.

An object of the present invention is to provide a novel CSK communication device that overcomes the above-mentioned drawbacks of the conventional SS communication system.

[Means for Solving the Problems] In order to achieve the above object, the present invention generates first and second PN code sequences having the same code length different from each other at a fixed period, and transmits transmission data every fixed period. For 0, the first PN code sequence is selected, and for 1 of transmission data, the second PN code sequence is selected, and the selected PN code sequence is transmitted as a transmission signal. Receiving the transmission signal and performing a correlation operation on the received signal using the same first and second PN code sequences used on the transmission side to obtain first and second correlation outputs, respectively; The output is observed by dividing a data section having the same width as the fixed period into a main observation section including a time point at which a correlation peak appears and a sub-observation section other than the main observation section, and a peak value of the first correlation output in the main observation section. And the second correlation output The peak value of the first product and the second correlation output obtained by multiplying the sum in the sub observation section in the main observation section is multiplied by the sum of the first correlation output in the sub observation section. Are obtained, and these first product and second product
Are compared with each other, and when the first product is larger than the second product, data 0 is regarded as demodulated data, and the second product is the first product.
And a receiving device that uses the data 1 as demodulated data when the product is larger than the product of

Further, the present invention is characterized in that the receiving apparatus determines the main observation section at a substantially central portion of the data section, and defines the sections on both sides of the central section as the sub-observation sections.

[Operation] A CSK (Code Shift Keying) communication device generates first and second PN code sequences having the same code length with a low cross-correlation from a transmitting device at fixed periods, respectively.
The first and second transmission data correspond to 0 and 1 of the transmission data, respectively.
A PN code sequence is selected and transmitted as a transmission signal. On the other hand,
The receiving device receives the received signal and the first and second signals used on the transmitting side.
The first and second correlation outputs are obtained by taking a correlation with the 2PN code sequence. Further, the first product obtained by multiplying the peak value of the first correlation output in the main observation section by the sum of the second correlation output in the sub observation section and the peak value of the second correlation output in the main observation section And a sum of the first correlation output in the sub-observation section to obtain a second product, and compare the first product and the second product with each other.
If the first product is greater than the second product, data 0 is demodulated data, and if the second product is greater than the first product, data 1 is demodulated data.

Embodiment Hereinafter, an embodiment in which the present invention is applied to a CSK communication apparatus using a Manchester code M sequence as a PN code sequence will be described in detail.

(1) Overall Configuration of CSK Communication Device FIG. 1 shows the overall configuration of a CSK communication device using a Manchester code M sequence, in which a transmitting device and a receiving device are manually connected via a transmission line or a transmission medium. . A modulator (transmitter) 11 in the transmitter includes two Manchester M-sequence generators 31 and 32 which generate Manchester M-sequences having low cross-correlation and the same code length in synchronization with each other.
Are provided, and their sign outputs are supplied to the switching circuit 33. This switching circuit 33 is used to transmit binary transmission data (0 or 1).
For example, when the transmission data is 0, the code output of the generator 31, that is, the first PN code sequence is selected, and when the transmission data is 1, the code output of the generator 32, that is, the second PN code sequence is selected. The code output signal selected by the switching circuit 33 becomes the transmission signal TXO. Switching circuit 3
The switching control in (3) is performed in synchronization with the cycle of the generated Manchester code M sequence, and one binary data (0 or 1) is generated by one cycle of the Manchester code M sequence, that is, the first or second PN code sequence. Is expressed.

Since the switching or selection of the two different Manchester code M sequences is performed according to the code (1 or 0) of the data to be transmitted, this modulation method is called code shift keying (CSK). Of course, the CSK is not limited to the Manchester M sequence, and other PN code sequences may be used.

The transmission signal TXO is transmitted to a transmission path or a transmission medium via the transmission interface 12A. Transmission interface 12A
Is a connection part in a broad sense, as shown in the section of [Prior Art], and is a part for performing carrier modulation or mixing processing to a power line.

The reception interface 12B also performs demodulation of a carrier, separation from a power line, A / D conversion, and the like, and converts a signal input from a transmission path or a transmission medium into a digital reception signal RXI and outputs the signal. The receiving device on the receiving side includes two correlators 21 and 22, a demodulation device 23, a carrier detection circuit 24, a synchronization control circuit 25, and the like. The digital reception signal RXI output from the reception interface 12B is branched into two and input to the correlators 21 and 22, respectively. The Manchester code M sequence generated from one Manchester M sequence generator 31, that is, the first PN code sequence is set in one correlator 21, and the correlation between the first PN code sequence and the received signal RXI is determined. Be taken. Similarly, a Manchester code M sequence generated from the other Manchester M sequence generator 32, that is, a second PN code sequence is set in the other correlator 22, and the second PN code sequence and the received signal RXI are Are correlated. The first and second correlation outputs obtained from these correlators 21 and 22 are provided to a demodulation device 23, where demodulation data 0 or 1 is assigned according to the correlation value and output as reception data RXD. Is done. Specifically, for example, the correlator 21
When the correlator 21 shows a larger correlation peak value among the correlation outputs of the signals 22 and 22, the received data of 0 is conversely output.
When 22 has a larger correlation peak value, one received data can be used as demodulated data.

The correlation output is also input to a carrier detection circuit 24 and a synchronization control circuit 25. The carrier detection circuit 24 detects the presence or absence of a carrier based on the correlation output, and supplies the detection signal to the synchronization control circuit 25. The presence or absence of the carrier is used to determine whether or not the received signal RXI is being received. The synchronization control circuit 25 generates a timing signal for demodulation and carrier detection based on the correlation output when the carrier is detected, and outputs the demodulation device 23 and the carrier detection circuit
Give 24.

As described above, in the CSK communication apparatus, the two correlation outputs are compared on the receiving side, and the 0 of the received data is determined according to the magnitude of the correlation output.
Alternatively, since 1 can be assigned, the Manchester M sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side, and no data demodulation error occurs. In addition, if an absolute value is taken as the output of the correlator, no error occurs even in the case of a transmission line having characteristic deterioration such that the transmission peak value is negative. Further, by using the Manchester code M sequence, it is possible to reduce the low-frequency component of the received signal and suppress the coupling loss with the transmission path.

(2) Configuration Example of CSK Modulator FIG. 2 shows a specific configuration example of the CSK modulator 11. FIG. 3 shows the output signal waveform of each part of this circuit.

In this embodiment, each Manchester M-sequence generator 31, 32
The shift register FF ₁₁ to ff ₁₃ of three stages _{(n = 3), FF 21} ~
FF ₂₃ , these shift registers are clock generators
The data shift operation is performed at the timing of the clock signal CK output from 34. The feedback circuits of these shift registers are different from each other. That is, shift register FF
_{In 11 to} FF ₁₃ , the signs of the cells in the second and third stages are fed back to their input sides via an exclusive-OR circuit (EX-OR) 31a, whereas the shift registers FF _{21 to} FF _{At 23} , the signs of the cells in the first and third stages are fed back via the EX-OR circuit 32a. The shift register and its feedback circuit are an M-sequence generator (PN
A code generator and a PN code = Pseude Noise Code = pseudo noise code) are respectively configured. Then, the exclusive OR of the code output of the last stage of each shift register and the clock signal CK is taken by the EX-OR circuits 37 and 38, respectively, to create a Manchester code.

A phase synchronization circuit is provided so that the other Manchester M-sequence generator 32 always has a constant phase (initial phase) when one Manchester M-sequence generator 31 has a specific phase (all 1s). This phase synchronization circuit includes a NAND circuit 36 and an initial phase setting unit 35. Initial phase setting device 35 is for setting an initial code in each stage of the shift register FF ₂₁ ~FF _23, can be set arbitrary code (all non-zero code). When the sign of all the stages of the shift register FF ₁₁ to ff ₁₃ becomes 1 (this state is caused once a period T of the Manchester code M series) L-level signal from the NAND circuit 36 is generated The sign set in the initial phase setting unit 35 at the time of the next rising of the clock signal CK is the shift register.
To each stage of the FF ₂₁ ~FF ₂₃ is loaded.

As described above, the outputs of the Manchester M-sequence generators 31 and 32, that is, the outputs of the EX-OR circuits 37 and 38, are provided to the switching circuit 33, and are transmitted by the transmission data TXD for each cycle (data section) T of the Manchester code M-sequence. A switching operation is performed.
The output of the NAND circuit 36 is provided to a transmission data processing unit (for example, a microprocessor) as a transmission request signal. The transmission data processing section outputs one bit (1 or 0) of the transmission data TXD every time the transmission request signal is input, and supplies it to the switching circuit 33.

FIG. 4 shows a modification. Compared to Fig. 2,
EX-OR circuit from Manchester M-sequence generators 31 and 32 respectively
37 and 38 are removed, and the output of the switching circuit 33 and the clock signal CK are input to the output side of the switching circuit 33 instead.
An EX-OR circuit 39 is provided to create a Manchester code. Reference numerals 31A and 32A indicate M-sequence generators, respectively.
These outputs (signs of the last stage of the shift register) are given to the switching circuit 33, respectively. This variant is
This has the advantage that the number of EX-OR circuits can be reduced by one.

A circuit may be provided on the output side of the switching circuit 33 in FIG. 2 and on the output side of the clock latch EX-OR circuit 39 in FIG. 4 so as to shape the waveform of the transmission signal TXO.

(3) Configuration Example of Correlator Next, the configuration of the correlators 21 and 22 will be described in detail with reference to FIG.

The correlators 21 and 22 include N-stage registers 41a and 41b, respectively.
In these registers 41a and 41b, Manchester code M sequences generated by Manchester M sequence generators 31 and 32 included in the modulation device 11, that is, first and second PN code sequences are set in advance. The code length of the M sequence generated using the n-stage shift register is 2 ⁿ -1 bits.
In the modulator 11, since the M-sequence is Manchester-coded, the number of stages N of the registers 41a and 41b is N = 2 (2 ⁿ -1).

On the other hand, the digital reception signal RXI input from the reception interface 12B is branched into two and input to the shift registers 42a and 42b provided in the correlators 21 and 22, respectively. These shift registers 42a and 42b also have N stages, and are driven by a clock CK having a frequency twice the frequency of the clock signal in the modulation device 11.

In the correlator 21, the EX-OR circuit 43a compares the sign of each stage set in the register 41a with the sign of the received signal sent to the corresponding stage of the shift register 42a. The output signals of all the EX-OR circuits 43a are provided to an adder 44a and added. The output signal of adder 44a is
1a represents the degree of coincidence between the code of each stage corresponding code and the shift register 42a of each stage, this is the correlation output R _a that is, the first correlation output of one of the correlators 21. Since the reception signal RXI is sequentially shifted in the shift register 42a for each clock signal CK, the correlation output _Ra is also changed to the clock signal CK.
Changes accordingly.

Similarly, in the other correlator 22, the register 41b
The EX-OR circuit 43b checks whether or not the sign of each stage set in the register and the sign of the received signal sent to the corresponding stage of the shift register 42b match. All EX
The output signal of the -OR circuit 43b is provided to the adder 44b and added. The adder 44b outputs a correlation output _Rb indicating the degree of correlation between the Manchester M sequence set in the register 41b, that is, the second PN code sequence, and the input digital received signal RXI, that is, a second correlation output. Become.

FIG. 6 shows a modification of the correlator 21. Register 41
Instead of a and the shift register 42a, a register 41A and a shift register 42A having N × m stages (m is a positive integer of 2 or more) are provided. Shift register 42A is driven by the clock signal CK _m of m times the frequency of the clock signal CK. N × m EX-OR circuits 43A are also provided, and the signs of the corresponding stages of the register 41A and the shift register 42A are EX-O
Input to R circuit 43A. Adder 44A is connected to all EX-OR circuits 43
By adding the output signal of the A and outputs a response signal R _a. As described above, the accuracy of the correlation operation is increased by increasing the number of stages of the register and the shift register by m times. It goes without saying that the correlator 22 can be similarly modified.

FIG. 7 shows still another embodiment. Here, the shift register 42 to which the received signal RXI is input is correlated with the correlators 21 and 22.
And is also used in. By doing so, the number of shift registers can be reduced and the configuration can be simplified. It goes without saying that the shift register whose number of stages is m times as shown in FIG. 6 can be shared by the correlators 21 and 22 in the same manner.

(4) Demodulation device and carrier detection circuit FIG. 8 shows an example of the configuration of the demodulation device 23 and the carrier detection circuit 24. FIG. 9 shows the signal waveform of each part in FIG. In this figure, the correlation outputs R _a and R _b are drawn in analog form for easier understanding.

First correlation output R _a which is output from the correlator 21 and 22 a pair
First, the principle of demodulating data based on and the second correlation output _Rb will be described. Referring to FIG. 9, one data section T
(This is equal to one cycle of the Manchester M sequence) is divided into a central window section (referred to as a main observation section W) and a portion before and after the window section (referred to as a sub observation section E section). The front and rear E portions are set at equal intervals. Of course, it is not necessary to set the E portion before and after the W portion equally, and the W portion may not be set at the center of the data section, but here, 0 <d
Using d that satisfies <T, the W part is a section of (T−d) / 2 to (T + d) / 2, and the E part is 0 to (T−d) / 2 and (T + d) / 2 to T The section is defined.

If data is being transmitted, data section T
, A correlation peak appears in one of the first correlation output _Ra and the second correlation output _Rb . In the synchronization control circuit 25, the correlation peak is detected, and a data section end signal ED that defines the end point of the data section is created so that the correlation peak is located at the center of the data section T. Then, based on the data section end signal ED, the window control pulse 25 and the window start pulse WL and the window stop pulse WH respectively defining the start point and the end point of the W section are generated.

Determining code _{P aW, P bW, A aE} , the meaning of A _bE as follows.

P _aW : Peak value (maximum value) of the first correlation output _{Ra in} the W section P _bW : Peak value (maximum value) of the second correlation output _{Rb in} the W section A _aE : First correlation output R _a (Addition value) A _bE in the E section of (a): The sum (addition value) of the second correlation output _{Rb in} the E section (reception data RXD) is generated as follows.

_{P bW · A aE> P aW} · A bE if data is _{1, P bW · A aE <} P aW · A bE if data is 0.

In this case, theoretically, if P _bW > P _aW , the data may be determined to be 1, and vice versa. However, considering the case where noise is included, demodulation errors may occur in the comparison of peak values in the correlation output. In general, in a correlation output having a correlation peak, the level before and after the peak is smaller than the correlation level of a correlation output having no correlation peak. For example, the second correlation output R _b
If there is a correlation peak, the sum A _bE before and after it is less than the sum A _aE of the first correlation output R _a no correlation peak. Utilizing this property, the product of the peak value and the sum of the correlation outputs that are separate from each other, that is, the first product P _aW · A _bE and the second product P _bW · A _aE are set so that a demodulation error does not occur as much as possible. That is, the demodulation data is created by comparing the magnitudes of. As a result, the data if _{P bW · A aE -P aW ·} A bE> 0 is _{1, P bW · A aE -P} aW · A bE <0 if the data is 0, is demodulated as.

That is, the first product P _aW · A _bE, which is obtained by multiplying the sum A _bE in the sub observation interval of the peak value P _aW and second correlation output R _b in the main observation interval of the first correlation output R _a And the second
The peak value P _bW of the correlation output R _{b in} the main observation section and the first
The second product P _bW · A _aE obtained by multiplying the sum A _aE in the sub-observation section of the correlation output of is obtained, and the first product P _aW · A _bE and the second product P _bW · A _aE are obtained. and compares each other, the peak value P _bW or P _aW give the product P _bW · a _aE or P _aW · a _bE value the larger
Correlation output R _b having, based on a corresponding relationship between the PN code sequence and the transmission data used in the correlation calculation of R _a, can generate demodulated data 1 or 0.

Next, the principle of carrier detection will be described. That is, when the absolute value of _{(P bW · A aE -P aW} · A bE) exceeds a predetermined threshold level Th _p, and carrier detection. The presence of the carrier means that a correlation peak appears in one of the correlation outputs. Therefore, the absolute value of the difference between the second product and the first product shows a large value. On the other hand, when there is no carrier, the absolute value of the difference between the products shows a value very close to zero. This makes it possible to determine the presence or absence of a carrier without being affected by noise or the like, as in the case of data demodulation.

Although the circuit shown in FIG. 8 operates in synchronization with a clock signal CK or CK _m from a digital circuit, shown in the clock signal for simplicity of explanation are omitted.

In this circuit, a first correlation output _Ra is supplied to _a latch circuit 51.
After being latched by the clock at a, it is converted to an absolute value by an absolute value circuit 52a, and further supplied to an adder circuit 55a and a maximum value hold circuit 54a. On the other hand, a window start pulse WL and a window stop pulse WH are input to the window generating circuit 53, and a window signal WS which becomes H level in the W section is output from the circuit 53. The window signal WS is supplied as an operation control signal to the latch circuit 48 of the adder circuit 55a and the latch circuit 46 of the maximum value hold circuit 54a.

In the adder circuit 55a, the latch circuit 48 operates only in the E section where the window signal WS is at the L level. Latch timing is, of course, defined by the clock signal. First correlation output R _a that is absolute value sequentially input, is summed with the previous addition result and the adder 47 supplied from the latch circuit 48 every clock signal, the addition result is again the latch circuit
Latched at 48. In this manner, data representing the sum _AaE is obtained from the adder circuit 55a, and is provided to the multiplier 56a.

The latch circuit 46 of the maximum value hold circuit 54a operates only in the W section where the window signal WS is at the H level. Latch circuit 46
And the absolute value of the first correlation value R _a which is the maximum value and the current input to the last being latched are compared by the comparator 45, the new correlation value for this time when the direction of current of the correlation value larger The maximum value is latched by the latch circuit 48. In this manner, data representing the peak value _PaW is obtained from the maximum value hold circuit 54a, and is provided to the multiplier 56b.

Similarly, for the second correlation output _Rb , the latch circuit
51b, an absolute value circuit 52b, a maximum value hold circuit 54b, and an adder circuit 55b are provided. The peak value P _bW from the maximum value holding circuit 54b is the sum A _bE from the adding circuit 55b is obtained each multiplier 56a, is provided to 56b.

The multiplier 56a performs multiplication for obtaining a second product P _bW · A _aE , and the multiplier 56b performs multiplication for obtaining a first product P _aW · A _bE. And a subtraction / absolute value circuit 59.

The comparator 57 compares the _{magnitude of} the second product P _bW · A _aE with the magnitude of the first product P _aW · A _bE , outputs a signal representing 1 or 0 according to the comparison result, and outputs a data section end signal. At the timing of ED, the data is latched by the latch circuit 58 and output as the reception data RXD. The adder circuits 55a and 55b and the maximum value hold circuits 54a and 54b are reset by the data section end signal ED.

On the other hand, the subtraction / absolute value circuit 59, subtraction and the absolute value of for the second product and the first product of the difference _{(P bW · A aE -P aW} · A bE) is performed, the calculation result Is compared with the threshold value Th _{p in the} comparison circuit 60, and if it is larger than Th _p , the carrier detection signal PAS is output.

(5) Configuration Example of Synchronization Control Circuit FIG. 10 shows a configuration example of the synchronization control circuit 25. The synchronization control circuit 25 includes a peak position detection circuit 28A, a peak position determination circuit 26B, a synchronization establishment determination circuit 28, an out-of-synchronization determination circuit 29, and the like.

The peak position detection circuit 26A is a circuit for detecting the position in the data section T where the peak of the correlation output is located. As shown in FIG. 11, the peak position PP is determined when the maximum value of the correlation output appears. Is measured as the time from to the data section end signal ED. In this embodiment, two correlation outputs R _a
The position where the absolute value of the sum of _Rb and _Rb shows the maximum value is the peak position.

The two correlation outputs _Ra and _Rb are provided to an adder 61, respectively, added, and converted into absolute values by an absolute value circuit 64. This absolute value signal is applied to one input terminal of comparator 62 and latch circuit 83. Signal indicating the end of the previous data section
When ED is supplied to the latch circuit 63 as a latch timing signal via the OR circuit 65A, the output of the absolute value circuit 64 is latched as an initial value. The value latched in the latch circuit 63 is provided as another input of the comparator 62. Therefore, thereafter, the value latched by the latch circuit 63 and the output value of the absolute value circuit 64 are sequentially compared by the comparison circuit 62 (for each clock pulse of the clock signal CK), and are compared with the latched values. When a large value output is obtained from the absolute value circuit 64, the output of the comparator 62 is given to the latch circuit 63 via the OR circuit 65A, so that the output of the absolute value circuit 64 is sent to the latch circuit 63 as a new value. Latched. Thus, the maximum value is always latched in the latch circuit 63.

On the other hand, the counter 66 that counts the clock signal CK is reset (cleared) by the data section end signal ED input through the OR circuit 65B or the comparison output of the comparator 62, and starts counting again from zero. The count output of the counter 66 is latched by the latch circuit 67 when the next data section end signal ED is given. The counter 66 counts the clock signal CK from the time when the peak value appears in the data section T to the time when the signal ED indicating the end of the data section T is given. This count value is latched by the latch circuit 67, and indicates the peak position PP.

Data indicating the peak position detected in this way
The PP is then provided to a peak position determination circuit 26B. The determination circuit 26B determines whether or not the detected peak position is within the set W section. As mentioned above,
In both the demodulation processing of received data and the carrier detection processing, it is necessary that a correlation peak exists in the W section, otherwise, correct demodulation processing and carrier detection processing cannot be performed.

The comparators 68 and 69 and the AND circuit 7
There is provided a window type digital comparison circuit composed of "0" and "0". Data indicating the start position of the W section is set in one comparator 68, and data indicating the stop (end) position of the W section is set in the other comparator 69. The data indicating the peak position PP is Only when it is between the start and stop positions of
The D circuit 70 outputs an H level peak position determination signal PH.

Next, the configuration and operation of the synchronization establishment circuit including the synchronization establishment determination circuit 28 will be described with reference to FIG.

Two registers 72 and 73 are provided. Register 72
Is provided with data representing the peak position PP, and data representing (3/2) T-PP is set in this register 72.
T is data representing the length (time) of the data section.
On the other hand, data T is set in the register 73. The selector 74 selects one of the setting data of these registers 72 and 73 according to the state of the peak position determination signal PH and supplies it to one input of the digital comparator 75.

On the other hand, the counter 71 counts the clock signal CK and supplies its count output to the other input of the digital comparator 75. The comparator 75 generates a data section end signal (coincidence signal) ED when the count value of the counter 71 becomes equal to the setting data provided through the selector 74. The counter 71 outputs this signal
It is reset by ED and starts counting from zero again.

Now, when the power is turned on, the correlation output and the data section are not synchronized, so that there is a case where no correlation peak exists in the W portion. At this time, the peak position determination signal PH is L
At this time, the selector 74 selects the setting data of the register 72 and supplies it to the comparator 75. This setting data (3/2) TP
P is the next data section end signal E such that the length (time) from the next peak to the next data section end signal is T / 2.
It is for generating D. In this manner, when the peak position is located within the W portion, the peak position determination signal PH becomes H level, and the selector 74 selects the setting data T of the register 73. It will occur at period T.

Synchronization is said to have been established when the state where the peak position exists in the W section of the data section continues for a predetermined plurality of times X. The counter 82 is clock enabled by the H-level peak position determination signal PH input via the AND gate 81, and counts the input data section end signal ED. This counter 82 performs an OR operation with the NOT circuit 84 when the signal PH is at the L level.
The signal is reset by the L level signal via the circuit 85. The count output of the counter 82 is provided to a digital comparator 83. On the other hand, a predetermined number X at which synchronization is determined to be established is set in the comparator 83. When the count value of the counter 82 reaches this X, a coincidence signal is generated from the comparator 83, the flip prop 19 is set and the synchronization establishment signal
DSR (L level) is output. The match signal of comparator 83 is O
The counter 82 is reset via the R circuit 85. Since the AND gate 81 is closed by the synchronization establishment signal DSR, the peak position determination signal PH is no longer input.

If the peak position determination signal PH becomes L level even once even while the counter 82 is counting the signal ED, the counter 82 is reset. Therefore, when the signal PH is H level, X signals ED are output. It is determined that synchronization has been established only when input is performed continuously. If the signal PH goes low before it is determined that synchronization has been established, the selector 74 selects the register 72 as described above and again outputs the data section end signal.
The ED generation timing is adjusted.

The out-of-synchronization determination circuit 29 determines out-of-synchronization when the carrier detection signal PAS is not continuously output over a plurality of (Y times) data sections.

Referring to FIG. 13, once synchronization is established, NAND gate 91 is opened by synchronization establishment signal DSR of L level.
If a carrier is detected, the carrier detection signal PAS becomes H
Level. When the carrier is no longer detected, the carrier detection signal PAS goes to L level, passes through the NAND gate 91, and provides an H level enable signal to the clock enable terminal CE of the counter 92. The counter 92 receives the NAND gate 91 and the NOT circuit 94 by the H level carrier detection signal PAS.
And have already been reset via OR95. Counter 92
Is the data section end signal that is input when enabled
The ED is counted, and the counted value is supplied to the digital comparator 93. In the comparator 93, data representing a predetermined number Y is set in advance. Therefore, when the count value of the counter 92 reaches Y, a match signal is generated from the comparator 93, the flip-flop 19 is reset, and the synchronization establishment signal DSR becomes H level. This H-level signal DSR causes the NAND gate 9
1 is closed. Also, O is determined by the output signal of the comparator 93.
The counter 92 is reset via the R circuit 95.

When the carrier detection signal PAS goes high while the counter 92 is performing a counting operation, the counter 92 is reset. That is, it is determined that the synchronization has been lost only when the state in which the carrier is not detected continues for Y data sections.

This makes it possible to clearly distinguish between temporary carrier non-detection due to a change in transmission characteristics of a transmission path or the like and carrier non-detection (correct synchronization loss) due to communication termination.

[Effects of the Invention] According to the present invention, in a transmitting apparatus, first and second PN code sequences having the same code length different from each other are generated at fixed periods, and the transmission data is reduced to 0 and 1 every fixed period. Correspondingly, the first and second PN code sequences are selected, and the selected PN code sequence is transmitted as a transmission signal, and the receiving device that has received the transmission signal uses the reception signal on the transmission side. The first and second correlation outputs are obtained by performing the correlation operation using the same first and second PN code sequences as described above, and the data section having the same width as the fixed period includes a time point at which a correlation peak is expected to appear. A first product obtained by dividing a main observation section into other sub-observation sections and multiplying a peak value in the main observation section of the first correlation output by a sum of the second correlation outputs in the sub-observation section. And the main observation section of the second correlation output The second product obtained by multiplying the peak value of the first correlation output and the sum of the first correlation output in the sub-observation section is obtained, and these products are compared with each other in magnitude. The first product is larger than the second product. In this case, data 0 is used as demodulated data, and when the value of the second product is larger than the first product, data 1 is used as demodulated data. As a feature of the CSK communication device that can compare the correlation outputs and assign 0 or 1 of the received data according to the magnitude, the code sequence on the receiving side does not need to be strictly synchronized with that on the transmitting side. Since demodulation errors do not occur and the absolute value of the correlation output is taken, there is an advantage that no error occurs even if a transmission line having deteriorated characteristics such as a negative transmission peak value is present. ,
Instead of simply comparing the peak values of the second two correlation outputs, the comparison is made using the product of the peak value of one main observation section and the sum of the other sub observation section,
Since the level of the correlation output having the correlation peak before and after the correlation peak is lower than the correlation level of the correlation output having no correlation peak, the correlation output can be compared in a direction in which the demodulation error is further suppressed. Even if the simple comparison between the peak value of the correlation output and the peak value of the second correlation output includes noise that causes an error, or even if the transmission characteristics are poor, an error occurs. And excellent effects such as stable demodulation can be achieved.

Further, according to the present invention, the receiving apparatus determines the main observation section at substantially the center of the data section and sets the sections on both sides of the center section as sub-observation sections. By shifting the appearance position to the main observation section near the center of the data section, the demodulation accuracy of the data to be demodulated by comprehensively comparing the magnitude of the correlation output in both the main observation section and the sub-observation sections on both sides is stabilized. It has the effect that it can be secured.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the overall configuration of one embodiment of the CSK communication device of the present invention. FIG. 2 is a circuit diagram showing a configuration example of the modulation device shown in FIG. 1, and FIG. 3 is a time chart showing the operation thereof. FIG. 4 is a circuit diagram showing another example of the modulation device shown in FIG. FIG. 5 is a circuit diagram showing a configuration example of a pair of correlators shown in FIG. 1, FIG. 6 is a circuit diagram showing a modified example thereof, and FIG. FIG. FIG. 8 is a circuit diagram showing a configuration example of the demodulation device shown in FIG. 1, and FIG. 9 is a waveform diagram showing the operation thereof. FIG. 10 is a circuit diagram showing a configuration example of the synchronization control circuit shown in FIG. FIG. 11 is a waveform diagram showing a peak position detecting operation, FIG. 12 is a waveform diagram showing a synchronization establishment determining operation, and FIG. 13 is a waveform diagram showing a loss of synchronization determining operation. FIG. 14 is a circuit diagram showing an example of a conventional SS communication device, and FIG.
The figure is a time chart showing the operation. 53 Window generating circuits 54a, 54b Maximum value holding circuits 55a, 55b Adding circuits 56a, 56b Multiplying circuits 51 Comparator 58 Latch circuits

──────────────────────────────────────────────────続 き Continued on the front page Examiner Hiroshi Ebata (58) Field surveyed (Int. Cl. ⁶ , DB name) H04J 13/00-13/06

Claims (2)

(57) [Claims] A first and a second code having the same code length different from each other.
PN code sequences are generated at fixed intervals, and the first PN code sequence is selected for 0 of transmission data and the second PN code sequence is set for 1 of transmission data at each fixed period.
A transmitting device that selects a PN code sequence and transmits the selected PN code sequence as a transmission signal, and receives the transmission signal,
For the received signal, the same first and second
PN code sequence to calculate the correlation between the first and second
Of each of the correlation outputs, the data section having the same width as the fixed period is separately observed in a main observation section including a time point at which a correlation peak appears and a sub-observation section other than the main observation section. The first product obtained by multiplying the peak value of the output in the main observation section by the sum of the second correlation output in the sub observation section and the peak value of the second correlation output in the main observation section and the first value A second product obtained by multiplying the sum of the correlation outputs of the sub-observation sections by the sum is obtained, and these first and second products are compared in magnitude with each other. A CSK communication apparatus comprising: a receiving apparatus that uses data 0 as demodulated data if the value is larger than the first product and demodulated data 1 if the second product is larger than the first product. 2. The reception apparatus according to claim 1, wherein the main observation section is defined at a substantially central portion of the data section, and sections on both sides of the central section are defined as the sub-observation sections.
The CSK communication device as described.