JPS5936425B2 - Lead frame structure with intermediate layer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to lead frames for semiconductor devices such as IC transistors and diodes, and in particular provides a Ni plating layer and an alloy plating layer prior to providing an Ag plating layer on a Cu base metal substrate. This is intended to improve the solderability of lead frames, especially when the thickness of the Ag plating layer is thin.

When manufacturing packages for semiconductor devices such as ICs,
Elements of semiconductor devices such as Si (hereinafter simply referred to as "semiconductor elements")
(also referred to as an "element") and a lead frame forming an external terminal are often connected (wire bonding) with a thin wire made of Au, Al, or the like.

Conventionally, materials with thermal expansion characteristics similar to glass, such as Kovar (Fe-Ni-Co alloy) and 42 alloy (Fe-Ni alloy), have been used for this lead frame due to the need for sealing with glass and ceramic. It's here. However, in recent years, as inexpensive plastic materials have begun to be used as package materials, it is no longer necessary to limit lead frame materials to expensive Kovar and 4゛2 alloys. and,
A lead frame with Au or Ag plating, especially inexpensive Ag plating, is used on a board made of inexpensive and thermally conductive Cu or Cu alloy (phosphor bronze, Cu-Sn alloy, Cu-Fe alloy, etc.). It is being In this case, attempts have also been made to make the Ag plating layer thinner in order to further improve economic efficiency. However, one of the basic characteristics required for a lead frame is solderability for connecting the lead frame and printed circuit board, and as mentioned above, the Ag plating layer provided on the Cu-based metal substrate must be made thinner. If it is too long, there is a problem that the solderability of the lead frame deteriorates.

According to research conducted by the present inventors, the reason for this is that when the Ag layer becomes thinner, some of the underlying Cu is diffused into the Ag surface, exposed, and oxidized. In particular, for the lead frame, the bonding between the semiconductor element (Si) and the lead frame substrate: Au
This is a particular problem because thermal oxidation is likely to occur due to heating during the manufacturing process of semiconductor device packages, such as bonding of lead wires such as lead wires, or the step of covering the package with plastic or the like after bonding. Also A
When the g-plating layer is made thinner, the remaining pinholes become a problem, and the possibility of Cu exposure increases. When solder is applied to a place where Cu is partially oxidized, Ag dissolves into the solder at a very high rate, so the adhesion of the solder to the Cu-based metal, which actually contributes to soldering strength, is reduced. It gets worse. As a result of further research based on the above findings, the present inventors found that Sn-Ni alloy and Sn-Co alloy have good solderability even after thermal oxidation. By plating with Ni to prevent Cu diffusion, further providing the above alloy layer to improve solderability, and then providing a surface Ag layer on top of that, it is possible to reduce the thickness of the Ag plating layer while using a Cu-based metal substrate. It has been found that even if the lead frame is thinned, the decrease in solderability due to thermal oxidation of the lead frame can be significantly alleviated.

The lead frame of the present invention is based on this knowledge, and includes a Ni layer and a Sn layer on a Cu base metal substrate.
It is characterized in that at least one type of alloy layer selected from Ni alloy and Sn-CO alloy and a surface Ag layer are sequentially provided. Hereinafter, the present invention will be explained in more detail with reference to the drawings. FIG. 1 is a plan view showing the arrangement of a lead frame and a semiconductor element in an example of an IC. On a stem Ic connected to a lead 1a, a semiconductor element 2
The emitter, base, or other input/output terminals A, B, C, D, etc. (only partially shown) on the element 2 are connected by lead Ib (5Au wire 3 (only partially shown). Ru.

1a, 1b, and Ic collectively form a lead frame. 2 and 3 are end views taken along the line and the line □-□ in FIG. 1, respectively, and similarly show the mutual arrangement of the lead frame 1 and the semiconductor element 2 and the connection state by the Au wire 3. It is shown from the side. The present invention relates to the materials of lead frames 1a, Ib, and Ic.

4 and 5 show the laminated structure of the lead frame, for example, as an enlarged view of part 0 in FIG. 3. FIG. 4 shows a conventional example, and FIG. show.
As shown in FIG. 4, the conventional lead frame has an Ag plating layer 5 directly formed on a Cu base metal substrate 4. As shown in FIG. On the other hand, in the example of this invention shown in FIG.
On the base metal substrate 4, first a Ni plating layer 6 and then a Sn plating layer 6 are formed.
-A plating layer T of either Ni alloy or Sn-CO alloy (hereinafter often referred to as an alloy plating layer) T, and further an Ag plating layer 5 are formed. In this invention, the material of the substrate 4 is a conventionally proposed Cu substrate metal, that is, C
U alone, phosphor bronze, Cu-Sn alloy, Cu-Fe alloy, etc. are used.

In addition, the Sn content *1 * amount in the alloy forming the alloy plating layer T is (1) 10 to 73% for Sn-Ni alloy (weight%, same hereinafter) (2) 10 to 8% for Sn-CO alloy
It is 0%.

In the above, if the Sn content is less than the lower limit, solderability will deteriorate, and if it exceeds the upper limit, there is a risk that the plating layer T will melt due to heating in the IC manufacturing process as described above. The lower limit of the Sn content in the preferred alloy is 25%, more preferably 35%. Usually the Ni plating layer 6 is 0.01~
3 μm) The alloy plating layer T has a thickness of 0.5 to 3 μm, and the Ag plating layer 5 has a thickness of 0.5 to 3 μm.

Although the Ni layer 6, alloy layer T, and Ag layer 5 are described above as plating layers, it is clear that any metal film forming means such as vacuum evaporation can be used other than ordinary electrolytic plating, and this Since such a forming means itself is well known, there is no need to describe it again here.

As described above, according to the present invention, in a lead frame for a semiconductor device, an inexpensive Cu-based metal substrate is used, a Ni layer is provided thereon to prevent diffusion of Cu to the surface, and a novel alloy layer is further formed. By providing the surface Ag layer after the formation, it becomes possible to maintain the necessary solderability even if the thickness of the expensive surface Ag layer is reduced.

Therefore, a lead frame with good solderability can be provided economically. The present invention will be explained in more detail below with reference to Examples. Example: A Cu substrate with a thickness of 0.254 m and a Cu substrate with a thickness of 0.254 m.
Three types of test specimens were provided with a 5 μm Ni plating layer and a 0.2 μm thick alloy plating layer of the materials shown in the table below, and each was provided with a surface Ag plating layer having the thickness shown in the table below.

Each of these test pieces was immersed in a rosin flux for 5 seconds, and then molten solder of Sn6O%-Pb4O% (2
(30° C.) for 10 seconds, and the degree of solder adhesion of each test piece was observed using a microscope. If you look at the table above, conventional Cu
In a lead frame in which Ag plating is directly applied to the substrate, the degree of solder adhesion decreases significantly as the Ag plating thickness decreases, whereas when using the alloy intermediate layer of the present invention, the degree of solder adhesion decreases even if the Ag plating thickness decreases. It can be seen that the decrease in is extremely small.

[Brief Description of the Drawings] Figure 1 is a plan view showing an example of the arrangement of a lead frame and a semiconductor element, and Figures 2 and 3 are plane views taken along line 1 and line I in Figure 1, respectively. The end view, FIG. 4, and FIG. 5 are enlarged cross-sectional views showing the laminated structure of lead frame materials for a conventional example and an example of the present invention, respectively. 1...Lead frame (1a, Ib...
・Lead, 1c... stem), 2...
Semiconductor element, 3... Connection, 4... Substrate layer, 5... Ag layer, 6... Ni layer, 7
...Alloy layer.

Claims (1)

[Claims] 1 On a Cu substrate metal plate, (1) Ni layer and (2) Sn
- A lead frame for a semiconductor device, comprising at least one alloy layer selected from a Ni alloy and a Sn-Co alloy, and (3) a surface Ag layer.