[go: up one dir, main page]

JPS5934626A - Method for formation of semiconductor film - Google Patents

Method for formation of semiconductor film

Info

Publication number
JPS5934626A
JPS5934626A JP57143995A JP14399582A JPS5934626A JP S5934626 A JPS5934626 A JP S5934626A JP 57143995 A JP57143995 A JP 57143995A JP 14399582 A JP14399582 A JP 14399582A JP S5934626 A JPS5934626 A JP S5934626A
Authority
JP
Japan
Prior art keywords
layer
film
single crystal
electron beam
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57143995A
Other languages
Japanese (ja)
Other versions
JPH0368532B2 (en
Inventor
Kenji Shibata
健二 柴田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Institute of Advanced Industrial Science and Technology AIST
Original Assignee
Agency of Industrial Science and Technology
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agency of Industrial Science and Technology filed Critical Agency of Industrial Science and Technology
Priority to JP57143995A priority Critical patent/JPS5934626A/en
Publication of JPS5934626A publication Critical patent/JPS5934626A/en
Publication of JPH0368532B2 publication Critical patent/JPH0368532B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/02433—Crystal orientation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02546—Arsenides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02549—Antimonides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02595—Microstructure polycrystalline
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02689—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth using particle beams
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H01L21/02691—Scanning of a beam

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a single crystal or coarse crystal grain polycrystalline semiconductor layer of good quality with which a laminated integrated circuit device can be formed by a method wherein a long groove is provided by selectively performing an etching in such a manner that a thick film formed on a semiconductor layer is left in striped form, and electron beams scan along said groove. CONSTITUTION:An SiO2 layer 102 is formed on a single crystal silicon substrate 101 in P type plane direction, a polycrystalline silicon layer 103 of approximately 6,000Angstrom , for example, is coated on the surface of the layer 102, and then an SiO2 film 104 is formed thereon. Then, a part of said SiO2 film 104 is removed in strip form by performing a well-known method of etching. Subsequently, the silicon layer 103 is recrystallized and annealed by irradiation of electron beam 10 on said strip from above in parallel-scanning manner. Besides, No. 11 appearing in the diagram shows the scanning direction of the electron beam. After the SiO2 film 104 has been removed, the part of crystal grain boundary is formed into the element as an element isolated insulating film 106 in each coarse grain using the well-known technique. A gate electrode 108 consisting of polycrystalline silicon, for example, is formed on the element region through the intermediary of a gate oxide film 107. source and drain regions 109 and 110 are formed, and an MOS transistor is obtained.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明は、半導体膜形成方法に係り、ｌＰ♀に粗大結晶
粒多結晶あるいは単結晶半導体膜を形成する方法に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a method for forming a semiconductor film, and more particularly, to a method for forming a coarse-grained polycrystalline or single-crystalline semiconductor film in lP♀.

〔従来技術とその問題点〕[Prior art and its problems]

周知の如く、半導体基板（以下代表的にシリコン基板を
用いる）上に素子を形成する半導体装置においては、酸
化、拡散、イオン注入、写真蝕刻など公知の技術を用い
て、シリコン基板上に平面大粒の多結晶廿たは単結晶半
導体層（以下代表的にシリコン層を用いる）を形成する
方法が提案されている。例えば、シリコン基板をＳｉＯ
２またはＳｉＮ等の絶縁力・、１でおおってその上に多
結晶シリコン層を被着し、これを連続ビームのレーザー
光まだは電子線により照射アニールすることにより単結
晶シリコン層となし、該層中に素子を形成することによ
り、接層半導体装置を製造しようというものである。し
かし従来の方法では、直径で２０μＨ１程度の粗大粒多
結晶シリコンにしがならず単結晶シリコン層をイ４する
ことはきわめてむずがしい。また実現した単結晶中には
多数の転位、双晶、積層欠陥等が含剪れ、シリコン層の
結晶性はきわめて悪いものであった。まだそのシリコン
層の表面−ば、かなり大きな凹凸ができ、そのため核層
中に素子を作る際にはリソグラフィー上多くの難点゛が
ビーム４を照射して、上記開孔部において下地単結晶シ
リコン基板との接触部を種結晶としてエピタキシャル成
長させ、引き続き横方向へ結晶成長させるというもので
ある。この方法の特徴は基板と同一面方位の単結晶領域
を希望する場所に作り得る点にあり、この技術をくりか
えしてゆけば三次元半縛体装置は可能であると考えられ
る。As is well known, in semiconductor devices in which elements are formed on a semiconductor substrate (hereinafter a silicon substrate is typically used), large planar grains are formed on a silicon substrate using known techniques such as oxidation, diffusion, ion implantation, and photolithography. A method of forming a polycrystalline semiconductor layer or a single crystalline semiconductor layer (hereinafter, a silicon layer is typically used) has been proposed. For example, a silicon substrate is made of SiO
A polycrystalline silicon layer is deposited on top of the polycrystalline silicon layer covered with an insulating material such as 2 or SiN, and then irradiated and annealed with a continuous beam of laser light or an electron beam to form a single crystal silicon layer. The idea is to manufacture a contact layer semiconductor device by forming elements in the layers. However, with the conventional method, it is extremely difficult to cut a single crystal silicon layer without forming coarse grained polycrystalline silicon with a diameter of about 20 μH1. Furthermore, the single crystal that was realized contained many dislocations, twins, stacking faults, etc., and the crystallinity of the silicon layer was extremely poor. The surface of the silicon layer still has quite large irregularities, which causes many difficulties in lithography when forming devices in the core layer. This method uses the contact area as a seed crystal to grow epitaxially, and subsequently grows the crystal in the lateral direction. The feature of this method is that it is possible to create a single crystal region with the same plane orientation as the substrate in a desired location, and it is thought that if this technique is repeated, it will be possible to create a three-dimensional semi-bound device.

しかし、現実には横方向に単結晶化できる長さくなり、
先に浴融、１与結晶し、第１！！ｌＪで示すようにレト
ｊ孔恥からはなかなかエビタ片シャルしにくい０開孔部
が溶融シフ、シかも絶縁膜２上のシリコン層３が蒸発せ
ずに横方向エビ成長するビームアニーげている要因は多
い。However, in reality, the length is long enough to form a single crystal in the lateral direction.
First, melt the bath, give one crystal, and the first! ! As shown by lJ, the opening part, which is difficult to remove from the hole, melts and shifts, and the silicon layer 3 on the insulating film 2 does not evaporate and grows laterally due to beam annealing. There are many factors.

〔多６１男の目的〕 本発明はこのような点に鑑みてな−４ｈ、たもので積層
集積回路装置を実現５をぜうる良質の単結晶又は粗大結
晶粒多結晶化７９体層を得ることを１．′ｌ的とする。[Purpose of the 61st Man] In view of the above points, the present invention realizes a multilayer integrated circuit device using a multilayer integrated circuit device. 1. 'l-like.

〔発明の概要〕[Summary of the invention]

本発明では、形成１−１．た半導体層上にれ〜ｊ侯を形
成１２、こ伯、をストライプ状に残イｊσゼるように選
択エツチング（−て長溝を設け、このｉＮＡに沿っで電
子ビームを走査（７、前記半導体層を単結晶も（７くは
粗大結晶粒多結晶化［７ている。In the present invention, formation 1-1. Form a long groove on the semiconductor layer 12, selectively etching it so that it remains in a stripe shape, and scan the electron beam along this iNA (7, etching the semiconductor layer). The layer can also be a single crystal layer (or coarse grained polycrystalline layer).

〔発明の効シ（１〕 本発明により絶ｈ５ル八土の＞ｐめられた所に良質の半
導体層を形成１．で、素子の積層化を実用上十分な特性
をもたせて実Ｄ；、することを可能とすること型（７ｆ
ｌｏ　）面方位の単結晶シリコンｌｋ板１０１の上に約
２μｍの５ＩＯＪＧ’ｊ　１０２を形成する。この除ン
リコンｆｉ−１０１には図示しな“が既に所望″）素子
が１１．４知Ｐ劇程を経て形成されている。次に第２図
（ｂ）に示すようにＳｉｎ、層１０２の表面にたとえば
約６００ＯＡの多結晶シリコン層１０３を被着する。そ
の上に０、５〜１．Ｏｔｔｍの”１０２ＦＪ　１０４を
形成する。次に第２図（ｃｌに示すようＫ、周知の方法
にてＳ　ｉ０２膜１０４の一部をストライプ状にエツチ
ング除去する。その後第２図（ｄ）に示すように電子ビ
ーム１０を上部から。[Effects of the Invention (1)] According to the present invention, a high-quality semiconductor layer is formed in a place with an absolute value of 1. In 1., it is possible to realize the stacking of elements with practically sufficient characteristics. , type (7f
5IOJG'j 102 having a thickness of about 2 μm is formed on a single crystal silicon lk plate 101 with a lo ) plane orientation. In this removed recon fi-101, a "desired" element (not shown) is formed through 11.4 steps. Next, as shown in FIG. 2(b), a polycrystalline silicon layer 103 of approximately 600 OA, for example, is deposited on the surface of the Sin layer 102. 0, 5-1 on top of that. Next, as shown in FIG. 2 (cl), a part of the Si02 film 104 is etched away in a stripe shape using a well-known method. Thereafter, as shown in FIG. electron beam 10 from above.

上記ストライプに平行に走査しながら照射して上記シリ
コン層１０３をアニールに再結晶化する。尚、１１はビ
ーム走査方向である。The silicon layer 103 is annealed and recrystallized by irradiation while scanning parallel to the stripes. Note that 11 is the beam scanning direction.

本発明の最大の特徴は、第２図（ｃｌに示す試料構造、
第２図（ｄｌで示す、１１１子ビームの特徴を充分に生
かしたアニール法にある。即ち、電子ビームのエネルギ
ーデポジションは電子の物質に対する透過能によっての
み決まっており、第２図（ｃｌの構造の試料では８１０
２　ｊＱがストライプ状に開孔［７ている部分１０５で
はシリコン層１０３に大部分の電子ビームエネルギーが
デポジットされるが、それ以外の５ｉｎ２膜１０４でお
おわれている部分ではエネルギー吸収が８ｉ０２腹中で
も起こるため、シリコン層におに！Ｉ）温度分布は第３
図に示すごとく、開孔部１０５で高く、それ以外でそれ
より低くなる。このよう最後に同化が起こる。従ってア
ニール後の再結晶化時の固液界面は第４図に示すごとく
になる。図に於いて、曲線の左側は同相、右側は液相で
あり、同相・液相界面付近には結晶粒界の発生が示され
ている。The greatest feature of the present invention is the sample structure shown in FIG.
This is an annealing method that takes full advantage of the characteristics of the 111 electron beam, shown in Figure 2 (dl).In other words, the energy deposition of the electron beam is determined only by the ability of the electron to penetrate the material, and as shown in Figure 2 (cl). 810 for structural samples
Most of the electron beam energy is deposited in the silicon layer 103 in the part 105 where 2 jQ is opened in a striped pattern [7], but in the other part covered with the 5in2 film 104, energy absorption also occurs in the 8i02 abdomen. Because of this, the silicon layer is covered! I) Temperature distribution is the third
As shown in the figure, it is high at the opening 105 and lower at other locations. Finally, assimilation occurs. Therefore, the solid-liquid interface during recrystallization after annealing becomes as shown in FIG. In the figure, the left side of the curve is the same phase, and the right side is the liquid phase, and the occurrence of grain boundaries is shown near the same phase/liquid phase interface.

ところで、通常溶融再結晶を自然現象に甘かせて行なう
と多くの核生成が行なわれ多数の結晶粒界が見られるが
、この結晶粒界は固液界面に直交するように連続して結
晶粒成長が起こる。そのため、第４図で示すように８ｉ
０２が開口し、ていた部分３０１では結晶粒界がますま
す集中して多数の結晶粒ができるが、　Ｓｉｎ、でおお
われていた部分では粒界がだんだん分散してゆき、やが
て単結晶ができるようになる。このようにして第２図（
ｃｌ工程で形成したストライプ状開口部の周期に合′ｉ
２せた鳴のストライプ状の非常に大きな結晶粒が成長す
る。By the way, when melt recrystallization is carried out without relying on natural phenomena, a lot of nucleation occurs and many grain boundaries are seen, but these grain boundaries are continuous crystal grains perpendicular to the solid-liquid interface. Growth occurs. Therefore, as shown in Figure 4, 8i
In the part 301 where 02 was opened, the grain boundaries became more and more concentrated and a large number of crystal grains were formed, but in the part covered with Sin, the grain boundaries gradually became dispersed, and eventually a single crystal was formed. become. In this way, Figure 2 (
It matches the period of the striped openings formed in the cl process.
Very large crystal grains in the form of two stripes grow.

このようにして電子ビームアニールによりクリ成してゆ
く。素子領域えはゲート酸化膜１０７を介による電極１
１２〜１１４を形成し、て二層に積層した半導体装置を
完成する。In this way, electron beam annealing is performed to clear the structure. In the element region, the electrode 1 is formed through the gate oxide film 107.
12 to 114 are formed to complete a two-layer stacked semiconductor device.

なお、上記実施例では電子ビームによりシリコン層のア
ニールを行なったが、アニール条件としては加速圧５〜
３０１＜Ｖで特に１０ＫＶ以下がよくビーム電流は１〜
ｌＯｍＡがよいが１０Ｋｖでは４ｍＡが最適であった。In the above example, the silicon layer was annealed with an electron beam, but the annealing conditions were an acceleration pressure of 5 to 5.
301<V, especially 10KV or less is good, and the beam current is 1~
1OmA is good, but 4mA was optimal at 10Kv.

真空度はｉ　ｏ’〜１０−”Ｔｏｒｒで基板温度は４０
０〜５００℃、シリコン基板を静′ｒＬ的にチャッキン
グしてアニールが行なわれた。このような条件での浴接
幅は約５０μｍであったため、第２図（ｃｊに示すスト
ライプ状溝のピッチの２倍のｆｉｌＤを５０μｍとした
。またビームをＸ方向（ストライプと平行方向）に走査
する時の辿ｍ”は１００ｃｒｒＶｋＣ。The degree of vacuum is IO' ~ 10-'' Torr and the substrate temperature is 40
Annealing was performed by statically chucking the silicon substrate at 0 to 500°C. Since the bath contact width under these conditions was approximately 50 μm, filD, which is twice the pitch of the striped grooves shown in Figure 2 (cj), was set to 50 μm. The trace m" during scanning is 100crrVkC.

Ｘ方向（ストライプと直交方向）のステ、ツブ送り距離
Ｐは２５μｍすなわちＰ　＝　１’）／’、２とした。The feed distance P in the X direction (direction perpendicular to the stripes) was 25 μm, that is, P = 1')/', 2.

本発明においては距離りまたはＰの決め方も重曹で、Ｄ
Ｃ−ＭＯＳ）ランジスタウバイポーラトランジスれらの
素子を積層配列することにより、従来より高集積、高速
、多機能なｆ＋を層半導体装置を実現することが可能と
なった。In the present invention, the distance or P is determined using baking soda.
(C-MOS) Langstau Bipolar Transistor By arranging these elements in a stacked manner, it has become possible to realize an f+ layer semiconductor device that is more highly integrated, faster, and has more functions than before.

本発明による効果を用いれば、シリコン以外の半導体た
とえばゲルマニウム＋　ＧａＡｓ　、　ＧａＰ　Ｊ　ｈ
るいはｌｎＰ　、　Ｉｎ５ｔ）などの種々の半導体にお
いても充分な効果が期待できる。By using the effects of the present invention, semiconductors other than silicon, such as germanium + GaAs, GaP J h
Sufficient effects can also be expected in various semiconductors such as InP, In5t, and the like.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図はエネルギービーム照射によるＬＥ８Ｂ構造の単
結晶膜の形成過程を説明する断面図、第２図（ａ）〜（
ｆ）はこの発明による半纏体膜を用いて行なった二ｊｄ
ＭＯ８ＬｓＩ製造工程を示す工程断面図、第３図は本発
明による電子ビームアニール時の試料の温度分布を示す
特性図、第４図は半導体膜のアニールによって溶融径再
結晶する時の固液界面を示す図である。 １・・・半導体基板、　　２・・・絶縁膜、３・・・半
導体層、　　　４・・・エネルギービーム、１０１・・
・単結晶シリコン基板、　１０２・・・８４０２膜、１
０３・　多結晶シリコン層、　　１０４　・・Ｓ　ｒ　
０２膜、１０３′・・・再結晶化したシリコン層、１０
５・・・開口部、　　　１０７・・・ゲート酸化膜、１
０６・・・絶縁膜、　　　１０８・・・ゲート電極、１
０９．１１０・・・ソース、ドレイン領域、１１１・・
・絶縁族％　　　１１２〜１１４・・・ＡＩ電極。 出願人　工業技術院長　石　坂　誠　−第１図 （仄２ （Ｃ〕 第２図 第２図 ｉ 第２図Figure 1 is a cross-sectional view explaining the formation process of a single crystal film with an LE8B structure by energy beam irradiation, and Figures 2 (a) to (
f) was carried out using the semi-enveloped membrane according to the present invention.
FIG. 3 is a process cross-sectional view showing the MO8LsI manufacturing process, FIG. 3 is a characteristic diagram showing the temperature distribution of a sample during electron beam annealing according to the present invention, and FIG. 4 is a solid-liquid interface when the semiconductor film is annealed to recrystallize the melt diameter. FIG. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2... Insulating film, 3... Semiconductor layer, 4... Energy beam, 101...
・Single crystal silicon substrate, 102...8402 film, 1
03. Polycrystalline silicon layer, 104...S r
02 film, 103'... recrystallized silicon layer, 10
5... Opening portion, 107... Gate oxide film, 1
06... Insulating film, 108... Gate electrode, 1
09.110...source, drain region, 111...
- Insulating group% 112-114...AI electrode. Applicant Makoto Ishizaka, Director General of the Agency of Industrial Science and Technology - Figure 1 (2 (C)) Figure 2 Figure 2 i Figure 2

Claims (1)

【特許請求の範囲】[Claims] 基体上に多結晶もしくは非晶質の半導体層を被着する工
程と、前記半導体層上に薄膜を形成しさらにこの薄膜を
ストライプ状に残存させるように選択エツチングして長
溝を設ける工程と、前記長溝に沿って電子ビームを走査
し前記半導体層を単結晶もしくは粗大結晶粒多結晶化さ
せる工程とから成る半導体膜形成方法。a step of depositing a polycrystalline or amorphous semiconductor layer on a substrate; a step of forming a thin film on the semiconductor layer and selectively etching the thin film so as to remain in a stripe shape to form long grooves; A method for forming a semiconductor film comprising the step of scanning an electron beam along a long groove to convert the semiconductor layer into a single crystal or coarse grain polycrystal.
JP57143995A 1982-08-21 1982-08-21 Method for formation of semiconductor film Granted JPS5934626A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57143995A JPS5934626A (en) 1982-08-21 1982-08-21 Method for formation of semiconductor film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57143995A JPS5934626A (en) 1982-08-21 1982-08-21 Method for formation of semiconductor film

Publications (2)

Publication Number Publication Date
JPS5934626A true JPS5934626A (en) 1984-02-25
JPH0368532B2 JPH0368532B2 (en) 1991-10-28

Family

ID=15351858

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57143995A Granted JPS5934626A (en) 1982-08-21 1982-08-21 Method for formation of semiconductor film

Country Status (1)

Country Link
JP (1) JPS5934626A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141506A2 (en) * 1983-09-12 1985-05-15 AT&T Corp. Method for producing a semiconductor structure
JPS63300510A (en) * 1987-05-30 1988-12-07 Agency Of Ind Science & Technol Laminated semiconductor device
JP2008136406A (en) * 2006-11-30 2008-06-19 Daiwa Seiko Inc Fishing bag

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0141506A2 (en) * 1983-09-12 1985-05-15 AT&T Corp. Method for producing a semiconductor structure
JPS63300510A (en) * 1987-05-30 1988-12-07 Agency Of Ind Science & Technol Laminated semiconductor device
JP2008136406A (en) * 2006-11-30 2008-06-19 Daiwa Seiko Inc Fishing bag

Also Published As

Publication number Publication date
JPH0368532B2 (en) 1991-10-28

Similar Documents

Publication Publication Date Title
US4448632A (en) Method of fabricating semiconductor devices
JPH0394476A (en) Manufacture of substrate for selective crystal growth and selective crystal growth method and manufacture of solar cell by using these substrates
JPS59155121A (en) Manufacture of semiconductor thin film
JPS5934626A (en) Method for formation of semiconductor film
JPS5918196A (en) Method for manufacturing single crystal thin film
JPS5893220A (en) Preparation of semiconductor single crystal film
JPS60152018A (en) Manufacture of semiconductor thin film crystal layer
JPS621220A (en) Manufacture of defect localized orientation silicon monocrystalline film on insulation support
JPS61131526A (en) Manufacturing method of semiconductor device
JPS5885520A (en) Manufacture of semiconductor device
JPH04206932A (en) Semiconductor device and manufacture thereof
JPS58132919A (en) Manufacture of semiconductor device
JPS6342417B2 (en)
JPS5939791A (en) Production of single crystal
JPH02140916A (en) Manufacturing method of thin film transistor
JPS59134819A (en) Manufacture of semiconductor substrate
JPS6191917A (en) Manufacture of semiconductor thin film crystal
JPS59128292A (en) Method for crystallizing thin film
JPS58180019A (en) Semiconductor base body and its manufacture
JPS5893218A (en) Manufacture of semiconductor thin film structure
JP2771635B2 (en) Ca lower 1-lower x Sr lower x F lower 2
JPS5893224A (en) Preparation of semiconductor single crystal film
JPS5893217A (en) Manufacture of semiconductor crystal film
KR0128522B1 (en) Low temperature poly-silicon film structure and transistor, and making method thereof
JPH0797555B2 (en) Method for manufacturing SOI substrate