JPS59134819A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To form a single crystal Si epitaxially only at an aperture and obtain a substrate of flatness with less crystal defect by single crystallizing also the thin film on a side wall by a method wherein an SiO2 on a single crystal Si substrate is opened, and a polycrystalline or amorphous Si of prescribed conductivity type is formed only on the side wall. CONSTITUTION:A thermal oxide film on the surface {100} of an Si substrate is reactively ion-etched, thus forming a pattern 12 having a vertical wall by leaving an oxide film of approx. 500Angstrom . Poly Si 13 of prescribed conductivity type is deposited by a CVD method and reactively ion-etched, and accordingly the poly Si 13 is left only on the side surface of the oxide film 12. Next, the oxide film 12 is etched with dilluted HF solution, and single crystal Si 15 is selectively grown on the suface 14 of the exposed substrate by a vapor phase epitaxial method. At this time, the poly Si on the wall surface is also single-crystallized into an integral body with the Si 15, thus generating no facets or unnevenness in the neighborhood of an oxide film interface, and therefore a flat epitaxial surface can be obtained. Deciding the wall surface material as amorphous Si is likewise effective.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor substrate in which a silicon epitaxial layer is selectively grown on a single crystal silicon substrate having an insulating film pattern on its surface.

In conventional semiconductor devices, a silicon substrate is made into a desired P-type or N-type conductive layer using ion implantation or impurity diffusion to form active elements, and active elements are separated using PN&- or partial oxidation (LOCO8) method. was used. However, the increase in the stray capacitance of the junction and the dimensional change during the partial oxidation process (
Bird's beak formation) was an obstacle to increasing device speed and areal density.

However, as a technology to compensate for the above drawbacks, we have developed a technology that uses 5O8 (Si on 5apphire) for sapphire substrates.
). Since the substrate is an insulator, stray capacitance is small.
This is advantageous for increasing the speed ratio and density of the element. However, since the silicon epitaxial layer has a lattice constant mismatch with the sapphire substrate, many lattice defects occur at the substrate-silicon interface, causing leakage current, which is a major drawback of SO8.

Furthermore, there are graphite epitaxy technology and bridging epitaxy technology as new single crystallization technologies for silicon films on insulating substrates.

The former is Applied Physics Letters Volume 35,
No. 1, pp. 71-74, 1979 (Applied
Physics' Letters, Vol.35. j
%l.

pp. 71-74, 1979), in which a quartz substrate is processed with grooves, a CVD film of polycrystalline silicon is grown over the entire surface of the substrate, and the film is made into a single crystal by laser irradiation.

The latter is published in Japan Journal of Applied Physics Vol. 19, p. 1, pp. L23-L26, 1980 (
Japan Journal of Applied
Physics.

Vol-19, il, pp, L23-L26, 1
980), according to which an insulating film is partially formed on a semiconductor single crystal substrate, a polycrystalline silicon film is further deposited on the entire surface of the substrate, and the entire substrate is recrystallized as a seed crystal by laser irradiation. The aim is to form a single crystal layer also on an insulating substrate. However, all of these methods have problems such as poor single crystallization and crystal defects on the insulating film, and have not yet reached the point where device characteristics that can withstand practical use have been obtained. Furthermore, it requires various high-precision techniques, lacks mass productivity, and has not yet reached the point where it has become a practical technology.

In contrast to these techniques, there is a selective epitaxial technique. In this method, an insulating film is partially formed on a semiconductor single crystal substrate, and a semiconductor single crystal layer of the same type as the substrate is epitaxially grown only on the exposed substrate area without depositing on the insulating film, and then it is applied to the active area of the device. That is. Since this epitaxial method is homoepitaxial, it does not require crystallinity with extremely good surface quality, and has excellent properties such as being simple and easy to mass-produce.

However, the substrate used in conventional selective epitaxial
Since the insulating film was formed on a single crystal substrate and then partially opened, the interface between the insulating film and the epitaxial film was strongly influenced by the plane orientation of the single crystal substrate used. . For example, if you use a (1001 board), (111)
A 4-fold symmetric facet with a surface is generated. Although the surface is flat, asymmetrical irregularities are formed at the insulating film-epitaxial film interface.

The surface shape of the epitaxial film obtained by the conventional method will be further explained using figures. FIG. 1(a) is a schematic plan view showing the growth shape of epitaxial silicon when using a (100) silicon substrate, and FIG.
FIG. 2 is a schematic cross-sectional view taken along line BB' of FIG. Further, FIGS. 2(a) and 2(b) are a schematic plan view and a sectional view corresponding to FIGS. 1(a) and (b), respectively, in the case where a (111) silicon substrate is used.

For example, a silicon oxide film 2 is deposited on a (100) silicon substrate 1, and an epitaxial film 4 is grown on the exposed silicon region 3 by etching and etching. A four-fold symmetrical facet 5 is formed. This is because various plane orientations are likely to be formed near the interface between the epitaxial film 4 and the silicon oxide film 2, which are discontinuous in material, and as a result, a (111) plane with a slow growth rate was formed. by. On the other hand, when the (111) substrate 11 is used, a flat surface with no facets can be obtained, but since it has three-fold symmetry, the shape near the interface within the rectangle is not symmetrical and has a pyramidal shape. Jagged edges are observed. When forming an epitaxial layer on a substrate with an insulating film in this way, it is strongly influenced by the plane orientation of the substrate.
It has heretofore been impossible to obtain a flat surface over the entire opening of the insulating film. Furthermore, the density of stacking faults tends to be higher near the interface between the epitaxial silicon film and the insulating film, which is a major problem in device fabrication. In the case of transistors formed using the conventional LOCO8 method, the breakdown voltage of the gate insulating film is low due to the unevenness of the surface, and wire breakage is also likely to occur.Furthermore, compared to transistors formed using the conventional LOCO8 method, the distance between the source and drain is several orders of magnitude wider due to the crystal defects. The drawback is that leakage current flows through the insulating film interface. Further, even when a bipolar transistor is formed on such an epitaxial film, there are disadvantages in that the unevenness of the surface makes subsequent patterning of the resist difficult and that the base and emitter regions are not formed uniformly. Moreover, a problem arises in that leakage current is likely to occur at the insulating film-epitaxial film interface between the base and the collector due to crystal defects and the like.

The present invention provides a method for manufacturing a semiconductor substrate, which can obtain an extremely flat surface without depending on the orientation of a single crystal substrate, and can significantly reduce the density of crystal defects existing at the interface between an insulating film and an epitaxial film. It provides:

According to the present invention, an insulating film is formed on a silicon single crystal substrate, and then an opening is provided in a desired portion of the insulating film, and only the side wall traps of the insulating film in the opening are P-type or N-type in the silicon crystal. A thin film of polycrystalline d1 silicon or amorphous silicon doped with impurities, or a thin film of non-doped polycrystalline silicon or amorphous silicon exhibiting the following properties is formed, and then epitaxial growth is selectively performed only in the opening of the insulating film. A method for manufacturing a semiconductor substrate is obtained, characterized in that the thin film of polycrystalline silicon or amorphous silicon is made into a single crystal during growth.

If a polycrystalline silicon thin film or amorphous silicon thin film is formed on the sidewalls of the insulating film pattern formed on the surface of a silicon single crystal substrate in this way and then selective epitaxial growth is performed, the (100) substrate will have extremely few facets. Therefore, a flat surface can be obtained, and in the case of a (111) substrate, jaggedness and dents can be alleviated due to the asymmetry, and a symmetrical surface can be obtained with a flat surface. Also (110) and (5
A similarly flat epitaxial surface can be obtained using other substrates such as 11).

Furthermore, if n-type or n-type impurities are doped into the polycrystalline silicon thin film or amorphous silicon thin film,
It plays the role of a channel stopper when a field effect transistor or hyperpolar transistor is formed in an epitaxial film, and can significantly reduce leakage current that tends to be formed in the silicon film in contact with the sidewall of the insulating film.

Next, the present invention will be explained in detail using figures.

Figure 3 (a), (b), (C), (d)
, (e) is a schematic sectional view for explaining the first embodiment of the present invention, in which the 4R manufacturing process is omitted along the lines 111Lf. After thermally oxidizing at 1000°C and depositing a Si film with a thickness of about 1 μm on a silicon substrate 11 with a (100) plane, a Si film with a thickness of about 500λ is etched by ordinary photolithography and reactive ion etching. 3(a) is obtained by forming a sin insulating film pattern 12 with a vertical wall surface. The Si02 film of about 500 Å is used as an etching mask for the polycrystalline silicon film 13 later. Next, the polycrystalline silicon film 13 is coated with a thickness of approximately 100 mm using the CVD method.
When deposited with a film thickness of OA, the result is as shown in FIG. 3(b), and when the polycrystalline silicon film 13 is subsequently etched anisotropically using a reactive ion etching technique or the like, a film of 8i0. Polycrystalline silicon remains at the initial thickness only on the sidewalls of the film 12, as shown in FIG.
) is obtained. Next, Si
When the film is etched, the silicon substrate surface 14 is exposed, as shown in FIG. 3(d). Next, approximately 1 vol.1% HCI was added to the gas system consisting of SiH, CB, and water.
In addition, selective epitaxial growth at a temperature in the range of 900°C to 1100°C results in a length of 8i0. A Si single crystal film 15 is grown only on the exposed silicon region 14 without being deposited on the surface of the film 12. When the epitaxial silicon film has a thickness of about 1 μm, the pattern shown in FIG. 3 (,) is obtained. 8
io, it was confirmed by TEM observation that the polycrystalline silicon present at the interface between the insulating film and the epitaxial silicon became single crystallized and became a part of the Si epitaxial layer 15. Moreover, no facets or irregularities were observed near the SiH2 interface, and a flat epitaxial surface was obtained. This is considered to be because the polycrystalline silicon film on the wall surface of the insulating film undergoes rearrangement according to the substrate surface orientation during epitaxial growth, and Si* molecules are constantly replenished from the wall surface.

Regarding wall materials, in addition to polycrystalline silicon, amorphous silicon also showed similar effects.

Next, a second embodiment of the present invention will be described. FIG. 4 is a schematic cross-sectional view showing the manufacturing steps in order to manufacture an n-channel insulated gate field effect transistor.

The group used has a specific resistance of about 1Ω・I (100)
It is a silicon single crystal substrate.

The steps up to forming a pattern of a 5in2 film 402 with a thickness of 1 μm and a Sin film 403 with a thickness of about 500λ on the surface of the substrate 401 are the same as in the first embodiment. Next, polycrystalline silicon is deposited to a thickness of about 1000λ using the CVD method.

Boron, which is an n-type impurity, is added to 1 during or after deposition.
Dope to about 0 α (Figure (a)). Next, by the same etching method as in the first embodiment, the polycrystalline silicon 404 is left only on the wall of the Sin film 402, and then the Sin film 403 is removed. Next, as in the first embodiment, SiH,
Approximately 1 HCI is added to a gas composed of C12 and hydrogen.
A silicon single crystal film 405 is epitaxially grown selectively on the exposed portion of the silicon substrate in addition to vo1% (Figure (b)).
. For example, by introducing diborane (B, H,) gas during growth, an epitaxial film having a specific resistance of 10 to 2 ohms can be easily obtained. The flatness and crystallinity of this epitaxial Si film are almost the same as those in the first embodiment, and the polycrystalline silicon is also single crystallized. Poron in the polycrystalline silicon formed on the sidewall is distributed within a range of about 0.1 μm from the insulating film after epitaxial growth. This becomes the channel strike and bar region 4041.

Next, after forming a gate oxide film 406, an impurity 40 is added to the surface of the epitaxial silicon substrate by means such as ion implantation.
7 is controlled and introduced to set the desired transistor threshold voltage (Figure (C)). After that, the polycrystalline silicon is CV
The gate electrode a! is deposited using the D method and patterned. 408
After that, source/drain regions 409 are formed by ion-implanting N-type impurities such as arsenic at a dose of 10"cm-2 or more (Figure (d)), and appropriate annealing is performed to remove ion implantation damage. After recovery, a P8G film 410 is deposited as an insulating film between the eyebrows by the CVD method and planarized by heat treatment.Contact holes 411 are formed using ordinary photolithography to obtain the image shown in FIG. 4(e). .Aluminium 412 is deposited by vacuum evaporation method, wiring electrodes are patterned, and aluminum and silicon are alloyed in hydrogen to obtain the finished image shown in FIG. 4(f).If necessary, CVD method is applied. A protective film is deposited at the electrode pad portion, and the protective film is removed by etching.The electrical characteristics of the insulated gate field effect transistor thus obtained are good, for example, the pn junction leakage current is 1oA when the applied voltage is 5μ.
/m or less, the slope of the source-drain subthread and shoulder characteristics was approximately 90 mV/decade.

All of these values are comparable to the characteristics obtained by the conventional LOCO8 method and are satisfactory. Furthermore, it was possible to relatively easily form an element isolation dimension of 05 μm, which could never be achieved by the LOCO8 method.

Furthermore, since the impurity concentration of the silicon substrate can be selected independently of the threshold voltage of the transistor, soft errors caused by α rays can be improved by using a m6 degree substrate, which has a lower specific resistance than the 1Ω boron resistivity used in the example. be able to do something,
It also has the advantage of achieving a high switching speed ratio.

In this example, polycrystalline silicon was left on the sidewalls of the SiO film, but a similar effect was obtained with amorphous silicon.

Next, a third embodiment will be described. Figure 5 (a), (b)
, (c).

(d), (e), (f), (g) are npn
3 is a schematic cross-sectional view of a bipolar transistor manufacturing process shown in the order of steps. A thermal oxide film 502 is formed on an n-type (100) plane silicon substrate 501, the oxide film is opened by ordinary photolithography, and phosphorus is diffused to form a highly concentrated collector region 503 ((a), Fig. ). After removing the thermal oxide film 502, a Si film 504 is deposited to a thickness of about 2 μm using the CVD method, and similarly patterned using photolithography and reactive ion etching to form an 8i film.
The side wall of the 0° membrane 504 has a nearly vertical shape. Next, polycrystalline silicon doped with poro:/ is deposited to a thickness of about 300 to 1500 Å by CVD, and then etched using reactive ion etching, so that only the side walls of the film 504 are filled with Sin and boron. Polycrystalline silicon 505 doped with is left (see (b)).

Next, add an appropriate amount of Hq/f hydrogen fluoride gas such as hydrogen chloride and phosphine (P) (,) to a gas system using, for example, Sin, C1, as a source gas and H2 as a carrier gas.
When epitaxial growth is performed at 00°C or higher, Sin.

No silicon is deposited on the film 504, and an n-type single crystal silicon film 506 is formed only in the opening of the silicon substrate. Sio, the polycrystalline silicon 505 covering the sidewalls undergoes rearrangement during the summer pitaxial growth, resulting in a monocrystalline layer 50.
6 and becomes a poron diffusion region 505'. In this way, FIG. 5(c) is obtained. A resist pattern is formed using photolithography, boron ions are implanted using the resist 508 as a mask, and then heat treatment is performed to form a base region 509.
5(d) is obtained. Next, a Sin film 510 is deposited by the CVD method, and photolithography and processing are performed.
Create a pattern using the ching method. Thereafter, only the region to be made the base contact is covered with a resist film 511, and ions are implanted into the resist film 511 at a dose of 10 cm or more using a mask to form an emitter region 512 and a collector concentration region 513, as shown in FIG. ). Next, the resist 514 is masked with a mask K L, and the poron is I O”cr
By implanting ions at a dose of n'' or more, a base simple concentration region 515 is obtained, as shown in FIG. 5(f).
A PSG film 516 is deposited as an interlayer insulating film by CVD method,
When a contact hole is opened and an A1 electrode 517 is formed, the result is as shown in FIG. 5(g). In this way, an npn transistor whose base-collector leakage current is comparable to that formed by the conventional LOCO8 method can be obtained.

In the above first to third embodiments, the thickness is 300 to 150.
Although 0A polycrystalline silicon is used, the speed of orientation of silicon atoms during growth is very fast, so there is no particular restriction on the thickness of the polycrystalline silicon film deposited on the side wall of the insulating film. By using the substrate covered by the present invention,
A semiconductor device with good characteristics could be formed.

In this case, it is clear that the insulating film 12 becomes a pre-separation region.

Furthermore, in the above embodiments, the gases used for selective epitaxial growth include SiH, CI, , HCI,
) 12 was used, but the mixture is not limited to this, and includes S 1Hc1 s , HCI ,
Mixed gas of H2, S 1c14, HCI, H2
A mixed gas of 5iHa, HCI, H.

A mixed gas or the like may also be used.

Furthermore, HI, HBr, etc. may be used instead of the above-mentioned HC+, that is, in general, any hydrogen halide may be used.

Further, in the above embodiments, a Sin film was used as the insulating film, but it may also be an 8i3N film, a stacked film of a Sin film and a 5isN4 film, a PSG film (phosphorous glass film), or the like.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1 and 2 are diagrams schematically showing the shapes of epitaxial films using a (100) plane and a (111) mother substrate, respectively, according to a conventional method. Further, FIG. 3 is a schematic cross-sectional view showing the first embodiment of the present invention in the order of steps. FIG. 4 is a schematic sectional view showing the second embodiment of the present invention in the order of steps. FIG. 5 is a schematic sectional view showing the third embodiment of the present invention in the order of steps. The numbers in the figure refer to the following. 1, 401, 501...(100) plane silicon substrate, 11--(111) plane silicon substrate, 2...-insulating film, 3--exposed silicon substrate surface, 4--epitaxial silicon layer, 5 −・・Tapered facet,
6.--Asymmetrical unevenness, 12.502,504,5
10...8i0□ Insulating film, 13... Polycrystalline silicon film, 14... Exposed (100) plane silicon substrate surface, 15... Epitaxial silicon layer, 404,
505--polycrystalline silicon doped with impurities, 40
5, 506...Epitaxial silicon layer, 40
4', 505'--Channel strike, bar area, 406
...Gate oxide film, 407... Channel doped region, 408... Polycrystalline silicon for date electrode, 409...
- Source/drain region, 410, 516... PSGJl'% for interlayer insulating film, 411... Contact hole, 412, 517... Aluminum i4Q, 50
3...Frefter area, 514 508 511...
Resist film, 509...Base region, 512...Emitter region, 513...Collector quotient concentration region, 515
...Base concentration area strength 7 Mouth (α) (b) Fang 2 B) 3 Shi) 4 Figure 410 4// Fang 5 times (α) (Otsu) (9) Procedural amendment (method) % formula % Display of case 1981 Patent Application No. 153766
Issue name: Relationship to the case of a person amending the manufacturing method of semiconductor substrates: Applicant: 5-33-1 Shiba, Minato-ku, Tokyo (423) Representative: Tadahiro Sekimoto, Representative: Tadahiro Sekimoto, 7. 5. Date of amendment order: January 31, 1982 (shipment date) 6. Correct as shown in the drawing to be corrected.叉、2.・

Claims (1)

[Claims] An insulating film is formed on a Si single crystal substrate, and then an opening is provided in a desired portion of the insulating film, and an impurity exhibiting P type or N type in the silicon crystal is added only to the wall of the insulating film in the opening. forming a thin film of polycrystalline silicon or amorphous silicon doped with or doped with polycrystalline silicon or a thin film of undoped polycrystalline silicon or amorphous silicon, and then epitaxially growing a single crystal silicon film selectively only in the opening of the insulating film. . A method for manufacturing a semiconductor substrate, characterized in that the thin film of polycrystalline silicon or amorphous silicon is made into a single crystal during the growth.