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JPS5928327A - Forming method of single crystal semiconductor film - Google Patents

Forming method of single crystal semiconductor film

Info

Publication number
JPS5928327A
JPS5928327A JP57137392A JP13739282A JPS5928327A JP S5928327 A JPS5928327 A JP S5928327A JP 57137392 A JP57137392 A JP 57137392A JP 13739282 A JP13739282 A JP 13739282A JP S5928327 A JPS5928327 A JP S5928327A
Authority
JP
Japan
Prior art keywords
single crystal
film
semiconductor film
substrate
crystal semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP57137392A
Other languages
Japanese (ja)
Other versions
JPS6256651B2 (en
Inventor
Hidefumi Mori
森 英史
Masahiro Ikeda
正宏 池田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NTT Inc
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP57137392A priority Critical patent/JPS5928327A/en
Priority to US06/434,536 priority patent/US4534820A/en
Publication of JPS5928327A publication Critical patent/JPS5928327A/en
Publication of JPS6256651B2 publication Critical patent/JPS6256651B2/ja
Granted legal-status Critical Current

Links

Classifications

    • CCHEMISTRY; METALLURGY
    • C30CRYSTAL GROWTH
    • C30BSINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B11/00Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method
    • C30B11/04Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method adding crystallising materials or reactants forming it in situ to the melt
    • C30B11/08Single-crystal growth by normal freezing or freezing under temperature gradient, e.g. Bridgman-Stockbarger method adding crystallising materials or reactants forming it in situ to the melt every component of the crystal composition being added during the crystallisation
    • C30B11/12Vaporous components, e.g. vapour-liquid-solid-growth

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Photovoltaic Devices (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a single crystal Si film at a low temperature on a glass substrate of low cost by such an arrangement wherein when crystals composed of an alloy of Au and Si are caused to educe on an amorphous substrate, the orientation of crystals is controlled by the repetitive patterns of Au film. CONSTITUTION:On a quartz glass substrate 11, a film of Au 12 which forms eutectic crystal with Si is caused to adhere thereto, a resist film of specific pattern 13 is provided thereon, and spatter etching is processed on exposed parts of the film 12 and a repetitive pattern of polygon 14 having a vertical angle which is a multiple of about 60 deg. is obtained. Here, the pattern 14 shall be a trapezoid having vertical angles of 60 deg. and 120 deg. and the distance between opposing sides shall be approx. 1mum, and pitch shall be approx. 1.2mum. Next, the substrate 11 is heated up to a temperature higher than the eutectic temperature of Si and Au, and Si is caused to adhere by evaporation, and eutectic alloy of Si-Au is caused to generate between patterns 14, and single crystal Si layer 19 is caused to generate of which crystal direction is aligned, by using surplus Si 18 adhered to the pattern 14. At the same time, Au is moved from the alloy 17 and the desired Si-Au thin film 20 is obtained.

Description

【発明の詳細な説明】 本発明は、単結晶半導体膜形成法、特にガラスなどの非
晶質基板上にシリコンなどの半導体材料の単結晶膜を成
長させる方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for forming a single crystal semiconductor film, and particularly to a method for growing a single crystal film of a semiconductor material such as silicon on an amorphous substrate such as glass.

従来、非晶質基板上にシリコン単結晶を成長させる方法
としてはグラフオエピタキシ法が知られている(M、W
、G@Is、D、C,FJanders and H,
I 。
Conventionally, the graphoepitaxy method is known as a method for growing silicon single crystals on an amorphous substrate (M, W
, G@Is, D, C, FJanders and H,
I.

8m1th、AppIIi@d Physics Le
tter第33巻第77頁(197?年))。この方法
では、非晶質絶縁基板上にピッチ3μmで深さ1100
n程度の溝企グレーティング状に刻み、その土に化学気
相堆積(CVD’I法により非晶質シリコンを堆積した
後にレーザアニール法により非晶質シリコンを結晶化さ
せる。ここでS基板上に切刻した溝により結晶化する際
の結晶方位を制御している。
8m1th, AppIIi@d Physics Le
Volume 33, page 77 (197?)). In this method, a depth of 1100 is formed at a pitch of 3 μm on an amorphous insulating substrate.
Amorphous silicon is deposited on the soil by chemical vapor deposition (CVD'I), and then crystallized by laser annealing. The cut grooves control the crystal orientation during crystallization.

しかしながら、かかる方法では、結晶性を向上させるた
めにアニールのレーザ出力を増加させると為上述した溝
の断面形状が熱により矩形がら変点があった。また、結
晶化の際に保設置1u(slo2や513N4)が必要
なので工程上複雑であるという欠点もあった。
However, in this method, when the laser output for annealing is increased in order to improve crystallinity, the cross-sectional shape of the groove described above changes from a rectangular shape due to heat. Furthermore, since 1 u (slo2 or 513N4) of storage is required during crystallization, the process is complicated.

以上の欠点を解決するため% * 、 Japanes
eJournaA’ of AppHed PhAc5
第20巻L9o3〜Lデoz頁(1911年)や特開昭
&? −10,2,2’1号には、第1図に示すように
、Auなどシリコンと低温で共晶反応を起す金属を溝λ
を刻んだ石英基板lの全面上に堆積して金属膜3を形成
した後、この金属膜3上に低温でシリコン単結晶を成長
させる方法が示されている。
In order to solve the above drawbacks,
eJournaA' of Applied PhAc5
Volume 20 L9o3~L de oz page (1911) and Tokkai Sho&? -10, 2, 2'1, as shown in Figure 1, a metal such as Au that causes a eutectic reaction with silicon at low temperatures is used in the groove
A method is shown in which a metal film 3 is formed by depositing on the entire surface of a carved quartz substrate l, and then a silicon single crystal is grown on this metal film 3 at a low temperature.

しかしながら、森らの方法では、<///>が基板に垂
直な方向に配向する性質を持つため、単結晶膜を得るた
めには第1図に示すように、基板l上の溝λを109.
、t°の角度を持つように精密に加工する必要があり、
また溝同士が400で交差するように溝コを形成する必
要がり、このためプロセスが複雑になる欠点があった。
However, in the method of Mori et al., since <///> has the property of being oriented in the direction perpendicular to the substrate, in order to obtain a single crystal film, the groove λ on the substrate l must be 109.
, it is necessary to precisely process it so that it has an angle of t°,
Furthermore, it is necessary to form the grooves so that the grooves intersect with each other at 400 degrees, which has the disadvantage of complicating the process.

また、溝コの加工には、リアクティブスパッタエツチン
グ等が使用されるが、理想的な断面形状をもつ溝を形成
するのは非常に困難であるため、結晶性の向上には限界
があった。
In addition, reactive sputter etching is used to process grooves, but it is extremely difficult to form grooves with an ideal cross-sectional shape, so there is a limit to the improvement of crystallinity. .

そこで、本発明の目的は、結晶性のよい単結晶半導体薄
膜を形成する方法を提供することにある。
Therefore, an object of the present invention is to provide a method for forming a single crystal semiconductor thin film with good crystallinity.

本発明の他の目的は、製造が容易な単結晶半導体薄膜を
形成する方法を提供することにある。
Another object of the present invention is to provide a method for forming a single crystal semiconductor thin film that is easy to manufacture.

本発明の更に他の目的は、低温で製造できる単結晶半導
体薄膜を形成する方法を提供することにあるO かかる目的を達成するために、本発明の第1の形態では
、平面非晶質基板上に結晶成長すべき半導体と共晶また
は化合物となる金属をtooの整数倍の角度の頂角をも
つ多角形の繰返し図形に形成し、その図形成金M’に有
する基板の上に半導体材料を堆積させて単結晶半導体薄
膜を形成する。
Still another object of the present invention is to provide a method for forming a single crystal semiconductor thin film that can be manufactured at low temperatures. A metal that becomes eutectic or a compound with the semiconductor to be crystal-grown is formed into a polygonal repeating figure having an apex angle that is an integral multiple of too, and the semiconductor material is placed on the substrate having the formed gold M'. is deposited to form a single crystal semiconductor thin film.

本発明の第2の形態では、平面非晶質基板上に結晶成長
すべき半導体と共晶または化合物となる金属を600の
整数倍の角度の頂角をもつ多角形の繰返し図形に形成し
、その図形状金属を有する基板の上に半導体材料を堆積
させてj’f=、結晶半導体膜を成長させ、次いで金属
を除去してから、単結晶半導体膜上に新たな単結晶半導
体膜をエピタキシャル成長させる。
In a second embodiment of the present invention, a metal to be eutectic or a compound with a semiconductor to be crystal-grown is formed into a repeating polygonal shape having an apex angle of an integral multiple of 600 on a planar amorphous substrate, A semiconductor material is deposited on the substrate having the shape metal to grow a crystalline semiconductor film, the metal is then removed, and a new single-crystal semiconductor film is epitaxially grown on the single-crystal semiconductor film. let

ここで、半導体としてはシリコンを用いることができる
。繰返し図形としては、例えば正三角形あるいは40 
と/Jの頂角を有する平行四辺形とすることができる。
Here, silicon can be used as the semiconductor. As a repeating figure, for example, an equilateral triangle or 40
It can be a parallelogram with apex angles of and /J.

本発明の好IJ例では、半導体材料の堆積を半導体と金
属との共晶温度以下で行う。
In preferred IJ embodiments of the present invention, the deposition of the semiconductor material is performed below the eutectic temperature of the semiconductor and metal.

以下に図面を参照して本発明の詳細な説明する。The present invention will be described in detail below with reference to the drawings.

第−A図〜第−F図は本発明方法の順次の工程の一実施
例を示し、第一五図に示すような基板、例えば石英ガラ
ス基板ll上に単結晶を成長させるべき半導体と共晶ま
たは化合物となる金属膜/2、例えば半導・体がシリコ
ンの場合には例えば金膜/2を蒸着法等で厚さ、例えば
1000 Aに形成して第、2B図に示す構造を得る。
Figures -A to -F show an embodiment of the sequential steps of the method of the present invention, in which a single crystal of a semiconductor is to be grown on a substrate as shown in Figure 15, for example a quartz glass substrate. A metal film/2 that becomes a crystal or a compound, for example, a gold film/2 when the semiconductor/body is silicon, is formed to a thickness of, for example, 1000 A using a vapor deposition method to obtain the structure shown in Figure 2B. .

この構造の上に所定形状のレジストパターン13を形成
して第10図に示す構造を得た彼、このしシストパター
ン13をマスクとして金膜lコをスパッタエッチ法等で
エツチングして約60の整数倍の角度を頂角に持つ多角
形の繰返し図形の金属(ここでは金)パターン/lIを
形成して第、21)図の構造を得る。
He formed a resist pattern 13 of a predetermined shape on this structure to obtain the structure shown in FIG. A metal (gold in this case) pattern /lI of a polygonal repeating figure having apex angles that are integral multiples of angles is formed to obtain the structure shown in Fig. 21).

ここでは金パターン/41の形状は、第3図に示す、l
: 5 L 、t=o0と/、2/7°の頂角を有し、
対向する辺の間の距離が1μmのひし形とし、かかるひ
し彫金パターン/&のピッチは1.−μmとした。
Here, the shape of the gold pattern /41 is shown in FIG.
: 5 L, t=o0 and/, has an apex angle of 2/7°,
The distance between opposing sides is 1 μm, and the pitch of the diamond engraving pattern /& is 1. −μm.

ところで1第一2D図の構造を得るためには、第28図
および第、2C図の処理の他に、リフトオフを利用する
方法を用いてもよい。すなわち九基板ll上に、例えば
厚さO,7μmのレジストパターン/3を所定形状に形
成して第41A図の構造を得る。次いで、この構造の上
にレジストパターン/3より薄い厚さに金膜/6を蒸着
法等で堆積して第98図の構造を得る。その後、アセト
ン等によりレジストパターン/&と共にレジストパター
ン/3上の金膜/6をリフトオフ処理により除去して第
2D図のような金パターン/lI−を有する構造を得る
Incidentally, in order to obtain the structure shown in Fig. 1, 2D, a method using lift-off may be used in addition to the processing shown in Figs. 28, 2C, and 2C. That is, a resist pattern /3 having a thickness of O and 7 μm, for example, is formed in a predetermined shape on a nine substrate 11 to obtain the structure shown in FIG. 41A. Next, a gold film /6 is deposited on this structure by vapor deposition or the like to a thickness thinner than the resist pattern /3 to obtain the structure shown in FIG. 98. Thereafter, the gold film /6 on the resist pattern /3 is removed by a lift-off process along with the resist pattern /& using acetone or the like to obtain a structure having a gold pattern /lI- as shown in FIG. 2D.

第コD図示の金パターン構造を得る際のレジストパター
ン/3または/3を形成するにあたっては次のような方
法を用いることができる。まず、石英ガラス基板ll上
にレジスト(たとえばシブレー社し 製AZ /330 J )を塗布し、次にたとえばH,
−Cd′/−ザ等からのレーザ光を重畳干渉させた状態
で上記レジストをグレーティング状に露光する。次に基
板//をto0回転し、同様に重畳干渉させたレーザ光
を照射し、前記グレーティング状の露光に重ねて他のグ
レーティグ状の露光を行う。次に、現像処理を行うと、
重なって露光した部分のレジストがひし形状に除去され
、所定形状のレジストパターン13または13が形成さ
れる。
The following method can be used to form the resist pattern /3 or /3 when obtaining the gold pattern structure shown in FIG. First, a resist (for example, AZ/330 J manufactured by Sibley) is applied onto a quartz glass substrate 11, and then, for example, H,
The resist is exposed in the form of a grating with laser beams from -Cd'/- lasers or the like being superimposed and interfered with. Next, the substrate // is rotated to 0, and the same superimposed and interfered laser beams are irradiated to perform another grating-like exposure superimposed on the grating-like exposure. Next, when developing processing is performed,
The overlapping exposed portions of the resist are removed in a rhombus shape, forming a resist pattern 13 or 13 in a predetermined shape.

次に、第コD図示の金パターンを珊する基板をシリコン
と金との共晶点温度よりも高い温度、たとえば310℃
に加熱した状態で、第2E図のように半導体材料として
シリコンS1を数A/sec 、例えばJ A/s e
 eの蒸着速度でかかる基板//の全表面に蒸着する。
Next, the substrate on which the gold pattern shown in FIG.
As shown in FIG. 2E, silicon S1 as a semiconductor material is heated at several A/sec, for example J A/s e
is deposited on the entire surface of such substrate // at a deposition rate of e.

蒸着されたシリコンは順次に金と反応し、ある濃度で金
膜に溶融して5l−Au共晶合金/γを形成する。蒸着
が進行すると、過剰のシリコンは基板ll上に符号/g
で示すように析出し始める。この析出において、析出シ
リコン/Sの結晶は基板//に対して垂直方向に(//
/ :>に配向し、金、<ターン/lIの形状により基
板//に対して水平方向の結晶方位が揃うので、単結晶
シリコン膜19が基板//上に形成される。金はこの単
結晶シリコン股/9上に移送されてS 1−Au共晶合
金の薄膜〃となり、第、2F図の層構造が得られる。こ
のときの単結晶シリコン膜19の膜厚はX)00 Aで
あった。
The deposited silicon sequentially reacts with gold and melts into a gold film at a certain concentration to form a 5l-Au eutectic alloy/γ. As the deposition progresses, excess silicon is deposited on the substrate ll with sign/g.
Precipitation begins as shown in . In this precipitation, the crystals of precipitated silicon/S are perpendicular to the substrate (//
/ :>, and the crystal orientation in the horizontal direction with respect to the substrate // is aligned due to the shape of the gold<turn/lI, so a single crystal silicon film 19 is formed on the substrate //. Gold is transferred onto this single crystal silicon crotch/9 to form a thin film of S1-Au eutectic alloy, resulting in the layer structure shown in FIG. 2F. The thickness of the single crystal silicon film 19 at this time was X)00A.

このようにして得られた第2F図の層構造をエレクトロ
ンマイクロプローブ分析法により深さ方向に元素分析を
行ってみると、基板l/の側から上方に向ってシリコン
wI/9があり、そのシリコン層/9の上にS 1−A
u共晶合金層〃のあることが確認された。また、単結晶
シリコン膜19に対して、透過電子回折法によりその結
晶性を調べた結果、第3図に示すように基板に対して垂
直方向に< II/ >軸の単結晶が形成されているこ
とが確認された。
Elemental analysis of the thus obtained layer structure shown in Figure 2F in the depth direction using electron microprobe analysis revealed that silicon wI/9 was present upward from the substrate l/ side. S1-A on top of silicon layer/9
It was confirmed that there was a u-eutectic alloy layer. Furthermore, as a result of examining the crystallinity of the single crystal silicon film 19 by transmission electron diffraction, it was found that a single crystal with <II/> axis was formed in the direction perpendicular to the substrate, as shown in FIG. It was confirmed that there is.

なお、第22図の構造において、5l−A、共晶合金層
〃は必要に応じて除去すればよい。
In addition, in the structure of FIG. 22, 5l-A and the eutectic alloy layer may be removed as necessary.

ところで、金パターン/lIの平面形状を、約600の
整数倍の角度を頂角に持つ多角形とすると、単結晶シリ
コンが成長できるのは次のような理由によるものと推察
される。すなわち、蒸着されたシリコンは金と反応して
合金を作るが、共晶温度以上に基板//が保たれている
ため、かかる5l−A、合金は溶融状態となる。シリコ
ン蒸着の進行により、遂には、5l−Au合金中にシリ
コン結晶が析出する。
By the way, if the planar shape of the gold pattern/lI is a polygon whose apex angle is an integral multiple of about 600, it is presumed that single crystal silicon can be grown for the following reason. That is, the deposited silicon reacts with gold to form an alloy, but since the substrate is kept above the eutectic temperature, the 5l-A alloy becomes molten. As silicon vapor deposition progresses, silicon crystals are finally deposited in the 5l-Au alloy.

析出した結晶は、基板面に平行に< iii >面が配
向するため、正三角形となり、その基板面内での方位は
結晶がJ−に、1溶融合金から受ける表面張力を最小と
するように配向する。
The precipitated crystal is an equilateral triangle because the <iii> plane is oriented parallel to the substrate surface, and the orientation within the substrate surface is such that the crystal is J- and the surface tension received from the molten alloy is minimized. Orient.

従って、金パターン/lIの形状は必ずしも上述した実
施例にのみ限定されるものではなく、最も単純なパター
ンは第6図に示すような正三角形の繰返しパターンであ
る。その他にも、第7図に示すパターンなど種々の変形
例があり、また、多角形の頂角についても、その角度を
600またはその整数倍に正確に定めなくてもよい。
Therefore, the shape of the gold pattern /lI is not necessarily limited to the above-described embodiment, and the simplest pattern is a repeating equilateral triangular pattern as shown in FIG. There are various other variations such as the pattern shown in FIG. 7, and the apex angle of the polygon does not have to be exactly 600 or an integral multiple thereof.

以上の実施例では、金属膜として、金を用いたが、その
他、アルミニウム、銀5faz銅)白金1ニツケル、パ
ラジウム、ガリウム、インジウノ\などのようにシリコ
ンと共晶または化合物を作るものであればいかなるもの
でもよい。
In the above examples, gold was used as the metal film, but other materials that form a eutectic or compound with silicon, such as aluminum, silver, copper, platinum, nickel, palladium, gallium, and indium, may also be used. It can be anything.

基板加熱の温度は、半導体を基板上に析出させるため、
共晶温度または化合物生成温度程度またはそれ以上の温
度であることが必要である。
The temperature of substrate heating is set so that the semiconductor is deposited on the substrate.
It is necessary that the temperature be at or above the eutectic temperature or compound formation temperature.

また、本実施例では、シリコンを供給するために蒸着法
を用いたが、その他、化学気相堆積法(CVD)、スパ
ッタリング法、プラズマCVD法等を用いてもよい。
Further, in this embodiment, a vapor deposition method is used to supply silicon, but other methods such as chemical vapor deposition (CVD), sputtering, plasma CVD, etc. may also be used.

更に、シリコン供給時に不純物をも同時に供給すれば、
不純物を含む結晶を成長させることもできるθ 結晶性のよいシリコンを成長させるためには、金属膜の
厚さは数百2以上であればよい。さらに加えて、繰り返
し形状の金属パターンを形成した後、その全面に上述の
金属パターンが転写される程度の厚さ、たとえば!00
 A程度以下の厚さで同種の金属を均一に付着させ、し
かる後にシリコンを付着させてもよい。
Furthermore, if impurities are also supplied at the same time as silicon supply,
It is also possible to grow crystals containing impurities. In order to grow silicon with good crystallinity, the thickness of the metal film only needs to be several hundred square meters or more. In addition, after forming a repeating metal pattern, the thickness is such that the above-mentioned metal pattern is transferred to the entire surface, for example! 00
The same type of metal may be uniformly deposited to a thickness of about A or less, and then silicon may be deposited.

さらに今まで述べた方法で成長させた結晶膜上に通常の
シリコンエピタキシ1′ル法により高純度シリコン結晶
膜を成長させることができるのはいうまでもない。
Furthermore, it goes without saying that a high-purity silicon crystal film can be grown by the usual silicon epitaxy method on the crystal film grown by the method described above.

金属膜パターンの繰り返しピッチについては数+μm以
下であればよく、好ましくは/〜3μm程度とする。
The repeating pitch of the metal film pattern may be several plus micrometers or less, and preferably about 1 to 3 micrometers.

また、基板としては、石英ガラスの他に、通常めガラス
、Si3N4やステンレスなどの金属丸板を用いてもよ
い。
Further, as the substrate, in addition to quartz glass, ordinary glass, a round metal plate made of Si3N4, stainless steel, or the like may be used.

以上説明したように、本発明では、金属とシリコンとの
合金より結晶を析出させ、その結晶の配向を金閲膜の繰
返し、パターンの形状により制御して単結晶シリコン膜
P形戊するので、平面基板上でも単結晶膜が得られる。
As explained above, in the present invention, crystals are precipitated from an alloy of metal and silicon, and the orientation of the crystals is controlled by repeating the film review and the shape of the pattern to form a P-type single crystal silicon film. A single crystal film can be obtained even on a flat substrate.

さらに、また、本発明では、共晶温度が低いので低温で
結晶を成長させることができ、従って、ソーダガラスや
パイレックスなど安価なガラスを使用できる。
Furthermore, in the present invention, since the eutectic temperature is low, crystals can be grown at low temperatures, and therefore inexpensive glasses such as soda glass and Pyrex can be used.

以上より、本発明は、低価格の太陽電池をはじめとして
、薄膜ト、ランジスタや三次元LSI等の製造に有効で
ある。
As described above, the present invention is effective for manufacturing low-cost solar cells, thin film transistors, transistors, three-dimensional LSIs, and the like.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の単結晶膜の形成法の説明図、第、2i図
〜第2F図は本発明における順次の工程の一実施例を示
すそれぞれ断面図、第3図はその繰返し金属パターンを
示す線図、第1IA図および第98図はリフトオフ法で
金属パターンを形成する工程を説明するためのそれぞれ
断面図、第5図は本発明により成長した結晶の構造を示
す電子回折写真、第6図および第7図は繰返し金属パタ
ーンの他の一例を示す線図である。 /・・・石英基板、 λ・・・溝、 3・・・金属膜、 //・・・非晶質基板、 7.2・・・金膜、 /3・・・レジストパターン、 /lI・・・繰返し金属パターン、 B・・・レジストパターン1、 /6・・・金膜、 /7・−6L−Au共晶合金1 71i′・・・析出シリコン結晶、 /q・・・単結晶シリコン+b、 〃・・・5i−Au共共晶合金ルウ 特許出願人  日本電信電話Ilモ社
Fig. 1 is an explanatory diagram of the conventional method of forming a single crystal film, Figs. 2i to 2F are cross-sectional views showing an example of the sequential steps in the present invention, and Fig. 3 shows the repeated metal pattern. 1A and 98 are cross-sectional views for explaining the process of forming a metal pattern by lift-off method, FIG. 5 is an electron diffraction photograph showing the structure of the crystal grown according to the present invention, and FIG. FIG. 7 and FIG. 7 are diagrams showing other examples of repeating metal patterns. /...Quartz substrate, λ...Groove, 3...Metal film, //...Amorphous substrate, 7.2...Gold film, /3...Resist pattern, /lI・...Repetitive metal pattern, B...Resist pattern 1, /6...Gold film, /7.-6L-Au eutectic alloy 1 71i'...Precipitated silicon crystal, /q...Single crystal silicon +b, 〃...5i-Au eutectic alloy Ru Patent applicant Nippon Telegraph and Telephone Ilmo Co., Ltd.

Claims (1)

【特許請求の範囲】 l)非晶質基板上に結晶成長する半導体と共晶または化
合物となる金属を約to0の倍数の角度の頂角をもつ多
角形の繰返し図形状に形成する工程と、しかる後に、前
記図形状の金属を有する基板上に半導体材料を堆積させ
て単結晶半導体膜を成長させる工程とを具えたことを特
徴とする単結晶半導体膜形成法。 コ)非晶質基板上に結晶成長する半導体と共晶または化
合物となる金属を約bd’の倍数の角度の頂角をもつ多
角形の繰返し図形状に形成する工程と、しかる後に、前
記図形状の金属を有する基板上に半導体材料を堆積させ
て単結晶半導体膜を成長させる工程と、その後、金属を
除去する工程と、前記単結晶半導体膜上に一新たな単結
晶半導体膜をエピタキシャル成長させる工程とを具えた
ことを特徴とする単結晶半導体膜形成法。 3)特許請求の範囲第1項または第一項に記載の単結晶
半導体膜形成法において、前記半導体はシリコンである
ことを特徴とする単結晶半導体膜形成法。 ll)特許請求の範囲第1項ないし第3項のいずれかの
項に記載の単結晶半導体膜形成法において、前記繰返し
形状は正三角形であることを特徴とする単結晶半導体膜
形成法。 3)特許請求の範囲第1項ないし第3項のいずれかの項
に記載の単結晶半導体膜形成法において、前記繰返し形
状は60 とl〃0の頂角を有する平行四辺形であるこ
とを特徴とする単結晶半導体膜形成法。 乙)特許請求の範囲第1項ないし第5項のいずれかの項
に記載の単結晶半導体膜形成法において、前記半導体材
料の堆積は前記半導体と前記金属との共晶温度以上で行
うことを特徴とする単結晶半導体膜形成法。
[Scope of Claims] l) A step of forming a metal that becomes a eutectic or a compound with a semiconductor whose crystal is grown on an amorphous substrate into a repeating polygonal shape having an apex angle that is a multiple of approximately to0; A method for forming a single-crystal semiconductor film, comprising the step of thereafter depositing a semiconductor material on the substrate having metal in the shape of the figure to grow a single-crystal semiconductor film. g) A step of forming a metal that becomes eutectic or a compound with a semiconductor crystal grown on an amorphous substrate into a repeating polygonal shape having an apex angle that is a multiple of approximately bd'; A step of depositing a semiconductor material on a substrate having a shaped metal to grow a single crystal semiconductor film, followed by a step of removing the metal, and epitaxially growing a new single crystal semiconductor film on the single crystal semiconductor film. A method for forming a single crystal semiconductor film, comprising the steps of: 3) A method for forming a single crystal semiconductor film according to claim 1 or 1, wherein the semiconductor is silicon. ll) The method for forming a single crystal semiconductor film according to any one of claims 1 to 3, wherein the repeating shape is an equilateral triangle. 3) In the method for forming a single crystal semiconductor film according to any one of claims 1 to 3, the repeating shape is a parallelogram having an apex angle of 60 and l〃0. Characteristic single crystal semiconductor film formation method. B) In the method for forming a single crystal semiconductor film according to any one of claims 1 to 5, the deposition of the semiconductor material is performed at a temperature equal to or higher than the eutectic temperature of the semiconductor and the metal. Characteristic single crystal semiconductor film formation method.
JP57137392A 1981-10-19 1982-08-09 Forming method of single crystal semiconductor film Granted JPS5928327A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP57137392A JPS5928327A (en) 1982-08-09 1982-08-09 Forming method of single crystal semiconductor film
US06/434,536 US4534820A (en) 1981-10-19 1982-10-15 Method for manufacturing crystalline film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57137392A JPS5928327A (en) 1982-08-09 1982-08-09 Forming method of single crystal semiconductor film

Publications (2)

Publication Number Publication Date
JPS5928327A true JPS5928327A (en) 1984-02-15
JPS6256651B2 JPS6256651B2 (en) 1987-11-26

Family

ID=15197599

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57137392A Granted JPS5928327A (en) 1981-10-19 1982-08-09 Forming method of single crystal semiconductor film

Country Status (1)

Country Link
JP (1) JPS5928327A (en)

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US5008206A (en) * 1986-07-11 1991-04-16 Canon Kabushiki Kaisha Method for making a photoelectric conversion device using an amorphous nucleation site
US5010033A (en) * 1987-03-27 1991-04-23 Canon Kabushiki Kaisha Process for producing compound semiconductor using an amorphous nucleation site
US5013670A (en) * 1986-09-18 1991-05-07 Canon Kabushiki Kaisha Photoelectric converter
US5070034A (en) * 1986-09-18 1991-12-03 Canon Kabushiki Kaisha Process for producing a semiconductor memory device
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US5363799A (en) * 1987-08-08 1994-11-15 Canon Kabushiki Kaisha Method for growth of crystal
US5425808A (en) * 1987-03-26 1995-06-20 Canon Kabushiki Kaisha Process for selective formation of III-IV group compound film
US5882960A (en) * 1993-06-25 1999-03-16 Semiconductor Energy Laboratory Co., Ltd Method of preparing a semiconductor having a controlled crystal orientation
US5895933A (en) * 1993-06-25 1999-04-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US5942768A (en) * 1994-10-07 1999-08-24 Semionductor Energy Laboratory Co., Ltd. Semiconductor device having improved crystal orientation
US6429483B1 (en) 1994-06-09 2002-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
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US6706572B1 (en) 1994-08-31 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film transistor using a high pressure oxidation step
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US5008206A (en) * 1986-07-11 1991-04-16 Canon Kabushiki Kaisha Method for making a photoelectric conversion device using an amorphous nucleation site
US5013670A (en) * 1986-09-18 1991-05-07 Canon Kabushiki Kaisha Photoelectric converter
US5070034A (en) * 1986-09-18 1991-12-03 Canon Kabushiki Kaisha Process for producing a semiconductor memory device
US5425808A (en) * 1987-03-26 1995-06-20 Canon Kabushiki Kaisha Process for selective formation of III-IV group compound film
US5010033A (en) * 1987-03-27 1991-04-23 Canon Kabushiki Kaisha Process for producing compound semiconductor using an amorphous nucleation site
US5304820A (en) * 1987-03-27 1994-04-19 Canon Kabushiki Kaisha Process for producing compound semiconductor and semiconductor device using compound semiconductor obtained by same
US4977096A (en) * 1987-06-30 1990-12-11 Canon Kabushiki Kaisha Method of making a photosensor using selective epitaxial growth
US5363799A (en) * 1987-08-08 1994-11-15 Canon Kabushiki Kaisha Method for growth of crystal
US5882960A (en) * 1993-06-25 1999-03-16 Semiconductor Energy Laboratory Co., Ltd Method of preparing a semiconductor having a controlled crystal orientation
US5895933A (en) * 1993-06-25 1999-04-20 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US7148094B2 (en) 1993-06-25 2006-12-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US6756657B1 (en) 1993-06-25 2004-06-29 Semiconductor Energy Laboratory Co., Ltd. Method of preparing a semiconductor having controlled crystal orientation
US6730549B1 (en) 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
US8330165B2 (en) 1994-06-09 2012-12-11 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US7547915B2 (en) 1994-06-09 2009-06-16 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having SiOxNy film
US6429483B1 (en) 1994-06-09 2002-08-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for forming the same
US6706572B1 (en) 1994-08-31 2004-03-16 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing a thin film transistor using a high pressure oxidation step
US6627487B2 (en) 1994-10-07 2003-09-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US6211536B1 (en) 1994-10-07 2001-04-03 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device having improved crystal orientation
US5942768A (en) * 1994-10-07 1999-08-24 Semionductor Energy Laboratory Co., Ltd. Semiconductor device having improved crystal orientation
US6601308B2 (en) 2002-01-02 2003-08-05 Bahram Khoshnood Ambient light collecting bow sight
USRE39686E1 (en) * 2002-01-02 2007-06-12 Bahram Khoshnood Ambient light collecting bow sight

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