JPS59225359A - Signal input device for signal observation equipment - Google Patents

Abstract

PURPOSE:To correct the difference between delay times accurately and easily by comparing a calibration logic signal passing a reference delay circuit with a calibration logic signal passing a probe and a variable delay circuit to control the variable delay circuit so that both delay times coincide. CONSTITUTION:A calibration logic signal generated from a clock pulse generator 23 is inputted into data input terminals D1-D3 of an input latch circuit 18 passing through variable delay circuits 16a-16n and the like while sent to a clock input terminal CL passing through a reference delay circuit 24. The variable delay circuit 16a-16n outputs the delay of the former signal from the latter signal to output terminals Q1-Q3. A delay time control circuit 30 shorten the delay time by one step in response to a command signal from a CPU 19. The CPU 19 memorizes the coincidence position of the variable delay circuit 16a to correct the value thereof 16a. Likewise, the correcting operation of the remaining channels continues to make the delay time of all channels coincide with that in the line of the reference delay circuit 24.

Description

TECHNICAL FIELD The present invention relates to a signal input device for correcting delay time differences between a plurality of signal input lines of a signal observation device of a logic analyzer.

Conventional technology logic analyzers have multiple signal input channels and corresponding memory, and can simultaneously capture, store, and display logic signals with multiple phenomena that are difficult to observe with conventional oscilloscopes. It is possible to
It is an effective measuring instrument for research, development, maintenance and repair of digital equipment.

A logic analyzer converts the observed signal input from the probe into a binary digital signal using a comparator.
It is sampled at every sampling clock of an arbitrary period and sequentially stored in the memory. This sampling clock can be used either by using an internal clock generated inside the logic analyzer or by synchronizing it with an externally inputted clock.
There are cases where the slA section clock signal is used. A measurement method using an internal clock is called asynchronous measurement, and a measurement method using an external clock is called synchronous measurement.

When measuring the time difference between a plurality of observed signals using such a logic analyzer, it is common to perform asynchronous measurement by sampling the observed signals using an internal clock. The internal tide lock used in this case has a short period (high frequency), and the measurement accuracy is the same. Recently, a logic analyzer with a clock cycle of 2 ns (500 MHz) has also been announced.

By the way, the observed signal input from the glove is sent to the sampling circuit (
When sending signals to a latch circuit (also referred to as a latch circuit), multiple channels IB1, which occur due to factors such as differences in signal delay times inherent in buffer amplifiers and converters in the probe, and uneven lengths σ of signal transmission cables, etc. It is required to minimize the difference in signal transmission time. Therefore, it is necessary to use a conventional logic analyzer to make the lengths of signal transmission cables as equal as possible, or to measure the difference in delay time of comparators, etc. in advance, and to reduce the required number of logic (number of analyzer input channels) -
The probes were grouped together in Mi and selected for each logic analyzer to minimize measurement errors. However, using this type of method to equalize signal transmission time differences between multiple channels is not only troublesome but also extremely difficult.

As a method to solve the above-mentioned drawbacks,
7-19] Publication No. 575, a reference signal transmission line consisting of a reference input line and a fixed delay line is provided, a clock signal is added to this reference signal transmission line and an unloading 1 constant signal input line,
A method for correcting the delay time difference based on a comparison of both delay outputs is disclosed. According to this method, the signal transmission time difference between 4i channels in the same globe is corrected. However, no method has been disclosed for correcting the signal transmission time difference between multiple gloves. However, when correcting the signal transmission time difference using the above method, a clock generator must be connected to the base input terminal of the glove, and even when performing asynchronous measurements using the internal clock, the base of the globe must be connected. A clock generator must be connected to the input input terminal. Therefore, it is not easy to use.

OBJECTS OF THE INVENTION Therefore, it is an object of the present invention to provide a signal input device that can accurately and easily correct signal transmission time differences (delay time differences) between a plurality of gloves and is easy to use.

Structure of the Invention To achieve the above object, the present invention includes a plurality of globes each including a plurality of signal lines for inputting observed signals, and a No. 4n input signal line of each of the plurality of globes. a reference delay circuit arranged so as not to pass through the plurality of probes; and a reference delay circuit arranged so as not to pass through the plurality of probes; a calibration logic signal generator for applying the signal to part or all of the signal input line, and a calibration logic signal that has passed through the base delay circuit and the calibration logic signal that has passed through the input line and the variable delay circuit. The present invention relates to a signal input device for a signal observation device, which includes a delay detection control circuit that compares a logic signal and controls a front Nr2 TfJ variable delay circuit so that both delay times match.

Effects of the Invention According to the above invention, instead of providing a reference delay circuit for each glove, a common reference delay circuit is provided for all the probes, and this is used to calculate the signal transmission time difference (delay time difference) of all the probes. This correction can be easily achieved. Furthermore, since the reference delay circuit is arranged so that it does not pass through the glove, it is possible to provide a device that is easy to use.

Embodiment Next, a logic analyzer according to an embodiment of the present invention will be described with reference to FIGS. 1 to 4.

In Figure 1, the second signal input connectors (2) and (3) provided on the logic analyzer main body tl+
] and second gloves +41 and +51 are joyably coupled. These first and second gloves 141
+51 is the input terminal (6a) to (6n), (7a) to (
7n), probe pod i8+ (91, and signal transmission cables (1(+a) to (Hln), (11a) to
(11n), and the signals from the input terminals (6a) to (6n) and (7a) to (70) are connected to the connector +21 +3 of the logic analyzer body tl+.
1K transmission. Note that probe pods (64 (71) are buffer amplifiers (12a) to (12n), (13a)
) to (]3n) and voltage combiner fi for waveform shaping.
(14aJ~(14n), (45a)~(tsr+)
It consists of

Logic analyzer main body (inside each glove [41
(Variable delay circuit (16a) corresponding to 51 channels)
) to (16r+) and (17a) to (17r3), the output terminals of which are connected to the data input terminals D+ to D6 of the input circuit, respectively. Input latch circuit α~
samples the logic state of the input line for each clock signal supplied to the clock terminal CL and outputs it to the output terminals Q1 to Q.
6 to the next stage central processing unit, ie, c p v (191). The CPU (191) processes the observed signal and corrects the delay time according to a predetermined program.

(2iJl&'f is a memory, which stores and outputs the data of the observed signal. 211 is a display circuit, which forms the display signal 2 based on the data given from CP (J091). It is supplied to the CRT ■21.In addition, lmo17 (2Ql, display IJol
l(2D and CRTQ21 are used when observing input data and are not directly related to delay time correction operation.

Section 1 is a clock signal generator, and CP [J (19
] A clock signal as a calibration logic signal is generated based on the control gAj. Therefore, this clock signal generator (
It is also possible to call c) a clock signal and calibration logic signal generator.

241 is a reference delay circuit, and signal input terminals (6a) to
Input latch circuit σ8 from (6n), (7a) to (7n)
) consists of a delay line for providing a reference delay circuit corresponding to the delay time from data input terminals D1 to D6 of the data input terminals D1 to D6. Na2,
The input terminal of this reference delay circuit (241) is fixedly connected to the clock signal generator (c), and the output @ is input to the clock terminal CL of the caratchi circuit by valving the changeover switch (25).
The connection is broken.

Changeover switch c! 5) &X This is for switching between the internal clock and the external clock, and the internal clock contact
and an external clock contact EXT. Note that an external clock supply circuit consisting of an external clock input connector and an external clock circuit (271) is connected to the external clock contact EXT.

The track is a connector for supplying a calibration logic signal, and is connected to the clock signal generator 031. (29a)～(
29n) represents the signal path for connecting the calibration logic signal supply connector rigidity to the input terminals (6a) to (6n) or (7a) to (7n) of Globe+81 or (91). +41 F51 input terminal (6
Connecting means having a connector configuration matching a) to (6n), (7a) to (7n) and the calibration logic signal supply connector u8j, or a lead wire with a clip of the same length, etc.

c30) is a delay time control circuit, which controls variable delay circuits (]6a) to (1an), (17a) to (17) based on the signal obtained from CP [1 (191) during delay time correction.
This is a circuit that generates a signal for controlling n). The delay detection control circuit according to the present invention corresponds to the input latch circuit α, CP[J(11), and delay time control circuit of this embodiment.

FIG. 2 is an explanatory diagram of j variable delay circuits (16a) in the youngest J diagram, and this variable delay circuit f@(16a)
consists of a delay line (31) and switches (32a) to (32n) connected to each tack of this delay line (311), and switches ( 32a) to (32n) are turned on and the delay time is adjusted. Remaining variable delay circuit (] 6b) in Figure 1
~(16n), (17a) ~(1711) are also configured in the same way as in FIG. In addition, in FIG. 1, the delay time control circuit α
n) and (17aJ to (17n)) are connected by one line, but in reality they are connected by multiple lines.

Figure 3 shows a part of the input launch circuit marked a. That is, only the D-type flip-frog (18a) that launches the output of the variable delay circuit (16a) of the [th] channel is required. This D type flip frog (18a)
latches data input to the data input terminal CL in synchronization with a clock signal input to the clock terminal CL. Although FIG. 3 shows only the D-type flip-frog (18a) of the &'@j-th channel, the remaining channels also include similar fold-type flip-frogs. That is, the first
The input latch circuit (I8) in the figure includes a number of D-type flip-flops corresponding to the number of channels.

Next, input terminals (6a) to (6) of valley globe IJt5+
n) A correction operation for equalizing the delay times from (7a) to (7n) to input terminals D+ to D6 of the input launch circuit will be explained.

In this example, the calibration logic signal supply connector (2
Since 8j only has connection terminals corresponding to the number of channels of a single globe, first
In order to correct the delay time of the channel corresponding to
(6n) and the IJ-do wire (29a) with a clip, for example.
~(29r+1 etc. are connected, and the contact of the changeover switch (25) is not turned on based on the control of the selector switch (25). and further controls and sets the variable delay circuits (16a) to (16n) to maximize the delay time of the variable delay circuits (16a) to (16n) based on the control of the CPU (191). .

Next, follow the instructions of C'PtJ (191).
The clock pulse as a calibration logic signal is generated from the pulse generator (2?A).As a result, the calibration logic signal is transmitted to each channel's amplifier (12a) to (12n)
, comparators (14a) to (14n), transmission cables (xoa) to (1on), variable delay circuits (16a, l to
(16n), etc., to the data input terminals D1-J of the input latch circuit (18). At the same time, the calibration logic signal passes through the reference delay circuit t24+Y and is sent to the clock input terminal ('L) of the input launch circuit (181).

Since the delay circuits (16a) to (1c; n) and the youngest child are set to the maximum delay state, the signals of the data input terminals D1 to D3 based on the first calibration logic signal and the clock input terminal C' The L signal and the input launch circuit (1
When the comparison .sigma. is found in step 81, the data input terminal outputs to the output terminals Q, .about.Q3 that the signal of .about.Da is delayed by .degree. C. compared to the signal of the clock terminal CL. Such an operation will be explained with reference to FIG. 4, which shows a comparison operation of both inputs.

Now, as shown in Figure 4 (A) <1. If the calibration logic signal is generated at this point, the reference delay circuit (241'
, ff to the clock input terminal ClIC of the input latch circuit °a~, as shown in FIG. On the other hand, data input terminal■
)□~D3, for example, the logic signal for delay calibration is obtained at the time point < 1. as shown in Fig. 4 (hl). Figure 4 (T3)
If the data is latched, a logic 0 will be output. As a result, it can be seen that, for example, the delay time of the signal transmission path of the input terminal I)+ is delayed from the delay time of the reference delay circuit (24).Therefore, from the CPU (1ω) to the variable delay circuit (16
A command signal is generated to switch the switches (32a) to (32n) of a) to (16n) to shorten the delay time, and in response, the delay time control circuit 13i11 shortens the delay time by J steps. Switch to shorten (
32a) to (32n) are controlled. After this operation, the calibration logic signal is generated again, and the comparison shown in FIG. 4 is performed. Then, the point at which the output of the input latch circuit first becomes logic "1" is checked Ii+.

The fact that the specific soft output first became logic ``′]'' means that
Figure 4 shows that the phase of the pulse of Bl and the pulse of Figure 4 (0) almost coincide. (16aJ
, and its variable delay circuit (lFia
). In this way, the input terminals (6a) to 6a for sequentially adjusting the delay time of the input terminal section or all the transmission paths to match the base delay time of the reference delay circuit 4)
(6n) is completed. Before correction, the input terminals (6a) to (6n) of the j-th globe (41) [usually the delay times between corresponding channels are not all the same, so the data input terminals D1 to D, and the clock input Terminal C
Both L signals do not match at the same time. Therefore, the correction operation of the channel whose internal inputs match stores the value of the matched variable delay circuit at CP[J(l), completes the correction, and continues the correction operation of the remaining channels in the same way. The delay time of the reference delay circuit (2) can be made to match the delay time of the line of the reference delay circuit (2).

After the delay time correction of the first probe (4) is completed as described above, the connector G! 81 and the second probe (5
1 input terminals (7a) to (7n), and
A similar correction is made for the transmission path related to the globe (51). As a result, the delay time of the valley channel of the probe +41 and the delay time of each channel of the second probe (51) are substantially the same. become.

When observing the observed logic signal in asynchronous measurement mode after delay time correction, connect the Globe iJ (510 input terminals (6a) to (6n), (7a) to (7n) to the observed logic signal circuit. , the observed logic signal is input.The input signal is input to the amplifiers (12a) to (12r+),
(13a) to (13n), and the comparator (]
7 in 4a-(14n), (15a)-(15n)
After being shaped based on the threshold voltage 'TH, it is input to the input latch circuit 081. Input latch circuit a~
A clock signal generator (23) is connected to the clock input terminal CL of the
) is supplied, so this clocked portion becomes the sampling signal and outputs the input signal from the Quezan ring (latched to the output terminals Q+ to Q).
Output from 6. Sampled data is memo IJ
(20JK is once stored, and then in the read mode, the data is read out from the memory 4, converted into a display signal by the display circuit (21), and displayed on the CRT f22+. This type of operation is not shown in the figure. This is done based on the trigger obtained from the trigger circuit where σ is omitted.

When performing synchronous measurement using an external clock, the VC switches the changeover switch (25) to contact EXT. In this case, the signal delay time of the external clock circuit (27j (including the total delay time from the input terminal of the 7' lobe for external clock signal input to the switch c25)) is calculated by the reference delay circuit c! By making the delay time slightly smaller than the delay time of 41, the data set-up time (T8) of the logic analyzer with respect to the external clock can be set to a certain value, and the hold time (TH) can be set to zero.

As is clear from the above (this embodiment has the following points).

(AI If you use multiple gloves, for example 2
In an embodiment of the present invention using two globes, not only can the delay time difference between the channels in globes 14+151 be virtually eliminated, but also the difference in delay time between the first globe (41 and the second globe (54)) can be reduced to substantially zero. It can be used without any delay time between.

(131 reference delay circuit 24) is fixedly disposed within the logic analyzer main body tll, so when correcting the delay time, the reference delay circuit G! The connection operation (4) is substantially unnecessary, and an easy-to-use device can be provided.

Modifications The present invention is not limited to the above-described embodiments, but can be modified, for example, as follows.

(a) When correcting the delay time, the Hegi sailing circuit (1
6a) to (16n) etc. may be set to the minimum delay time and the correction may be started. In the case of this minimum delay time, an output of logic "]" is usually obtained as there is a pulse of fBl in FIG. When they almost match, the logic “♂” is output.

(bl The delay time may be corrected for each j channel.

(cl connector (increase the number of terminals of 281,
and the second globe +41 (51), the calibration logic signal may be supplied to both at the same time.

(di buffer amplifiers (12a) to (12n),
(13a) to (13n), and/or comparator (1
4a) to (14n), (45a) to (15n) f Logic analyzer body (for example, variable delay circuit (
16a) to (16n) and (17a) to (17n).

Therefore, the globe [4J f5+ has multiple signal transmission cables (LOA) ~ (LON), (11A) ~ (11N
) may be used alone.

There is also a buffer amplifier (1
Only 2aJ~(12n), (13a)~(13n)- are provided, and the controllers (14a)~(14n), (15
a) ~(15n)q body ill K may be transferred.

tel It is of course applicable to the case where more gloves are provided.

(fl Number of channels in a single probe is 1 to 8
Channels are preferred, but may be increased or decreased as needed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a logic analyzer according to an embodiment of the present invention, FIG. 2 is a circuit diagram showing one variable delay circuit in FIG. 1, and FIG. 3 is a circuit diagram showing two launch circuits in FIG. 1. The circuit diagram of FIG. 4 is a waveform diagram for explaining the delay time correction operation in the logic analyzer of FIG. 1. (1)...Logic analyzer body, +2+ta+...
・・Connector, (41・jth glove, (51・
...Second probe, (6a) to (6n) ('7a)
~(7n)...Input terminal, +81 (91...Probe board, (10a) ~(10n) (lla)
~(lln,) -=signal transmission cable, (]6su~(
16n) (17a) to (17n)...variable delay circuit,
Oat...Input latch circuit, (191...CPU, C3j...Clock signal generator (logic signal generator for calibration), Seki...Basic extension circuit, Toru...Logic signal for calibration Supply connector. Agent Noriji Takano procedural corrector (spontaneous) April 23, 1980 Patent Application No. 100682 2 Title of invention Signal input device for signal observation device 3 Related: a of applicant 4's agent's explanation. 8. Contents of the supplement. As shown in the attached sheet. Add "etc." afterward. (3) From page 7, line 15 of the specification to page 8, line 15 of "
Above purpose 310100. It is something. ” to the following sentence. ``To achieve the above object, the present invention includes a plurality of probes for inputting observed signals, a variable delay circuit connected to the output side of the plurality of probes, and a plurality of probes. a reference delay circuit arranged so that the reference delay circuit does not pass through the reference delay circuit; a calibration logic signal generator for applying a calibration logic signal to the reference delay circuit and simultaneously applying it to the probe; a delay detection control circuit that compares the calibration logic signal with the calibration logic signal that has passed through the globe and the variable delay circuit and controls the variable delay circuit so that both delay times match; This invention relates to a signal input device for an observation device.'' 2. Claims (11) A plurality of probes for inputting observed signals; a variable delay circuit configured to prevent signals from passing through the plurality of probes; a reference delay circuit disposed in the reference delay circuit; a calibration logic signal generator for applying a calibration logic signal to the reference delay circuit and simultaneously to the probe; and the calibration logic passed through the reference delay circuit. A signal observation device comprising: a delay detection control circuit that compares a signal with the calibration logic signal that has passed through the probe and the variable delay circuit and controls the variable delay circuit so that the delay times of both match. (21) The signal input device according to claim 1, wherein the probe has a plurality of channels. (3) The signal input device according to claim 1, wherein the probe includes a buffer amplifier and a voltage comparator. The signal input device according to item 1. (4) The delay detection control circuit has a data input terminal to which the output of the variable delay circuit is input, and a clock input terminal to which the output of the reference delay circuit is input. 4. The signal input device according to claim 1, wherein the signal input device includes a D-type flip-frog.

Claims (1)

[Scope of Claims] (11) A plurality of globes each including a plurality of signal input lines for inputting observed signals, and respective variable delays connected to the signal input lines of each of the plurality of globes. a reference delay circuit arranged so as not to pass through the plurality of groves, and a part or all of the signal input lines of the plurality of groves at the same time that a calibration logic signal is applied to the reference delay circuit. a calibration logic signal generator for applying the signal to the reference delay circuit; and comparing the calibration logic signal that has passed through the reference delay circuit with the calibration logic signal that has passed through the input line and the variable delay circuit. A signal input device for a signal observation device, comprising: a delay detection control circuit that controls the variable delay circuit so that both delay times match. (2) A patent claim in which the glove is composed of a plurality of signal transmission cables. The signal input device according to claim 1. (ζ) The signal input device according to claim 1, wherein the globe includes a buffer amplifier, a voltage comparator, and a signal transmission cable. (4) The delay detection control Claim 1: The circuit includes a D-type flip-flop having a data input terminal to which the output of the self-variable delay circuit is input, and a clock input terminal to which the output of the reference delay circuit is input. or the signal input device according to claim 2 or 3. (51) The signal input line is a line including a buffer amplifier and a voltage comparator.
Signal input device as described in section.