JP2004239754A - System and method for correcting interchannel skew of a plurality of sampling digitizers - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interchannel skew correction system for a plurality of sampling digitizers capable of correcting at any time an interchannel skew between the plurality of the sampling digitizers in a state of being assembled into a system. <P>SOLUTION: The interchannel skew correction system for the plurality of the sampling digitizers, is provided with an M-distributed clock supply means for clocks of the same timing, and a skew measurement means. The M-distributed clock supply means individually separates A plurality of M signals to be measured output from a DUT on a performance board for putting the DUT on and performs interruptions, and supplies calibrating clocks of the same timing condition to a plurality M of sampling head sections. The skew measuring means specifies an interchannel skew ΔT on the basis of groups of measured data acquired by supplying the calibrating clocks to the plurality M of the sampling head sections, and performing sampling measurement at each sampling head section. <P>COPYRIGHT: (C)2004,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a device for correcting skew between channels of a multiple sampling digitizer. In particular, the present invention relates to an inter-channel skew correction apparatus for a multi-sampling digitizer, which is capable of correcting the inter-channel skew between a plurality of sampling digitizers at any time while being incorporated in a system.
[0002]
[Prior art]
[0003]
[Patent Document 1]
JP-A-2002-139550 (FIG. 6)
JP-A-2002-189036 (FIG. 7)
[0004]
Japanese Patent Application Laid-Open No. 2002-139550 provides a sampling digitizer that can match the timing of a clock signal to a jitter measurement point in a short time. According to this, the timing of the clock signal can be matched with a desired point of the input signal waveform to be captured in a short time, and the test time can be reduced.
Japanese Patent Application Laid-Open No. 2002-189036 discloses a sampling digitizer that can control the application timing of a clock signal without increasing a jitter component by applying a PLL circuit configuration. According to this, by controlling the phase of the sampling clock to change the phase of the PLL circuit configuration, sampling can be performed at a desired timing (phase).
[0005]
Next, FIG. 1 is a conceptual configuration diagram of a two-channel sampling digitizer provided in a conventional semiconductor test apparatus. Here, it is assumed that measurement signals S1a and S2a, which are high-speed repetitive signals, are output from two output terminals of a device under test (DUT) on the performance board PB, and a two-channel sampling digitizer has one It is assumed that it is stored in the sampler board 20.
The main components are a performance board PB, transmission cables CB1 and CB2, a clock source 40, a sampling head unit 101 for CH1, a sampling head unit 102 for CH2, and a clock distributor 42 in the sampler board 20. The digitizer 150 includes AD converters 31 and 32, acquisition memories 51 and 52, and other subsequent circuits (not shown).
[0006]
As an example of the internal configuration of the two sampling head units 101 and 102, as shown in FIG. 2, a sampling head SH, a pulsar 14, and a variable delay unit (phase shift unit) 16 are provided. The variable delay means 16 receives the distributed clock 42clk from the clock distributor 42 and outputs a delayed clock 16clk delayed to a desired phase position based on a delay control signal 16c from outside. In addition, as the delay resolution, a minute delay of, for example, about 5 picoseconds is possible.
[0007]
The pulser 14 receives the delay clock 16clk and outputs positive and negative sampling pulses SP + and SP- converted into predetermined narrow pulses. The sampling head SH receives the positive and negative sampling pulses, receives an input high-speed repeatedly generated measurement signal S1b, and performs instantaneous sampling by an equivalent sampling method (see FIG. 2 of JP-A-2002-139550). It is output as a low-speed sampling waveform S11 converted to a low-speed frequency.
Here, the delay time t9 from the input terminal of the distributed clock 42clk of the variable delay unit 16 to the output terminal of the pulser 14 differs depending on the variation of the mounted components. It fluctuates due to change, and also fluctuates with time.
[0008]
In response to the low-speed sampling waveforms S11 and S12, the digitizer unit 150 shown in FIG. 1 continuously outputs the measurement data 31d and 32d that have been quantized and converted by the corresponding AD converters 31 and 32, respectively. , 52 sequentially. Thereafter, by reading the acquired measurement data group and performing data processing, various items such as timing, phase, and group delay amount can be calculated.
[0009]
By the way, in order to perform timing measurement, phase, group delay measurement and the like between the two measurement signals S1a and S2a, it is important to eliminate inter-channel skew between both sampling digitizers in advance. Here, the causes of the skew between the channels include, firstly, skew due to variations in mounted components between the sampling digitizers, and secondly, errors in the transmission line in the section from the output end of the DUT to the input end of the sampler board 20. And skew due to environmental temperature fluctuation and aging.
[0010]
Next, FIG. 3 is a principle configuration diagram for explaining a conventional adjustment method for removing skew between two-channel circuits in the sampler board 20. This adjustment method will be described.
The adjustment is performed by connecting a dedicated adjustment jig provided outside as shown in FIG. 3 to the sampler board 20 alone.
First, the high-speed calibration clock PGclk generated from the pulse generator PG is divided into two by the power splitter PS and supplied to the input terminals TM1 and TM2 of the sampler board 20 via the transmission line CB3 having the same delay amount. Therefore, the measurement signals S1b and S2b for calibration having the same amplitude are supplied at the same timing to both input terminals TM1 and TM2 of the sampler board 20.
On the other hand, the high-speed calibration clock PGclk generated from the pulse generator PG is converted into a low-speed clock divided by a 1 / N frequency divider, and then supplied to the clock distributor 42 on the sampler board 20 side.
[0011]
Next, the sampling head units 101 and 102 on the sampler board 20 receive the calibration measurement signals S1b and S2b as inputs and sample based on the low-speed clock. Then, step-like low-speed sampling waveforms S11 and S12 down-converted to 1 / N are output. The low-speed sampling waveforms S11 and S12 are set to a measurement state by an oscilloscope or the like, and the delay amount of the variable delay means 16 is adjusted and controlled so that the skew ΔT between the two waveforms becomes zero. The calibration delay amount setting data obtained as described above is stored. As a result, skew due to component variations between the two-channel sampling digitizers in the sampler board 20 can be eliminated.
[0012]
[Problems to be solved by the invention]
On the other hand, the skew between the transmission lines in the section from the output end of the DUT to the input end of the sampler board 20 is regarded as having the same propagation delay by being connected by equal-length wiring. However, since the coaxial wiring on the performance board PB and the soldering process of the line end are individually wired by the user, it may cause a variation in the propagation delay amount. Therefore, when an actual DUT is tested in a state in which the DUT is incorporated in a semiconductor test apparatus, there is a case where the skew between channels may cause a practical problem. In this respect, the conventional calibration method has a practical problem.
In addition, the circuit elements of the sampling digitizer vary in skew between channels due to a change in environmental temperature and a change with time. Also in this case, when an actual DUT is tested by a semiconductor test apparatus, there may be a practical problem in timing measurement, phase, group delay measurement, etc. of the two due to skew between channels. There are disadvantages.
[0013]
Accordingly, an object of the present invention is to provide an inter-channel skew correction device for a plurality of sampling digitizers, which is capable of correcting the inter-channel skew between a plurality of sampling digitizers at any time while being incorporated in a system.
[0014]
[Means for Solving the Problems]
A first solution is shown. Here, FIG. 4 shows a solution according to the present invention.
In order to solve the above-mentioned problem, a sampling digitizer having a plurality of M (M is an integer of 2 or more) channels includes a plurality of M high-speed repetitive signals (signals to be measured) output from a device under test (DUT) on a performance board PB. ), And a plurality of M sampling head sections 101, 102,... Which sample at predetermined timing and convert them into low-speed low-speed sampling waveforms S11, S12,.
A clock source 40 for generating and supplying a sampling reference clock Rclk to the sampling head unit;
A digitizer unit 150 that receives the low-speed sampling waveform, performs quantization conversion, and sequentially stores the quantized data in corresponding acquisition memories 51, 52,.
An inter-channel skew correction device for a multi-sampling digitizer that corrects inter-channel skew for a multi-M channel sampling digitizer that receives a plurality of M signals to be measured from a DUT and performs sampling measurement with the above.
M distribution clock supply means having the same timing, and skew measurement means 80,
The M distribution clock supply means separates and interrupts a plurality of M signals to be measured output from the DUT on the performance board PB on which the DUT is mounted, and calibrates the plurality of M sampling heads under the same timing condition. That supplies the clock of
The skew measuring unit 80 supplies the clock for calibration to a plurality of M sampling heads, and specifies the skew ΔT between channels based on a group of measurement data obtained by sampling measurement at each sampling head. Yes,
An inter-channel skew correction apparatus for a multiple sampling digitizer, comprising:
[0015]
Next, a second solution will be described. Here, FIG. 4 shows a solution according to the present invention.
One mode of the above-mentioned M distribution clock supply means includes a calibration pulse generator PG, a cable CB5, a power splitter PS, and M switches SW1, SW2,.
The calibration pulse generator PG and the cable CB5 are provided outside the performance board PB to generate a calibration clock PGclk for calibration, and are connected to the power splitter PS on the performance board PB via the cable CB5. To supply
The power splitter PS is a distributor capable of at least M distribution. The power splitter PS receives the calibration clock PGclk from the pulse generator PG and distributes the distributed clocks PSclk1, PSclk2,. Supply to the switch,
Each of the switches SW1, SW2,... Is a two-input, one-output high-frequency relay, which separates the signal under measurement of the DUT during calibration, and replaces the distributed calibration clock with the corresponding sampling head units 101, 102,. The skew correcting device between channels of the above-mentioned multiple sampling digitizer is provided.
[0016]
Next, a third solution will be described. Here, FIGS. 4 and 5 (a) show a solution according to the present invention.
In order to solve the above problem, the skew measuring means 80 measures a skew amount between channels between a plurality of M sampling digitizers to obtain a correction amount,
A calibration clock PGclk of a predetermined frequency is generated from the calibration pulse generator PG, and the plurality of M switches are switched and controlled to distribute M, and distribution calibration clocks PSclk1, PSclk2,. Means for supplying to the sampling head unit,
A plurality of M sampling heads receive the distributed calibration clocks as input signals, sample and quantize each, and store them in a corresponding acquisition memory as a group of measurement data so that the waveform of the input signal can be specified. And
Means for reading out the stored plurality of M measurement data groups, specifying the waveform of the distribution calibration clock as an input signal, and calculating the inter-channel skew ΔT of each sampling digitizer from the waveform. There is a device for correcting skew between channels of a multiple sampling digitizer.
[0017]
Next, a fourth solution will be described. Here, FIGS. 4 and 5 (a) show a solution according to the present invention.
One aspect of the sampling digitizer of the plurality of M (M is an integer of 2 or more) channels is to receive a plurality of M high-speed repetitive signals (signals to be measured) output from a device under test (DUT) on the performance board PB. A plurality of M sampling head units 101, 102,... Which sample at predetermined timings and convert them into low-speed low-speed sampling waveforms S11, S12,.
A clock source 40 for generating and supplying a sampling reference clock Rclk to the sampling head unit;
A digitizer unit 150 that receives the low-speed sampling waveform, performs quantization conversion, and sequentially stores the quantized data in corresponding acquisition memories 51, 52,.
M distribution clock supply means having the same timing, and skew measurement means 80,
The M distribution clock supply means separates and interrupts a plurality of M signals to be measured output from the DUT on the performance board PB on which the DUT is mounted, and calibrates the plurality of M sampling heads under the same timing condition. That supplies the clock of
The skew measuring means 80 supplies the clock for calibration to a plurality of M sampling heads, and specifies the skew ΔT between channels based on the waveform data of the clock for calibration acquired by each sampling head. Yes,
A method for correcting skew between channels of a multi-sampling digitizer for correcting skew between channels for a plurality of M-channel sampling digitizers having the above configuration and receiving a plurality of M signals to be measured from a DUT and performing sampling measurement,
Prior to actual measurement of the DUT, a skew measurement procedure for obtaining a channel skew ΔT between sampling digitizers of a plurality of M channels is provided.
In the actual measurement of the DUT, the variable delay means 16 for delaying the sampling clock incorporated in the sampling head unit of the sampling digitizer of a plurality of M channels based on the skew ΔT between channels obtained in the skew measurement procedure, A predetermined amount is subtracted or added from the delay set value (delay control signal 16c) set in the variable delay means 16 so that the inter-channel skew ΔT specified in step (c) is canceled, and is output from the DUT. A step of sampling and measuring each of the plurality of M signals to be measured and storing the signals in an acquisition memory;
A read processing procedure for reading a measurement data sequence of a plurality of channels acquired in the acquisition memory in the sampling measurement and supplying the read data sequence to a data processing unit (not shown) in a subsequent stage;
There is an inter-channel skew correction method for a multi-sampling digitizer which has the above and cancels the inter-channel skew.
[0018]
Next, a fifth solution will be described. Here, FIGS. 4 and 5 (a) show a solution according to the present invention.
One aspect of the sampling digitizer of the plurality of M (M is an integer of 2 or more) channels is to receive a plurality of M high-speed repetitive signals (signals to be measured) output from a device under test (DUT) on the performance board PB. A plurality of M sampling head units 101, 102,... Which sample at predetermined timings and convert them into low-speed low-speed sampling waveforms S11, S12,.
A clock source 40 for generating and supplying a sampling reference clock Rclk to the sampling head unit;
A digitizer unit 150 that receives the low-speed sampling waveform, performs quantization conversion, and sequentially stores the quantized data in corresponding acquisition memories 51, 52,.
M distribution clock supply means having the same timing, and skew measurement means 80,
The M distribution clock supply means separates and interrupts a plurality of M signals to be measured output from the DUT on the performance board PB on which the DUT is mounted, and calibrates the plurality of M sampling heads under the same timing condition. That supplies the clock of
The skew measuring means 80 supplies the clock for calibration to a plurality of M sampling heads, and specifies the skew ΔT between channels based on the waveform data of the clock for calibration acquired by each sampling head. Yes,
A method for correcting skew between channels of a multi-sampling digitizer for correcting skew between channels for a plurality of M-channel sampling digitizers having the above configuration and receiving a plurality of M signals to be measured from a DUT and performing sampling measurement,
Prior to actual measurement of the DUT, a skew measurement procedure for obtaining a channel skew ΔT between sampling digitizers of a plurality of M channels is provided.
In the actual measurement of the DUT, the variable delay means 16 for delaying the sampling clock incorporated in the sampling head unit of the sampling digitizer of a plurality of M channels based on the skew ΔT between channels obtained in the skew measurement procedure, A predetermined amount is subtracted or added from the delay set value (delay control signal 16c) set in the variable delay means 16 so that the inter-channel skew ΔT specified in step (c) is canceled, and is output from the DUT. A step of sampling and measuring each of the plurality of M signals to be measured and storing the signals in an acquisition memory;
The measurement data sequence of the plurality of channels acquired in the acquisition memory in the sampling measurement is read, and the measurement data sequence on the time axis of the acquisition memory is moved back and forth by software so that the skew ΔT between channels is equivalently canceled. A read processing procedure for converting the converted measurement data string to a subsequent data processing unit (not shown),
There is an inter-channel skew correction method for a multi-sampling digitizer which has the above and cancels the inter-channel skew.
[0019]
The means of the present invention may be practicable other constituent means by appropriately combining the respective element means in the above-mentioned solving means, if desired. Further, although the reference numerals given to the respective elements correspond to the reference numerals shown in the embodiments of the invention, the present invention is not limited to these, and other practical equivalents are applied. It is good.
[0020]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, an example of an embodiment to which the present invention is applied will be described with reference to the drawings. Further, the scope of the claims is not limited by the following description of the embodiments, and the elements, connection relationships, and the like described in the embodiments are not necessarily essential to the solution. Furthermore, the descriptions / forms of the elements, connection relations, and the like described in the embodiments are merely examples, and are not limited to the descriptions / forms.
[0021]
The present invention will be described below with reference to FIGS. The components corresponding to the conventional configuration are denoted by the same reference numerals, and the description of the components having the same reference numerals is omitted unless necessary.
[0022]
FIG. 4 is a conceptual configuration diagram of a two-channel sampling digitizer provided in the semiconductor test apparatus of the present invention. This component has a configuration in which a pulse generator PG, a cable CB5, a power splitter PS, switches SW1 and SW2, and a skew measuring unit 80 are added to the conventional configuration of FIG.
[0023]
The pulse generator PG receives a synchronous clock having a synchronous relationship with the reference clock Rclk from the clock source 40, and supplies a high-frequency calibration clock PGclk resulting from multiplication to a desired integer N times to the power splitter PS via the cable CB5. . It should be noted that the value of the integer N to be multiplied may be variable, and may be a value of N generated by a clock frequency near the output frequency of the DUT, or a fixed value of N may be applied.
[0024]
The power splitter PS is a two-way splitter, and is disposed on the performance board PB, receives the above-mentioned calibration clock PGclk, and distributes the same two at the same timing as distribution calibration clocks PSclk1 and PSclk2 corresponding to the switches SW1 and SW2. And supply it with equal length.
[0025]
The switches SW1 and SW2 are two-input and one-output high-frequency relays, and are disposed in an empty area on the performance board PB. The B contacts of the switches SW1 and SW2 are wired with equal length to the corresponding IC pins of the DUT, and the A contacts of the switches SW1 and SW2 are wired with equal length to the distribution calibration clocks PSclk1 and PSclk2. Therefore, the distribution calibration clocks PSclk1 and PSclk2 having the same amplitude can be supplied at the same timing on the performance board PB to the input ends of the sampling head units 101 and 102 of the sampler board 20. Therefore, calibration can be performed for the entire sampling system for the sampler board 20 including the transmission cables CB1 and CB2 and the digitizer 150.
As a result, at the time of calibration, the calibration at the present time can be performed based on the skew measuring means 80.
[0026]
The skew measuring means 80 measures the amount of skew between channels between the two sampling digitizers at the present time to obtain a correction amount. This measurement procedure will be described.
First, the switches SW1 and SW2 are switched and controlled, the calibration clock PGclk of a desired frequency is generated from the pulse generator PG, and the distribution calibration clocks PSclk1 and PSclk2 of the same amplitude are supplied to both transmission cables CB1 and CB2 at the same timing. Keep it.
Also, the same delay setting value is given to the delay control signal 16c supplied to both variable delay means 16 in the sampling head units 101 and 102 shown in FIG. For example, “0” is given as a delay amount.
Next, in the above state, a desired reference clock Rclk is generated from the clock source 40, sampling is performed, and continuous measurement data 31d, 32d obtained by quantizing conversion by both AD converters 31, 32 are respectively obtained. Are stored in the acquisition memories 51 and 52.
[0027]
FIG. 5A is a waveform in which time series data of both measured data 31d and 32d are plotted, and FIG. 5B is an example of a change in the skew ΔT between channels with respect to a delay set value.
In both waveforms acquired as shown in FIG. 5 (a), a rising position (see FIGS. 5A and 5B) at a voltage level of 特定 is specified, and a skew ΔT between channels between the specified two is obtained as a skew correction amount. . The obtained skew correction amount is stored in the system as the skew correction amount at the delay setting value.
FIG. 5B is a diagram in which the inter-channel skew ΔT obtained by measuring each of the delay setting values while sequentially changing the setting from 0 ns to 10 ns, for example, is plotted. A skew correction amount is obtained for each delay setting value in the same manner as described above, and stored in the system as a skew correction amount corresponding to each delay setting value.
[0028]
The update of the skew correction amount can be performed at any time when the system requires it. Even if a skew between channels (a change from FIG. 5C to FIG. 5D) occurs, the skew between channels can be practically eliminated by updating the skew correction amount at the present time. For example, in the related art, the skew between channels occurs around 100 ps, but in the present invention, the skew can be reduced to 10 ps or less. Therefore, a great advantage is obtained in that the DUT characteristics can be evaluated and determined in the best condition.
[0029]
Here, a description will be given of two types of correction methods in which actual DUT measurement is performed and a skew correction amount is applied.
The first correction method is a method in which a skew correction amount is subtracted from a delay set value (delay control signal 16c) provided to one variable delay means 16 to perform hardware correction. That is, at the time of actual measurement of the DUT, the skew correction amount corresponding to the delay setting value given to one of the variable delay means 16 is subtracted, and the subtraction result is supplied as the delay control signal 16c.
According to this, sampling can be performed in a state where the skew ΔT between channels has been eliminated.
[0030]
The second correction method is a method of moving a data sequence so as to perform software-based skew correction on a time axis. That is, both measurement signals S1a and S1b are measured under the condition of the same delay setting value without hardware correction, and stored in the acquisition memories 51 and 52. After the completion of the measurement, the stored measurement data is read out, and the data string of the measurement data is time-sequentially converted into time-series data of the skew correction amount corresponding to the delay setting value obtained by the calibration for one of the measurement data. Move on axis. Alternatively, read control is performed so that an address read from the acquisition memories 51 and 52 is accessed with an offset of an address amount corresponding to the skew correction amount.
According to this, both measurement data strings used by the subsequent data processing unit (not shown) are skew-corrected measurement data strings. Therefore, data processing in which the skew between channels is substantially canceled is realized.
[0031]
It should be noted that the technical idea of the present invention is not limited to the specific configuration examples and connection examples of the above-described embodiment. Further, based on the technical idea of the present invention, the above-described embodiment may be appropriately modified and widely applied.
For example, in the configuration example of FIG. 4 described above, a specific configuration example in which the sampling head units 101 and 102 have two channels has been described, but in the case of a large number of channels of two or more channels, or in the configuration of a plurality of sampler boards 20. Can be similarly applied as described above.
[0032]
Further, in the configuration example of FIG. 4 described above, the specific example including the dedicated pulse generator PG is used. However, the pulse generator PG is deleted, and the calibration clock is changed from the clock source 40 including the clock signal source of many channels. It may be configured to supply PGclk.
[0033]
【The invention's effect】
The present invention has the following effects based on the above description.
As described above, according to the present invention, the skew correction amount can be updated at any time when the system requires it. The skew between the channels caused by the change of the skew between the channels due to a change with time, board exchange, and the like can be practically eliminated. That is, it is possible to realize an inter-channel skew correction device for a plurality of sampling digitizers, which is capable of correcting the inter-channel skew between a plurality of sampling digitizers at any time while being incorporated in the system.
As a result, there is obtained a great advantage that the timing measurement between the two measurement signals S1a and S2a, and the characteristic evaluation and the judgment processing of the device test such as the phase and the group delay can be always performed satisfactorily with stable quality. Therefore, the technical effect of the present invention is great, and the industrial economic effect is also great.
[Brief description of the drawings]
FIG. 1 is a conceptual configuration diagram of a two-channel sampling digitizer provided in a conventional semiconductor test apparatus.
FIG. 2 is an example of an internal configuration of a sampling head unit.
FIG. 3 is a principle configuration diagram for explaining a conventional adjustment method for removing a skew between two-channel circuits in a sampler board.
FIG. 4 is a conceptual configuration diagram of a two-channel sampling digitizer provided in the semiconductor test apparatus of the present invention.
FIG. 5 is a diagram illustrating a waveform in which time series data of both measured data is plotted and a skew amount, and an inter-channel skew obtained by measuring each delay setting value while sequentially changing the setting from 0 ns to 10 ns, for example. It is the figure which plotted (DELTA) T.
[Explanation of symbols]
CB1, CB2 Transmission cables SW1, SW2 Switches TM1, TM2 Input end CB3 Transmission line CB5 with the same delay amount Cable 14 Pulser 16 Variable delay means (phase shift means)
Reference Signs List 20 sampler board 31, 32 AD converter 40 clock source 42 clock distributor 51, 52 acquisition memory 80 skew measuring means 101, 102 sampling head section 150 digitizer section DUT device under test PB performance board PG pulse generator PS power splitter SH sampling head

Claims (5)

A sampling digitizer of a plurality of M (M is an integer of 2 or more) channels receives a plurality of M high-speed repetitive signals (signals to be measured) output from a device under test (DUT) on a performance board and performs sampling at a predetermined timing. A plurality of M sampling heads for converting the waveform into a low-speed low-speed sampling waveform;
A clock source for generating and supplying a sampling reference clock Rclk to the sampling head unit;
A digitizer unit that receives the low-speed sampling waveform, performs a quantization conversion, and sequentially stores the waveform in a corresponding acquisition memory;
An inter-channel skew correction device for a multi-sampling digitizer that corrects inter-channel skew for a plurality of M-channel sampling digitizers that receive a plurality of M signals to be measured from a DUT and perform sampling measurement, comprising:
M distribution clock supply means having the same timing and skew measurement means,
The M distribution clock supply means separates and interrupts a plurality of M signals to be measured output from the DUT on the performance board on which the DUT is mounted, and supplies the plurality of M sampling heads with the same timing condition for calibration. Supply the clock,
The skew measuring means supplies the clock for calibration to a plurality of M sampling heads, and specifies an inter-channel skew ΔT based on a measurement data group obtained by sampling measurement at each sampling head. ,
A device for correcting skew between channels of a multiple sampling digitizer, comprising: The M distribution clock supply means includes a calibration pulse generator, a cable, a power splitter, and M switches,
The calibration pulse generator and the cable are arranged outside the performance board to generate a calibration clock for calibration, and supply the clock to the power splitter on the performance board via the cable.
The power splitter is a distributor capable of at least M distribution, receives a calibration clock from the pulse generator, and supplies M distributed calibration clocks having the same timing to M switches.
Each of the switches is a two-input, one-output high-frequency relay, which disconnects the signal under measurement of the DUT during calibration, and supplies the distributed calibration clock to the corresponding sampling head unit. An apparatus for correcting skew between channels of a multiple sampling digitizer according to claim 1. The skew measuring means measures a skew amount between channels between a plurality of M sampling digitizers to obtain a correction amount,
Means for generating a calibration clock of a predetermined frequency from the calibration pulse generator, switching the plurality of M switches, and supplying distributed calibration clocks of the same timing distributed to M to a corresponding plurality of M sampling head units; ,
Means for receiving the distributed calibration clock as an input signal at a plurality of M sampling heads, sampling and quantizing conversion, and storing the data in a corresponding acquisition memory as a group of measurement data so that the waveform of the input signal can be specified;
Means for reading out the stored plurality of M measurement data groups, specifying the waveform of the distribution calibration clock as an input signal, and calculating the inter-channel skew ΔT of each sampling digitizer from the waveform. Item 2. A device for correcting skew between channels of a multiple sampling digitizer according to Item 2. A sampling digitizer of a plurality of M channels receives a plurality of M high-speed repetitive signals (signals to be measured) output from a device under test (DUT) on a performance board, samples at a predetermined timing, and forms a low-speed low-speed sampling waveform. A plurality of M sampling heads for conversion;
A clock source for generating and supplying a sampling reference clock Rclk to the sampling head unit;
A digitizer unit that receives the low-speed sampling waveform, performs a quantization conversion, and sequentially stores the waveform in a corresponding acquisition memory;
M distribution clock supply means having the same timing and skew measurement means,
The M distribution clock supply means separates and interrupts each of a plurality of M signals to be measured output from the DUT on the performance board on which the DUT is mounted, and supplies the plurality of M sampling heads with the same timing condition for calibration. Supply the clock,
The skew measuring means supplies the clock for calibration to a plurality of M sampling heads and specifies the skew ΔT between channels based on the waveform data of the clock for calibration acquired by each sampling head. ,
A method for correcting skew between channels of a multi-sampling digitizer for correcting skew between channels for a plurality of M-channel sampling digitizers having the above configuration and receiving a plurality of M signals to be measured from a DUT and performing sampling measurement,
Prior to actual measurement of the DUT, a skew measurement procedure for obtaining an inter-channel skew ΔT between a plurality of M-channel sampling digitizers;
In the actual measurement of the DUT, the variable delay means for delaying the sampling clock incorporated in the sampling head of the sampling digitizer of a plurality of M channels based on the inter-channel skew ΔT obtained in the skew measurement procedure is described above. A procedure of subtracting or adding a predetermined amount to each of the delay setting values set in the variable delay means so that the specified inter-channel skew ΔT is cancelled, sampling each of them, and storing them in an acquisition memory;
A read processing procedure for reading a measurement data sequence of a plurality of channels acquired to the acquisition memory in the sampling measurement and supplying the read data sequence to a data processing unit in a subsequent stage,
A method for correcting skew between channels of a multiple sampling digitizer, comprising: A sampling digitizer of a plurality of M channels receives a plurality of M high-speed repetitive signals (signals to be measured) output from a device under test (DUT) on a performance board, samples at a predetermined timing, and forms a low-speed low-speed sampling waveform. A plurality of M sampling heads for conversion;
A clock source for generating and supplying a sampling reference clock Rclk to the sampling head unit;
A digitizer unit that receives the low-speed sampling waveform, performs a quantization conversion, and sequentially stores the waveform in a corresponding acquisition memory;
M distribution clock supply means having the same timing and skew measurement means,
The M distribution clock supply means separates and interrupts each of a plurality of M signals to be measured output from the DUT on the performance board on which the DUT is mounted, and supplies the plurality of M sampling heads with the same timing condition for calibration. Supply the clock,
The skew measuring means supplies the clock for calibration to a plurality of M sampling heads and specifies the skew ΔT between channels based on the waveform data of the clock for calibration acquired by each sampling head. ,
A method for correcting skew between channels of a multi-sampling digitizer for correcting skew between channels for a plurality of M-channel sampling digitizers having the above configuration and receiving a plurality of M signals to be measured from a DUT and performing sampling measurement,
Prior to actual measurement of the DUT, a skew measurement procedure for obtaining an inter-channel skew ΔT between a plurality of M-channel sampling digitizers;
In the actual measurement of the DUT, the variable delay means for delaying the sampling clock incorporated in the sampling head of the sampling digitizer of a plurality of M channels based on the inter-channel skew ΔT obtained in the skew measurement procedure is described above. A procedure of subtracting or adding a predetermined amount to each of the delay setting values set in the variable delay means so that the specified inter-channel skew ΔT is cancelled, sampling each of them, and storing them in an acquisition memory;
The measurement data sequence obtained by reading the measurement data sequence of the plurality of channels acquired to the acquisition memory in the sampling measurement and moving the measurement data sequence on the time axis of the acquisition memory back and forth so that the inter-channel skew ΔT is equivalently canceled. A read processing procedure for converting the converted measurement data string to a data processing unit at a subsequent stage;
A method for correcting skew between channels of a multiple sampling digitizer, comprising:

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