JPS59222952A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS59222952A JPS59222952A JP58097129A JP9712983A JPS59222952A JP S59222952 A JPS59222952 A JP S59222952A JP 58097129 A JP58097129 A JP 58097129A JP 9712983 A JP9712983 A JP 9712983A JP S59222952 A JPS59222952 A JP S59222952A
- Authority
- JP
- Japan
- Prior art keywords
- film
- metal film
- bonding pad
- semiconductor substrate
- wafer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 229910052751 metal Inorganic materials 0.000 claims abstract description 33
- 239000002184 metal Substances 0.000 claims abstract description 33
- 239000000758 substrate Substances 0.000 claims abstract description 20
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000010931 gold Substances 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 238000000034 method Methods 0.000 abstract description 5
- 229910052782 aluminium Inorganic materials 0.000 abstract description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 4
- 238000002161 passivation Methods 0.000 abstract description 4
- 229910052710 silicon Inorganic materials 0.000 abstract description 3
- 239000010703 silicon Substances 0.000 abstract description 3
- 238000005336 cracking Methods 0.000 abstract description 2
- 238000009792 diffusion process Methods 0.000 abstract description 2
- 230000002265 prevention Effects 0.000 abstract description 2
- 238000000059 patterning Methods 0.000 abstract 1
- 238000007669 thermal treatment Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000008188 pellet Substances 0.000 description 2
- 239000005360 phosphosilicate glass Substances 0.000 description 2
- 238000005086 pumping Methods 0.000 description 2
- 238000005452 bending Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000003923 scrap metal Substances 0.000 description 1
- 238000004804 winding Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4845—Details of ball bonds
- H01L2224/48451—Shape
- H01L2224/48453—Shape of the interface with the bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明はデンディングパッドを有する半導体装置に関
するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having a denting pad.
第１図および第２図は従来の半導体装置におけるポンデ
ィングパッド（ボンディング角取ｐ出し電極）の構造を
示したものである。図において、１１は所定の回路素子
等が形成された半導体基板で、この基板１ノ上に形成さ
れたフィールド酸化膜１２上に所定の回路部と接続した
例えばアルミニウムを主成分とする金属配管１３が形成
されている。図の１３ｂは、金属配線１３のポンプイン
グツぐラド部である。この金属配線１３の形成されたウ
ェハ１０の上面には？ンディングパッド１３ｂ上に開口
部１５を有する例えばＰＳＧ （リンシリケートガラス
）膜からなるノｅツシペーション膜１４が被着されてい
る。FIGS. 1 and 2 show the structure of a bonding pad (bonding square p-electrode) in a conventional semiconductor device. In the figure, reference numeral 11 denotes a semiconductor substrate on which predetermined circuit elements and the like are formed, and a metal pipe 13 mainly made of aluminum, for example, connected to a predetermined circuit portion on a field oxide film 12 formed on this substrate 1. is formed. Reference numeral 13b in the figure indicates a pumping radius portion of the metal wiring 13. What is on the upper surface of the wafer 10 on which the metal wiring 13 is formed? An ejection film 14 made of, for example, a PSG (phosphosilicate glass) film and having an opening 15 is deposited on the landing pad 13b.
第３図に示すようにこのようなポンディングパッド１３
ｂを有するＫｔ／ットは、リードフレームにマウントさ
れた後、リードフレームのリード部とポンディングワイ
ヤ１６を介し接続される。As shown in FIG.
After being mounted on a lead frame, the Kt/t having the number b is connected to the lead portion of the lead frame via a bonding wire 16.
ところで上記のようにポンディングノクツド１３ｂ上に
金線等のデンディングワイヤ１６を熱圧着する際にポン
ディングパッド１３ｂに衝撃が加わシ、？ンディングノ
クッド１３ｂ下のフィールド酸化膜１２に図のようにク
ラック１７が局部的に入ることがちシ、甚だしいときに
は半導体基板１ノにまでクラック１７が及ぶこともある
。By the way, as mentioned above, when bonding the bending wire 16 such as a gold wire onto the bonding pad 13b by thermocompression, an impact is applied to the bonding pad 13b. As shown in the figure, cracks 17 often occur locally in the field oxide film 12 under the semiconductor substrate 13b, and in severe cases, the cracks 17 may even extend to the semiconductor substrate 1.
このようにフィールド酸化膜１２にクラック１７が入る
と、本来は電気的に分離されるべき金層配線１３と半う
６体基板１１との間の絶縁性が低下し、リーク電流が流
れ、半導体素子の特（ＪＡ−が不良のものとなシ、製品
の歩留シが低下する欠点があった。When a crack 17 occurs in the field oxide film 12 in this way, the insulation between the gold layer wiring 13 and the semi-circular substrate 11, which should be electrically isolated, deteriorates, leakage current flows, and the semiconductor If the characteristics of the device (JA-) were poor, there was a drawback that the yield of the product would be reduced.
また、素子が不良となるに至らなくとも、長期間の使用
中に素子の特性が劣化するため、別品の信頼性が低下す
るという欠点もあった。Furthermore, even if the element does not become defective, the characteristics of the element deteriorate during long-term use, resulting in a reduction in the reliability of separate products.
この発明は上記のような点に鮭みなされたもので、ワイ
ヤボンディング工程における衝撃による素子の信頼性や
歩留シの低下が防止された半導体装置を提供しようとす
るものである。The present invention has been made based on the above-mentioned points, and is intended to provide a semiconductor device in which deterioration in device reliability and yield due to impact during the wire bonding process is prevented.
すなわちこの発明に係る半導体装置では、半導体基板の
ポンディングパッド領域にフィールド酸化膜等の第１絶
縁膜を介し、電気的に分離されたクラック阻止用の第１
金属膜を形成し、このクラック阻止用の第１金ｈ Ｊｌ
ｕ上に第２の絶縁膜を介して第２金属膜からなるポンデ
ィングパッドを形成したものである。That is, in the semiconductor device according to the present invention, a crack preventing first insulating film, which is electrically isolated from a first insulating film such as a field oxide film, is provided in a bonding pad region of a semiconductor substrate through a first insulating film such as a field oxide film.
First gold h Jl is used to form a metal film and prevent this cracking.
A bonding pad made of a second metal film is formed on the substrate u with a second insulating film interposed therebetween.
以下図面を参照してこの発明の一実施例につき製造過程
とともに説明する。まず、第４図に示すように、拡散層
等所定の各領域の形成された半導体基板２１上に第１フ
イールド酸化膜２２を約８０００Ｘの膜厚で形成し、そ
の上面にアルミニウムにシリコンを添加した部材からな
る第１金属膜２３を約８０００Ｘの膜厚で形成する。An embodiment of the present invention will be described below along with a manufacturing process with reference to the drawings. First, as shown in FIG. 4, a first field oxide film 22 with a thickness of about 8000X is formed on the semiconductor substrate 21 on which predetermined regions such as diffusion layers have been formed, and silicon is added to aluminum on the upper surface. The first metal film 23 made of the above-mentioned material is formed to have a thickness of about 8000X.
次いで、第５０に示すように写真蝕刻法によりｙｌ？ｌ
テンングパッド形成予定部に第１金属膜２３が残るよう
に１３０μ×１３０μの正方形に第１金属膜２３をパタ
ーニングする。次にプラズマ酸化膜２４をウェハ上面に
約１００００ Ｘの膜厚で形成する。Then, as shown in No. 50, yl? l
The first metal film 23 is patterned into a square of 130μ×130μ so that the first metal film 23 remains in the area where the tensing pad is to be formed. Next, a plasma oxide film 24 is formed on the upper surface of the wafer to a thickness of about 10,000×.
続いて、第６図に示すようにこのウエノ）全面にアルミ
ニウムにシリコンを添加した部材からなる第２金属月４
２５を租層形成し、ウエノ・の所定の部位と接続すると
ともに上記第１金Ｍ収２３の真上に１２０μ×１２０μ
の正方形状のがンディングパッド部２５ｂが位置するよ
うに上記第２金属脱２５をパターニングする。Next, as shown in FIG.
A layer of 120μ x 120μ is formed directly above the first gold layer 23 and connected to a predetermined portion of the metal layer 25.
The second metal strip 25 is patterned so that the square-shaped landing pad portion 25b is located.
次いで、第７図の断面図および第８図の平面図に示すよ
うにウェハ上にＰＳＧ膜からなる膜厚１２μのパッシベ
ーション膜２６を被着し、上記デンディングパッド２５
ｂ上のパッシベーション膜２６に１００μ×１００μの
正方形の開口部２７を設は第２金属膜２５を露出させる
。Next, as shown in the cross-sectional view of FIG. 7 and the plan view of FIG.
A square opening 27 of 100 μ x 100 μ is provided in the passivation film 26 on the passivation film 26 to expose the second metal film 25 .
この後、このウェハを４５０℃の炉内で３０分間のフォ
ーミング処理（熱処理）する。続いてこのウェハを所定
の半導体ペレット状に切シ出して、リードフレーム上に
マウントし、３０μφ（直径３０μｍ）の金線を用いて
ボンディングし、モールド樹脂でベレットを制止して製
品が完成する。Thereafter, this wafer is subjected to a forming treatment (heat treatment) for 30 minutes in a 450° C. furnace. Subsequently, this wafer is cut into a predetermined semiconductor pellet shape, mounted on a lead frame, bonded using a 30 μφ (diameter 30 μm) gold wire, and the pellet is restrained with a molding resin to complete the product.
なお、上記実施例におりる第１金属ｊ摸２３は、２層以
上の金属配線層を有する装置ではボンディング・フッド
を形成すべき最上店の金屑配線層以外の金属配線層で形
成すればよい。In addition, in the case of a device having two or more metal wiring layers, the first metal layer 23 in the above embodiment may be formed of a metal wiring layer other than the Mogami-ten scrap metal wiring layer that should form a bonding hood. good.
第９図には上記のようにして形成したボンディングパッ
ド２５ｂ合有する半導体装置にボンディングワイヤ１６
を接続した状態の断面図を示す。ここに示すようにワイ
ヤボンディング工程２４にクラック１７が入ったとして
も、下層に設けられた第１金属族２３によシフラック１
７の伸びが阻止され１．クラック１７が半導体基板２１
に遅することを防止できる。上記第２金ｐ５膜２５は配
線層や半導体領域とは接続されておらず電気的に分離さ
れているため、第２金属膜２５までクラックが達しても
？ンディングワイヤ１６と半導体基板２ノとがショート
する恐れもない。FIG. 9 shows a bonding wire 16 attached to a semiconductor device having a bonding pad 25b formed as described above.
A cross-sectional view of the connected state is shown. As shown here, even if a crack 17 occurs in the wire bonding process 24, the first metal group 23 provided in the lower layer will cause the shift rack 1 to
The elongation of 7 is prevented and 1. The crack 17 is the semiconductor substrate 21
This can prevent delays. Since the second gold P5 film 25 is not connected to the wiring layer or the semiconductor region and is electrically isolated, what happens if a crack reaches the second metal film 25? There is no fear of short-circuiting between the winding wire 16 and the semiconductor substrate 2.
ここで、本実施例の装置におけるポンディングパッドの
不良率を検査した結果、第２金爲膜２５と半導体基板２
ノとの電気的ショートの発生する確率は１″：）のポン
プイングツｅッド当シ０．０５チ程度であった。一方、
従来の装置では半導体基板とポンディングパッドのショ
ートの確率は１つのパＣンディングノぐラド当シ０．１
２％であシ、本発明によシ装置の歩留シおよび信頼性の
改善が図れることが確認できた。本発明の効果は特に多
ビンの半導体装置において著しいことが予想される。す
なわち、２０ビンの半導体装置と、１００ピンの半導体
装置の歩留シを予想すると下表のようになる。Here, as a result of inspecting the defective rate of the bonding pad in the device of this embodiment, it was found that the second gold film 25 and the semiconductor substrate 2
The probability of occurrence of an electrical short with the pump was about 0.05 when the pumping thread was 1":). On the other hand,
In conventional equipment, the probability of a short circuit between the semiconductor substrate and the bonding pad is 0.1 per bonding pad.
At 2%, it was confirmed that the present invention could improve the yield and reliability of the device. It is expected that the effects of the present invention will be particularly significant in multi-bin semiconductor devices. That is, the expected yield of a 20-bin semiconductor device and a 100-pin semiconductor device is as shown in the table below.
尚、上記実施例では第１金ＪｉＡＭがビンディングパッ
ドよシも広い正方形の場合につき述べたが、これは第１
金属膜とゲンディングパソドとが基板に対し水平方向に
略同じ外周部を有する略同−面積でもよい。しかしこの
場合には、第１金属膜のクラック阻止効果は第１金属膜
をピンディングツ々、ドよ）も広くした場合より劣る。In the above embodiment, the case where the first metal JiAM is square and wider than the binding pad is described;
The metal film and the ending pad may have substantially the same outer circumference in the horizontal direction with respect to the substrate and may have substantially the same area. However, in this case, the crack prevention effect of the first metal film is inferior to that in the case where the first metal film is pinned wider.
また、巣１金属膜の形状はポンディングパッドの形状と
同一で々くてもよい。Further, the shape of the nest 1 metal film may be the same as the shape of the bonding pad.
以上のようにこの発明によれば、ワイヤボンディング工
程時の術数によるショー） ｆｃ防止でき、装置の歩留
シおよび信頼性が改善された半導体装置を提供すること
ができる。As described above, according to the present invention, it is possible to provide a semiconductor device in which fc can be prevented during the wire bonding process and the yield and reliability of the device are improved.
第１図および２１５２図はそれぞれ従来の半導体装置に
おけるン］タンプイングツ々ッドを示す平面図および断
面図、第３図は従来の半導体装置のワイヤボンディング
状態を説明する断面図、第４図乃至第７図はこの発明の
一実施例に係る半導体装置を製造過程とともに示す断面
図、第８図は第７図の装置の平面図、第９区はこの発明
の一実施例に係る半導体装置のワイヤボンディング状態
を示す断面図である。
１６・・・デンディングワイヤ、２１・半導体基板、２
２・・・第１フイールド酸化膜（第１絶縁膜λ２″３・
・・第１金属膜、２４・・・プラズマ酸化膜（第２絶縁
膜）、２５・・・第２金属膜、２５ｂ・・・ビンディン
グパッド、２６・・・／Ｎ’ｌッシペーションｊ應。
出細入代理人 弁理士 鈴 江 武 彦第１図
第２図
第３図
第４図
１
第５図
１
第６図
１
第７図
７FIGS. 1 and 2152 are a plan view and a cross-sectional view showing a tamping tube in a conventional semiconductor device, respectively, FIG. 3 is a cross-sectional view illustrating a wire bonding state of a conventional semiconductor device, and FIGS. FIG. 7 is a cross-sectional view showing a semiconductor device according to an embodiment of the present invention along with the manufacturing process, FIG. 8 is a plan view of the device of FIG. 7, and section 9 shows wires of the semiconductor device according to an embodiment of the present invention. FIG. 3 is a cross-sectional view showing a bonding state. 16... Dending wire, 21. Semiconductor substrate, 2
2...First field oxide film (first insulating film λ2''3.
...First metal film, 24...Plasma oxide film (second insulating film), 25...Second metal film, 25b...Binding pad, 26.../N'l sipation. Issuing Agent Patent Attorney Takehiko Suzue Figure 1
Figure 2 Figure 3 Figure 4 Figure 1 Figure 5 1 Figure 6 1 Figure 7 7
Claims (2)
を介して形成され他の配謙層および半導体基板と電気的
に分離された８Ｉ！１金属膜と、この第１金属膜上の真
上に第２の絶縁膜を介し形成された第２金属膜からなる
ポンディングパッドとを具備することを特徴とする半導
体装置。(1) A semiconductor substrate, and an 8I! formed on the semiconductor substrate via a first insulating layer and electrically isolated from other wiring layers and the semiconductor substrate! 1. A semiconductor device comprising: a first metal film; and a bonding pad made of a second metal film formed directly above the first metal film with a second insulating film interposed therebetween.
ィングパッドの外周部よシも半導体基板に対し水平方向
外側にその外周部が存在することを特徴とする特許請求
の範囲第１項記載の半導体装置。(2) Claims characterized in that the outer periphery of the above-mentioned gold rot film exists horizontally outside the semiconductor substrate than the outer periphery of the binding pad formed directly above it. The semiconductor device according to item 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58097129A JPS59222952A (en) | 1983-06-01 | 1983-06-01 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58097129A JPS59222952A (en) | 1983-06-01 | 1983-06-01 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59222952A true JPS59222952A (en) | 1984-12-14 |
Family
ID=14183950
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58097129A Pending JPS59222952A (en) | 1983-06-01 | 1983-06-01 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59222952A (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03104247A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Wafer scale semiconductor device |
| JPH03131044A (en) * | 1989-10-17 | 1991-06-04 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH06204284A (en) * | 1993-01-08 | 1994-07-22 | Nec Yamagata Ltd | Semiconductor device |
| US6815322B2 (en) * | 2002-07-10 | 2004-11-09 | Renesas Technology Corp. | Fabrication method of semiconductor device |
| US7391114B2 (en) | 2004-02-05 | 2008-06-24 | Matsushita Electric Industrial Co., Ltd. | Electrode pad section for external connection |
-
1983
- 1983-06-01 JP JP58097129A patent/JPS59222952A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH03104247A (en) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | Wafer scale semiconductor device |
| JPH03131044A (en) * | 1989-10-17 | 1991-06-04 | Mitsubishi Electric Corp | Semiconductor device and manufacture thereof |
| JPH06204284A (en) * | 1993-01-08 | 1994-07-22 | Nec Yamagata Ltd | Semiconductor device |
| US6815322B2 (en) * | 2002-07-10 | 2004-11-09 | Renesas Technology Corp. | Fabrication method of semiconductor device |
| US6963513B2 (en) | 2002-07-10 | 2005-11-08 | Renesas Technology Corp. | Fabrication method of semiconductor device |
| US7391114B2 (en) | 2004-02-05 | 2008-06-24 | Matsushita Electric Industrial Co., Ltd. | Electrode pad section for external connection |
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