JPS59212954A - Program robbery preventing device for electronic circuit - Google Patents

Abstract

PURPOSE:To obtain an electronic circuit where the contents stored in a memory memory element cannot be extracted to outside by providing a buffer circuit at the input part of a terminal stage of a data bus within a microcomputer. CONSTITUTION:A CPU 3 sends the address signal to a terminal stage 1, an RAM 2 and an address recorder 4 and reads out a program of the RAM 2 to execute a read instruction. When the RAM 2 is chip-selected by the recorder 4 during execution of instruction, ''1'' is applied to an enable terminal G (inverse) of a bidirectional bus/buffer 6. Thus the A-B is turned off and no signal is delivered onto the data bus of the stage 1. When a memory excepting the RAM 2 is chip-selected by the recorder 4, ''0'' is applied to the DIR terminal of the buffer 6. Then the conduction is possible only to B from A, and no data is sent outside. It is impossible to set the memory read terminal RD (inverse) of the CPU 3 at L owing to the presence of a buffer 7 even though ''0'' is applied to a memory read terminal 1a in order to read intentionally a memory out of the stage 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a program theft prevention device in an electronic circuit for preventing computer program copying.

In recent years, microcomputers have become widespread, and their applications are wide-ranging. Microcomputers are widely used in everyday applications such as office automation, personal computers, and child game consoles. On the other hand, there have been a number of cases where microcomputer programs have been copied and used illegally, and this is currently being discussed as a social problem. Recently, however, there has been a trend to grant rights under copyright law to computer software as well.

However, as a practical matter, when software is copied and used, the substantial loss is immeasurable. Ultimately, it is necessary to take measures to prevent software from being copied.

An object of the present invention is to develop a countermeasure to prevent computer software from being copied in this way.

Conventionally, as a measure to prevent copying, there is a method of using an LSI (Large Scale Integrated Circuit) called a gate array or a logic array as a custom IC (a user's exclusive integrated circuit). However, this method is also made by combining multiple gate circuits, and the internal structure of this LSI can be decoded from input and output data. However, this method only takes a little longer to decipher, and is not logically impossible to decipher.

Taking the above points into consideration, the inventor constructed a buffer circuit at the input part of the terminal block of the data bus in the microcomputer, and provided a mechanism that prevents the contents stored in the memory element from being taken out. The present invention has been completed.

An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, and is a circuit diagram of a small-scale microcomputer, which is connected to an external circuit through a terminal block. , 2 is RAM,
3 is cpu (central processor unit)
, ri is an address decoder, E is a power supply, B1 is an address bus, and B2 is a data bus, and since these are the same as those of the conventional ones, detailed explanation thereof will be omitted.

In the present invention, a bidirectional bus buffer 6 is inserted into the input portion of the terminal block in the data bus B2.

For example, this bus pack aro is shown in Figure 2 (a), (b) (
What should MsL do with the logic diagram shown (inverted output type)? wtp/Mt
Lz, :zz7P (manufactured by Mitsubishi Electric Corporation) 5N7Q
4LS, :2Fj (manufactured by Texas Instruments)
.

MB74tLB2￥! (manufactured by Fujitsu Limited) has an enable terminal ■ and a direction terminal DIR as shown in the first diagram, and the terminal σ has an H or /
When a signal is input, it is disabled, that is, there is no conduction between AB. When L, that is, the θ signal, is input to the terminal terminal, conduction occurs between AB, but when the θ signal is input to the direction terminal DIR, conduction occurs only from A to B, and when the / signal is input to the direction terminal R, conduction occurs from B to A. conducts to. Note that when the memory read signal S is H (including when writing), the output signal f to the gate is H, and conduction to the bidirectional bus φ buffer is from B to A. When determining this direction, the bus request signal is always at H level.

It is inserted between the memory lead terminal /a of the terminal block / and the terminal n of the CPU 3 in such a direction that no signal is passed from the terminal block /, such as a buffer 7 such as an amplifier.

Bus request terminal /b of terminal block / is terminal B of 0PUj
Connect to USRQ, and the signal on this connection line is +! It is connected to the V power supply so that it is always at H, that is, the /@ signal level, and drops to the L or L O signal level only when the terminal /b is set to L.

The write terminal /C of the terminal block / is inputted to the terminal R/W of RAM 2 as a signal g via an inverter.0 When the address decoder is assigned to address θ for readout, the signal a output from the terminal yo is It becomes O.

The signals a and b are input to a gate j consisting of an input and negative AND circuit, and the output signal e thereof is input to an enable terminal of the bidirectional bus pack-allo.

The above signal f1.h is input to a gate consisting of a full-NOR circuit, and its output signal f1. (Input to the direction terminal DIR of the bidirectional bus buffer.

The above signal S and g are negated and inputted to the OR circuit 10, and the negated output signal C is negated together with the above signal a and inputted to the AND circuit //, and this output signal d is input to the chip select terminal surface of the RAM 2. input.

The signal g is input to the read/write terminal VW of the RAM 2.

Next, the operation of this device will be explained.

(1) The flow of data when the program is run.

The CPU 3 is activated by the signal of the clock pulse 3a during the dynamic f'fi.
passes the address signal through the address bus B1 to the terminal block/
, send to RAMJ and address decoder Hiro RAM, 2
If a program is contained in the CPU 3, the CPU 3 can read the contents through the data bus B2 and execute instructions. If RAM 2 is allocated to address 0θ, which is the memory address allocated by the address decoder Hiroshi, the program in RAM 2 will immediately run.

(la) During the above operation, RA is
When M and 2 are chip selected, that is, the output signal a of the address decoder Hiro's terminal yo (active, i.e. 0) and the signal b of the memory read terminal n of 0PU3 (active, L, i.e. O), or circuit l
The output signal C of O is O, and the output signal d of AND circuit // is 0
When the θ signal is input to the terminal surface of RAM 2, the signals a and b enter the gate j, and the output signal e (H,
That is, /) enters the enable terminal '5 of the bidirectional bus buffer. This terminal? When B+''-H, that is, /, the line between A and B of the bidirectional bus buffer B is turned off, so no signal is output on the data bus of the terminal block /.Therefore, even when GLOGSIM is running, 'RAM, data is never exposed to the outside world.

(1b> During the above operation, RA is
When a memory other than Mj is chip-selected, the output signal a of the address decoder becomes H, that is, /. Therefore, the output signal e of C)1 becomes L, that is, θ, regardless of the memory read signal S, and the θ signal is input to the enable terminal of bidirectional path buffer B. However, at that time, the memory read signal is L, that is, O (when reading)
Therefore, the output signal fIJ''-L of the gate becomes 0, the O signal is applied to the DIR terminal of the bidirectional bus buffer B, and the conduction of the bidirectional bus buffer G only goes from A to B. Therefore, the data is never exposed to the outside world.

(2) When you intentionally try to read the memory from the terminal block/, a forced KL or O signal is input to the memory lead terminal /a of the terminal block/, and the CPU It is not possible to set the signal of the memory lead terminal n of No. 3 to L.

Therefore, the signal S is H, and the output signal C of the OR circuit 10 is /
, the output signal d of the AND circuit // becomes /, so the RAM
Since the / signal is input to the terminal surface of 2 and no chip selection is performed, the data of RAM=2 will not appear externally. Therefore, the contents of the RAM 2 cannot be read out dynamically or statically by operation from the terminal block.

Note that when the buffer 7 is not present, when the memory read terminal n is forcibly set to L, the output signal f of the gate ♂ becomes L, and the direction determining terminal DIR of the bidirectional bus instruction buffer is set to L.

When this terminal DIR is at L, a bidirectional hash buffer that allows data to flow from A to B may be used.

゛(3)　Write to RAM2.

Next, RAM! Explain what happens when you input data into .

When the signal of the bus request terminal /b of the terminal block / is set to L, the address bus, data bus, and state control output signal of 0PU3 become high impedance state, and at the same time, the output signal f of the output becomes L, and the bidirectional bus is activated.・LK the buffer direction determining terminal 1) R. As mentioned in operation 7b above, this means that the bidirectional bus buffer has A
from to B. That is, data bus B2
conducts only from the outside to the inside.

- Then, when the address and data are sent from the terminal block / to the address bus B1 and data bus B2, and the signal H is input to the write terminal /C, the output signal g of the inverter becomes L, and the read/write terminal R of the RAM u /W to L.

That is, the data on the data bus is written to the RAM 2 at the specified address.

A method of writing a program into RAM from outside using RAM is as described above. Here, instead of using RhMk, it is quite possible to use a ROM in which a program has already been written.In this way, the effectiveness of the present invention is not limited by the type of memory O.

As is clear from the above, in the present invention, if the electronic circuit is sealed so that it can only be operated from the terminal of the terminal block, the contents of the memory cannot be read from the outside. For example, it enables the production of unreadable microcomputers, which is useful when applied to microcomputer applications such as electronic game machines, etc.
Its benefits are extremely great.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a microcomputer provided with a buffer circuit, and FIGS. 2(a) and 2(b) are logic diagrams specifically showing a bidirectional buffer. /...terminal block, B2...data bus, B...bus buffer circuit. 1 diagram, 2 diagrams (If

Claims (1)

[Claims] A program theft prevention device for an electronic circuit, characterized in that a buffer circuit is provided at the input part of a terminal block of a data bus in a microcomputer, thereby making it impossible to take out the contents stored in a storage element.