JPH0399346A - Semiconductor storage device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] An object of the present invention is to provide a semiconductor memory device that can prevent a third party from reading the memory contents and ensure the protection of information. A storage section that reads/writes data based on addresses to the memory to be stored, and a read section that outputs read/write strobe signals and address data to the storage section and controls reading/writing of data in the storage section. a write control circuit, an address processing means for processing designated address data to generate confidential address data in response to the generation timing of a read strobe signal in the read/write control circuit; and a read strobe signal in the storage section; and an address restoration means for returning the confidential address data generated to the original address data in response to the timing of occurrence of the address data.

[Industrial application field]

The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a function of preventing a third party from reading out stored contents.

With the development of microcomputers, their applications are increasing dramatically, not only in the communications industry but also in the consumer market. Additionally, since information handled by microcomputers is stored in memory, the scale of memory will expand in the future, and the issue of how to protect personal information in devices used for personal use (such as IC cards) has become an issue. .

[Conventional technology]

In a conventional semiconductor memory, when writing data, data is written by inputting write address data and a write strobe signal, and the data is stored at the input address.

On the other hand, at the time of reading, memory data at the input address is read by inputting address data to be read and a read strobe signal.

[Problem to be solved by the invention]

However, in such conventional semiconductor storage devices, the entire contents of the memory can be read by inputting address data sequentially, so this means that the contents of the memory cannot be read out by a third party. However, there was a problem in that there was a risk that copyrighted materials, such as microprograms, would be infringed.

Therefore, it is desirable to protect information.

On the other hand, as a conventional technique related to such countermeasures, for example, there is a "data encryption method" described in Japanese Patent Application Laid-open No. 152241/1983. In this method, in a multi-chip processor system, data encryption and decryption conversion tables are provided in microprograms, memory, and peripheral LSIs to encrypt information flowing on a data bus and protect software.

However, this method is only applicable to microprocessor systems, and it is not possible to completely protect personal information stored in individual memories, such as IC cards used for personal use. There is a demand for a semiconductor memory device that can independently protect the data.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor memory device that can reliably protect information by preventing a third party from reading the stored contents.

[Means to solve the problem]

In order to achieve the above, the semiconductor memory device according to the present invention includes a memory section in which data is read/written based on an address, and a read/write strobe signal and address data are output to the memory section. a read/write control circuit that controls read/write of data in the storage unit; and a read/write control circuit that processes specified address data to generate confidential address data in response to the timing of generation of a read strobe signal. Address processing means and address restoration means for returning the confidential address data generated in response to the generation timing of the read strobe signal to the original address data are provided in the storage section.

[Effect]

In the present invention, when reading data, specified address data is processed to generate confidential address data in response to the timing of generation of a read strobe signal, and then this confidential address data is converted into the original specified address data in the storage section. The data is returned and read externally. In this case, the third party can intervene only at the connection between the read/write control circuit and the storage unit, so the content of the address data that is different from the address data input by the third party is read in this part. analysis of the information becomes impossible.

Therefore, complete protection of memory contents can be achieved.

〔Example〕 Hereinafter, the present invention will be explained based on the drawings.

1 to 4 are diagrams showing an embodiment of a semiconductor memory device according to the present invention. FIG. 1 is a block diagram of a semiconductor memory device, and the semiconductor memory device shown in this figure is roughly divided into a memory section 1.
and a read/write control circuit 2.

First, the read/write control circuit 2 will be explained. The read/write control circuit 2 consists of a memory interface 3 and a first additional circuit 4. The first additional circuit 4 is newly added. Therefore, the memory interface 3 has exactly the same function as the conventional one, and the read strobe signal RD
, write strobe signal WR, control signal CNT
L, addresses Aφ to A11, and input/output data Dφ to D7 are output. The first additional circuit 4 has a function as address processing means, and is composed of a random number generator 5, a subtracter 6, and a selector 7. The operation of the random number generator 5 is controlled by the control signal CNTL, and generates random numbers in response to the generation timing of the read strobe signal RD, and the random number generation is programmable.

Here, the detailed configuration of the random number generator 5 is shown, for example, as shown in FIG.
The mask pattern is configured by the user and is user programmable, and the mask pattern is determined during the manufacturing process. Then, each D flip-flop circuit 8a to 8 is controlled by the control signal CNTL.
n is preset, and in response to the generation timing of the read strobe signal W), the D flip-flop circuits 8a to 8
n operates and outputs random numbers Rφ to Rfl.

The programming method is exclusive OR circuit 9a.
, 9b are connected to in the circuit.

Returning to FIG. 1 again, the output of the random number generator 5 is input to the subtracter 6, and the subtracter 6 performs an operation (address data processing) and outputs the result to the selector 7 as confidential address data. The selector 7 operates with an inverted signal of the write strobe signal WR (in other words, it operates entirely when the write strobe signal WR is not active), selects the operation result (confidential address data) from the subtracter 6, and stores it in the storage unit 1. send to Therefore, at the time of reading, the read designation address data is processed into confidential address data using random numbers and output to the storage unit 1. On the other hand, at the time of writing, the selector 7 selects normal write designation address data and sends it to the storage section l as it is.

Next, the storage unit 1 consists of a memory 11 and a second additional circuit 12, and this is a form in which the second additional circuit 12 is newly added to the memory 11, which corresponds to a conventional memory. It is something. Therefore, in Memo January 1, a large number of memory cells for storing data are arranged in a matrix in exactly the same way as in the past, and data is read/written by addressing. and addresses Aφ to A7 are input, and input/output data Dφ to Dfi are exchanged. Second
The additional circuit 12 has a function as address restoration means and is composed of a random number generator 13, an adder 14, and a selector 15. Random number generator 13 receives control signal CN
Its operation is controlled by the TL, and it generates random numbers similar to the random number generator 5 in response to the generation timing of the read strobe signal RD.The detailed circuit configuration is exactly the same as the random number generator 5. The control signal CNTL is used for random number generator 5 and random number generator 13.
The initial value of is set. The output of the random number generator 13 is input to the adder 14, and the adder 14 performs an operation of adding [random number] to the confidential address data output from the first additional circuit 4 at the time of reading (returning to designated address data). conduct,
The result (original designated address data) is sent to the selector 15.
Output to. Similar to the selector 7, the selector 15 operates with an inverted signal of the write strobe signal Wπ, selects the calculation result from the adder 14, and sends it to the memory 11. Therefore, when reading, the confidential address data is returned to the original specified address data and output to the memory 11, and when writing, the selector 15 selects the normal write specified address data and sends it to the memory 11 as it is. Furthermore, a control bus 16, an address bus 17, and a data bus 18 are connected between the storage unit 1 and the read/write control circuit 2, and only these connections can be controlled by a third party. There is.

Next, the effect will be explained.

This is the same as in the conventional case, and as shown in FIG. 3, where the data flow is shown by the hatched area, when the write strobe signal WR becomes active,
Both select normal designated address data, and data Dφ to D7 are written to all designated addresses in the same way as in the conventional case.

[Two Pupils] When the read strobe signal RD becomes active as shown in FIG. Select the result of 6 and add the second additional circuit 1
In step 2, the selector 15 selects the calculation result of the adder 14. As a result, the specified address data is processed to generate confidential address data, which is transmitted to the address bus 17.
The data is transmitted to the second additional circuit 12 through the second additional circuit 12, and the second additional circuit 12 returns the specified address data to the original designated address data, performs a read access to the memory 11, and reads out the data. In this case, a third party can intervene only in the control bus 16, address bus 17, and data bus 18, and even if the address is specified from the address bus 17 and read access is made to the storage unit 1,
In this part, reading will be performed based on confidential address data, so the contents of the address that is the sum of [input address] + [random number] will be read.
The memory contents obtained by a third party will be a completely "random" sequence of words, making analysis impossible.

Therefore, complete protection of memory contents can be achieved. As a result, unlike the technology described in the above-mentioned prior art publication, personal information can be completely protected for the IC card itself, which is used as a single memory, for example, for personal use.

Furthermore, since the random number generator 5.13 is programmable, it is possible to maintain confidentiality between memories containing additional circuits as described above, for example.

Note that processing into confidential address data may use a random number generator as in the above embodiment, but is not limited to this; for example, a counter may be used instead of a random number generator, or a multiplier/divider may be used. A combination may also be used.

〔Effect of the invention〕

According to the present invention, it is possible to prevent a third party from analyzing the stored contents, and it is possible to completely protect the information stored in the memory.

[Brief explanation of drawings]

1 to 4 are diagrams showing an embodiment of a semiconductor memory device according to the present invention, in which FIG. 1 is an overall configuration diagram thereof, FIG. 2 is a circuit diagram of its random number generator, and FIG. 3 is its data. FIG. 4 is a diagram explaining the operation when writing data, and FIG. 4 is a diagram explaining the operation when reading data. Engineering...Storage unit, 2...Read/write control circuit, 3...
・Memory interface, 4...First additional circuit, 5.13...Random number generator, 6...Subtractor, 7.15...Selector , 8a-8n...D flip-flop circuit, 9a
, 9b... Exclusive OR circuit, 11.
... Memory, 12 ... Second additional circuit, 14 ... Adder, 16 ... Control bus, 17 ... Address bus, 18...Data bus.

Claims (1)

[Scope of Claims] A storage section that reads/writes data based on addresses to a memory that stores data; and a storage section that outputs read/write strobe signals and address data to the storage section, a read/write control circuit for controlling read/write of the read/write control circuit; and an address processing means for processing designated address data to generate confidential address data in response to the generation timing of a read strobe signal in the read/write control circuit; A semiconductor memory device, characterized in that the storage section is provided with address recovery means for returning the confidential address data generated in response to the timing of generation of a read strobe signal to the original address data.