JPS59210600A - Error correcting circuit of memory system - Google Patents

Abstract

PURPOSE:To enable the correction of one defective memory element by providing an ECC circuit equal in number to the number of a multibit of memory element output, and connecting each memory element output to the ECC circuit for each different bit. CONSTITUTION:The ECC circuit is made to a polyhedron, and ECC circuits ECC0-3 equal in number with the number of multibit are provided, and different bit is connected to different ECC circuit. On receiving information bits a0-a15, inspection bits P0-Pk are prepared in an inspection bit preparing circuit 11, and an information bit 12 and an inspection bit 13 inputted and stored in a memory 14. Then, the presence of an erroneous bit and the designation of an erroneous bit are made by a composing device 15 using information bits a0'- a15' read out from the memory 14 and inspection bits P0'-Pk'. The erroneous bit is corrected by a correcting circuit 16, and correct information bits a0-an are sent out.

Description

[Detailed Description of the Invention] Memory using MO3 type LSI is increasing in chip capacity per chip at a rate of 4 times every 2.5 years, making it the second largest memory after IM pin/chip. It won't be long before elementary r- is realized. On the other hand, the rate of increase in memory system capacity is 2 to 3 (iW/2.5 years), which is smaller than the rapid increase in the number of bits in memory devices. )teeth,
It is unlikely that this will become very large in the future.

Under these circumstances, the problem is that when configuring a small expansion unit using large-capacity memory elements, a conventional 1-pin output memory element such as the 1Mth memory element does not have sufficient word depth. This is something that cannot be removed. For example, to configure a 2MB expansion unit with LM Focus/Chiap element r, 1
I only have 6 chimps in mind. Therefore, if the memory element has one-bin output, the word depth cannot be limited to a maximum of 16 hits, which is an inconvenience. In addition, in the current large i1't''l- machine, the word depth is approximately 64 hif+.
It is.

Therefore, in the future, it is thought that multivib, I-output (4-pin output in the figure) memory elements as shown in FIG. 2 will be used more frequently.

The memory element shown in Figure 1 is well known,
Figure 2 shows a generalization of this to insects. Next, each operation will be explained inside the cylinder. In the 1-bit output memory element 1 shown in FIG. Writing is performed to the memory cell 5 at the intersection of , and the contents are read to the output terminal 6.

Further, in the 4-bit output memory element 7 shown in FIG. 2, the bit decoder 8 is divided into four blocks. That is, the word line 9a selected by the word decoder 9
Writing is performed independently from the input terminals 2a to 2d to a total of four memory cells 9'a to 8'd at the intersections of the bit lines 8a to 8d selected for each block of the PIT decoder 8. is performed, and the contents of each memory element are output to output terminals 6a to 6d.

One major problem when using such multi-pin output memory devices is how to correct errors. In order to make the main memory of large computers that require large memory elements more resistant to failure, so-called error correction circuits (hereinafter referred to as E
CC circuit (ErrorCorrectingC4rcu
(abbreviated as ITS)). Figure 3 shows multi-pi)
As an example, a case is shown in which memory elements 10 for information bits MO to M15 each having a 4-bit output are added.

In other words, the test bits [*] are added to all bits (64 bits) that correspond to one word.

Here, MO to M15 are information bits, totaling 64 bits,
PMO to PMk are test bits. In this case, for example, the well-known S e C-
D' e D (Single-error Corr.
ction.

Double-error Detection)
When adding 1 function, 8 bits for checking are required for 64 bits of information, that is, =7.

However, when configured as shown in the r7+3 diagram, 4-bit output is output from one memory 10+τ, so IJ
If the memory element of IVi becomes defective, all four pins I will become an error, and there is a drawback that the error correction (SeC-DeD) shown in the bar becomes impossible in the ECc circuit 10.

In addition, in the commonly used 5eC-DeD error correction method, it is possible to detect and correct errors when 1 bit is defective, and only detect errors when 2 bits are defective. In the case of 3-bit defects, error detection is also impossible.

The present invention eliminates the above-mentioned drawbacks and provides a circuit configuration in which a 5eC-DeD function can be effectively applied by an E'CC circuit to a memory system using a multi-bit output memory element.

FIG. 4 shows that the memory shown in FIG.
An example in which a CC circuit is added is shown below. The main point of the invention is E
The feature is that the CC circuit is multifaceted, and the number of ECC circuits ECC0 to ECC3 is the same as the number of multi-bits (4 bits in Figure 4), and the different bits of each memory element are connected to different ECC circuits. shall be. That is, in the case of the figure, among the outputs of each memory element, a, to δ2. and p.

~PA is ECC0, b, Nb, and q, ~q4
is in ECC1, c, ~c and r, ~rx are in EC
C2+5, d, ~d,5 and So ~SA are connected to ECC5, respectively. With such a configuration, even if one memory element becomes defective, it is a 1-bit error in each ECC circuit and can be corrected. Note that instead of providing four ECC circuits as shown in Figure 4, I JIVA's E
CC circuits can also be used in a time-division manner.

Here, in the configuration shown in FIG. 3, there is one ECC circuit, but
This is an error correction circuit for input (64 pins). On the other hand, there are four ECC circuits in Figure 4, but these are 16-bit input error correction circuits, so each ECC circuit has four ECC circuits.
The number of elements used in the CC circuit is small. On the other hand, time-sharing ECC
If a circuit is used, only one 16-bit input ECC circuit is required, which has the advantage of greatly reducing the number of elements used in the ECC circuit. However, since one word is divided into four times and processed, the processing speed for one word becomes 1/4 times slower. Therefore, this time-sharing method is suitable for low-speed and inexpensive memory systems.

ECC circuit used in the present invention, 4. ■5eC-DeD
is already well known, and its outline is shown in FIG. This figure is a configuration diagram of an ECC circuit, for example, ECC0 in FIG. 4, and information bit a. - Inspect the code by hp
"p" is created.In addition, in FIG. 4 above, for simplicity, this test bit creation IiU
Route 11 has been omitted. Then the information pick)・12(aO
~aIs) and test pill □ 13 (p, ~p,)
is input to the memory 14 and stored. When reading, the information bits aA to aI' read from the memory 14
Using f and check bits p to p', the decoder 15 specifies the presence or absence of an error bit from θ k and, if there is an error bit, which bit is the error bit.

If there is an erroneous bit, the erroneous bit correction circuit 1G corrects the error and sends out correct information bits l=a, ~a.

As explained above, the present invention provides a memory configured using memory elements with multi-bit output, and an ECC circuit for the multi-bit number and number of outputs of the memory element, which performs ECC on each memory element output for each different bit. It is connected to a circuit. By doing this, if one chip is damaged and an error occurs in all the multiple outputs of one memory element, in the conventional configuration 'f' is written and the multiple outputs are added to one ECC circuit. On the other hand, in the configuration of the present invention, since the multiple outputs are distributed, it is possible to detect an error without any abnormality even if only one bit becomes defective in one ECC circuit. , the effect is great.

412! 1 tni 1 diagram Figure 1 and 2 are explanatory diagrams showing memory elements with 1-bit output and multi-pinpoint output, respectively. Figure 3 shows errors in memory using memory elements with multi-bit output. FIG. 5 is a block diagram showing a conventional configuration in which a correction circuit is added, FIG. 54 is a block diagram showing an embodiment of the present invention, and FIG. 5 is a block diagram showing an example of an error correction circuit.

MO~M15. PMO to PMk...Multi-pinto output memory; Niko, ECC0 to ECC5...Error correction circuit.

Claims (1)

[Claims] Error correction in a memory system configured using a plurality of memory elements having a plurality of information focus output terminals, characterized in that an error correction circuit is provided for each information bit of the memory element as described in -. circuit.