JP2930239B2 - Storage device failure detection method and storage control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for detecting a failure in a storage device and a storage control device, and more particularly to a failure detection method suitable for detecting an address failure in a storage device using an error correction code. And a storage control device.

[Conventional technology]

Conventionally, as a method of detecting an address failure of a storage device, for example, as described in Japanese Patent Application Laid-Open No. 52-2224, address information is assigned to a redundant portion of an error correction code error location indicating capability (data and data). There is known a method for detecting a mismatch between a write address and a read address by encoding / decoding the data. Japanese Patent Application Laid-Open No. 57-71599 discloses a method of allocating redundant bits of the error location indication capability to a divided address unit for a storage device in which an address is divided and input in a plurality of times. It has been disclosed.

[Problems to be solved by the invention]

According to the above-mentioned conventional technique, when address information is assigned to a plurality of redundant bits and an error occurs in the plurality of bits due to an address fault, the fault is not identified as a data error, and if worse, the data is erroneously corrected. there is a possibility. For example, in the method described in Japanese Patent Application Laid-Open No. 57-71599, when redundant bits are assigned to an address unit that is time-divisionally input twice to a storage device using a 1-bit error correction / 2-bit error detection code, When a one-bit failure occurs in the time-division input address path, a two-bit error may occur, and the failure can be detected. However, in general, it is not possible to identify a two-bit error in data, and it is difficult to specify a failed part. Even when a 1-bit error correction / 2-bit error detection code is used, a detected address error can be identified as a data error by allocating only one redundant bit for an address. Is less likely to be embodied as an address error. For example, if one redundant bit is assigned to the parity set of all addresses, when the number of mismatched address bits at the time of writing and at the time of reading caused by an address failure is an odd number, it appears as an address error. Not be.

An object of the present invention is to assign address information to a plurality of redundant bits of the error location indication capability of an error correction code, and to detect a failure in a storage device and detect any address error without being confused with a data error. It is to provide a control device.

[Means for solving the problem]

The storage device failure detection method of the present invention uses a single-byte error correction / double-byte error detection code that enables error correction in a plurality of bits (this plurality of bits is referred to as a byte). And assigning information such as a write address or an address parity generated from the address to a specific single byte in the redundant portion of the error byte position indicating capability of the code (these are collectively referred to as address information). A parity check matrix is configured to detect and detect an address failure of the storage device by identifying single and double byte errors in other data.

Further, the storage control device of the present invention has a
Means for generating check bits from write data and write address information based on a parity check matrix in which address information is assigned to a specific single byte in a redundant portion of the error byte position indicating capability of the double byte error detection code; Means for writing the generated check bits together with the write data to a location specified by the write address of the storage device; means for reading data and check bits from the location specified by the read address of the storage device; Means for generating a syndrome based on a parity check matrix similar to the above from the check bits and the read address information, and decoding the syndrome and determining that there is an error in a byte position assigned to the address information of the parity check matrix. Has a means for detecting a storage device address failure. To.

(Operation)

In single byte error correction / double byte error detection code,
Single byte errors can be distinguished from other single and double byte errors. Also, since the bits assigned to the address information are confined within a single byte of the code, any address error will only appear as an error in the single byte assigned to the address information. Thus, any address error can be distinguished from single and double byte errors in other data.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2.

FIG. 1 is a block diagram showing an entire configuration of an embodiment of a storage control device according to the present invention.
0, a storage device 30, a syndrome generator 40, a syndrome decoder 50, and an error corrector 60.

The operation of FIG. 1 is as follows. At the time of writing, when the write data 11 and the address 15 are given by the central processing unit or the like, the check bit generator 20
A check bit 22 is generated from the address 15 at the time of writing based on a predetermined parity check matrix described later, and the generated check bit 22 and the write data 11 are stored in the storage device.
It is written to the location specified by address 15 in 30. At the time of reading, when an address 15 is given, the read data 31 and the read check bit 32 are read from the portion of the storage device 30 specified by the address 15 and input to the syndrome generator 40 together with the address 115 at the time of reading. Is done. The syndrome generator 40 generates a syndrome 43 from the read data 31, the read check bits 32, and the address 15 based on a predetermined parity check matrix, and inputs the syndrome 43 to the syndrome decoder 50. Syndrome Decryptor 50
Then, the syndrome 43 is decoded based on a predetermined parity check matrix, and the error pointer 54 and the error detection signals 56 and 5 are decoded.
Generate 7,58. The error detection signals 56, 57, 58 indicate a correctable data error, an uncorrectable data error, and an address error, respectively. The error corrector 60 inverts a predetermined bit of the read data 31 based on the error pointer 54, and outputs corrected data 61.

Next, detection of an address failure of the storage device 30 according to the present invention will be described in detail.

FIG. 2 shows the data length assuming that 4 bits are 1 byte.
8 shows a parity check matrix of a single-byte error correction / double-byte error detection code suitable for use in the present embodiment when 8 bytes (32 bits) are used. The information length of the modified Reed-Solomon code known as a double byte error detection code is set to 8 bytes for data (D ₀
To D ₇ ) and 1 byte for address (A), that is, 9 bytes in total. In the figure, the symbol I is the unit matrix of 4 × 4, T and T ⁱ is a so-called Galois field GF (12 ⁴⁾
It shows the entrainment matrix of the above atomic length and its power matrix.

On the basis of the parity check matrix shown in FIG. 2, the check bit generator 20 outputs D ₀ to D ₇ (4
From the information A within 4 bits generated from the write address 15 and the write address 15, check bits C ₀ , C ₁ , and C ₂ (4 bits each) are generated as follows according to the arithmetic rules on GF (2). Is done.

C ₀ = D ₀ · I + D ₁ · I + D ₂ · I + D ₃ · I + D ₄ · I + D ₅ · I + D ₆ · I + D ₇ · I + A · I C ₁ = D ₀ · I + D ₁ · T + D ₂ · T ² + D ₃ · T ^{3 _{+ D 4 · T 4 + D}} 5 · T 5 + D 6 · T 6 + D 7 · T 7 + A · T 8 C 2 = D 0 · I + D 1 · T 2 + D 2 · T 4 + D 3 · T 6 + D 4 · T 8 + D ₅ · T ¹⁰ + D ₆ · T ¹² + D ₇ · T ¹⁴ + A · T In the syndrome generator 40, D ₀ ′ to D ₇ ′ (4 bits each) of the read data 31 and the read check bit 32
C ₀ ′, C ₁ ′, C ₂ ′ (4 bits each) and read address 15
From the information A 'within 4 bits generated from, the syndromes S ₀ , S ₁ , S ₂ (each 4 bits) are generated as follows according to the arithmetic rules on GF (2).

_{S 0 = D 0 '· I} + D 1' · I + D 2 '· I + D 3' · I + D 4 '· I + D 5' · I + D 6 '· I + D 7' · I + A · I + C ₀ ′ · IS ₁ = D ₀ ′ · I + D ₁ ′ · T + D ₂ ′ · T ² + D ₃ ′ · T ³ + D ₄ ′ · T
^{_{4 + D 5 '· T 5}} + D 6' · T 6 + D 7 '· T 7 + A' · T 8 + C 1 '· IS 2 = D 0' · I + D 1 '· T 2 + D ^{_{2 '· T 4 + D 3}} ' · T 6 + D 4 '·
T ⁸ + D ₅ ′ · T ¹⁰ + D ₆ ′ · T ¹² + D ₇ ′ · T ¹⁴ + A ′ · T + C ₂ ′ · I In the syndrome decoder 50, between the syndromes S ₀ , S ₁ , and S ₂ When the following two relationships are established, the address error detection signal
Outputs 58.

S ₁ = S ₀ · T ⁸ S ₂ = S ₀ · T Next, there are some effective methods for creating address information A and A ′ within 4 bits allocated to the parity check matrix from the write and read addresses. The various methods are shown below. However, it goes without saying that the present invention is not limited to this.

(1) The parity bit of the address sent from the central processing unit or the like is used as it is. For example, if the address length is
If a parity bit is attached every 8 bits in 32 bits, the address parity bit becomes 4 bits and can be used as it is as the address information of the parity check matrix.

(2) Grouping is performed according to how addresses are used in the storage device, and a parity signal for each group, that is, a signal obtained by taking an exclusive OR of all bits in each group is used as address information. As a method of grouping, for example, an address directly supplied to a memory element,
Select a memory element. (Chip Select or Card Select) Dynamic RAM
It is useful to divide the address into units of time-division-transferred addresses such as the row address and the column address, and to divide the addresses input to and output from the same IC / LSI into different groups.

If the generated address information A is less than 4 bits, an unallocated bit occurs in the byte. However, this bit may be always considered to be "0", and does not hinder the realization of the present invention.

In the above embodiment, an example in which the byte length is 4 bits and the data length is 8 bytes is shown, but the present invention is not limited to this, and can be applied to any byte length and data length. Byte length 4 bits, data length considered to be useful in practice
Even in the case of 16 bytes and 32 bytes, the existence of a code having a code length capable of allocating address information without increasing the number of check bits exists.
5, Number 7 (1986) 646-648 (IEEE.Tra
ns. Computers, C-35, No. 7, July, 1986, pp. 646-648).

As described above, according to the present embodiment, in a storage device using an error correction code, it is possible to detect an address failure of the storage device and identify a data error without increasing the number of check bits.

〔The invention's effect〕

As is apparent from the above description, according to the present invention, a single-byte error correction / double-byte error detection code that enables error correction in a unit of a plurality of bits (bytes) is used, and
By confining the address information in a specific single byte in the redundant portion of the error byte position indicating capability in the code, an address error can be detected without being confused with a data error. And the like, and therefore, there is an effect that trouble handling is also facilitated. When address parity is used for confined address information, these effects can be realized without increasing the number of check bits. Further, the above effects can be realized without capturing an address failure or the like, that is, without reducing the possibility that the address failure is embodied as an address error.

[Brief description of the drawings]

FIG. 1 is a diagram showing an overall configuration of an embodiment of a storage control device according to the present invention, and FIG. 2 is a diagram showing one column of a parity check matrix suitable for use in the failure detection method of the present invention. 20 ... check bit generator, 30 ... storage device, 40 ... syndrome generator, 50 ... syndrome decoder, 60 ... error corrector.

Claims (3)

(57) [Claims] 1. A failure detection method for a storage device using a single-byte error correction / double-byte error detection code which enables error correction in a unit of a plurality of bits (hereinafter referred to as a byte). Address information is assigned to a specific single byte in the redundant portion of the single byte error correction / double byte error detection code error byte position indicating capability to form a parity check matrix. At the time of writing, write data and write address information By
Check pits are generated in accordance with the parity check matrix, and the generated check pits are added to the write data and written to the storage device. At the time of reading, the data read from the storage device and the check pits, and the read address information, A syndrome is generated according to the parity check matrix, and the syndrome is decoded. If there is an error in a byte position assigned to the address information of the parity check matrix, it is recognized as an address failure of the storage device. And detecting a single byte error and a double byte error of the data. 2. A method according to claim 1, wherein a Reed-Solomon code is used as a single-byte error correction / double-byte error detection code, and the error byte position indication capability of the code is included in a redundant portion. A parity check matrix is composed of the address information assigned to a specific single byte as a write address and a parity bit of a read address. A check bit is generated by write data and a parity pit of the write address at the time of writing, and read data is checked at the time of reading. A method for detecting a failure in a storage device, wherein a syndrome is generated from a pit and a parity bit of a read address. 3. A storage control device for controlling writing and reading of a storage device, wherein address information is stored in a specific single byte in a redundant portion of an error byte position indication capability of a single byte error correction / double byte error detection code. Means for generating a check bit from write data and write address information based on the allocated parity check matrix; and adding the generated check bit to the write data and writing the check bit to a location specified by the write address of the storage device. Means for reading data and a check bit from a portion designated by a read address of the storage device; and a means for reading a single byte error correction / double byte error detection code in a redundant portion of an error byte position indicating capability. Based on a parity check matrix in which address information is assigned to one byte, the read data and check bit, and Means for generating a syndrome based on the read address information; and decoding the syndrome, and if there is an error in a byte position assigned to the address information of the parity check matrix,
A storage control device having means for detecting an address failure of a storage device.