JPS59197167A - solid-state image sensor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application This invention relates to a solid-state imaging device made of a bulk type COD or the like.

BACKGROUND TECHNOLOGY AND PROBLEMS Among the solid-state imaging devices (for example, bulk type CCI) whose light-receiving region (sensor region) is a PN junction, overflow drain OFDs that suppress blooming have recently been developed to effectively utilize the device surface. It has been proposed to arrange the substrate not in a two-dimensional manner but in a three-dimensional manner, that is, in the depth direction of the base.

FIG. 1 shows an example of this, and is a cross-sectional view of a normal interline transfer type solid-state imaging device αα along a plane perpendicular to the signal transfer. In this figure, a bulk channel (
An N type region (2) for forming a buried channel) and a P+ type region (3) for a channel stopper cS are formed, and a region (2) is formed between these regions (2) and (3).
3) N+ region 4 which becomes sensor region 8ENS in contact with
) is formed. This region (4) and the base (1) form a PN junction JS for the sensor.

A transfer electrode (force) for the vertical shift register VR is formed on the upper surface of the substrate (1) via an insulating layer (6) such as 8i02. This area is used as a read control gate CG area.

An N-type region (8) of a conductivity type different from that of the P-type substrate (11) is formed on the lower surface of the P-type substrate (11).
) and the region (8) form a control gate region for the overflow drain OFD. Therefore, a predetermined reverse bias is applied to this PN junction Jo from the outside. vB is the bias source.

According to this configuration, when the optical signal charge based on the optical signal incident on the sensor region 5ENS exceeds the potential barrier formed by the PN junction JQ, the excess optical signal charge is of the N type. It is released into region (8) to suppress pluming.

In this way, if the overflow drain OFD is arranged three-dimensionally, the device surface can be used effectively. However, since this configuration requires double bonding, the overflow control gate (rear P-type substrate) is It becomes difficult to control the concentration of (1), as well as the depth XJ of this P-type substrate (1) from the PN junction surface JS, which causes manufacturing problems.

OBJECTS OF THE INVENTION Therefore, the present invention proposes a solid-state image sensing device that can effectively utilize the device surface and is easy to manufacture.

Summary of the Invention Therefore, in this invention, the sensor region has an MO8 configuration, and a vertical overflow drain region is formed in this sensor region. A conductivity type channel stop region and an island region are provided, a − conductivity type transfer region is provided in the island region, a light receiving region of another conductivity type is provided between the island region and the channel stop region, and an insulating region is provided on the light receiving region. The above object is achieved by keeping the light-receiving electrode provided through the membrane and the substrate at the same potential, and making this potential different between the light-receiving period and the read-out period.

Specific Example Next, an example of the present invention will be explained in detail with reference to FIG.

In this example, a base (1) of negative conductivity type, for example, N- type, is used, and on the upper surface side of this base body (1), another conductivity type for channel stopper C8, that is, P A type region (lυ) is formed, and a part between these type regions (Ill) is an island region with a relatively high concentration that becomes a P-type potential well. Therefore, in this example, a P-type island region (12
1 is formed. This island region (N-type region for the bulk channel that constitutes the vertical shift register VB within 12+
13) is formed.

The island area (12) and the area for channel stopper C8 (L
A P-type region circle that is easily depleted is formed between the
Furthermore, a transparent electrode (19) is formed on the entire surface of this base (1) through an insulating layer (6) such as SiO2. ) constitutes a sensor region 5ENS with an MO8 configuration.On the surface of the N-type region 00, there is a transfer layer made of polysilicon or the like for the screen shift register VB between the above-mentioned insulating layer (6) and the transparent electrode (1ω). An electrode (7) is formed spanning the P-type region (1) and the P-type region (111).

Note that each of the above-mentioned regions αυ to I can be formed using ion implantation or diffusion techniques.

A predetermined potential VG, which is different between the light reception period and the readout period, is commonly applied to the transparent electrode a2 and the substrate (1) as a sensor control signal. Reference numeral (17) is a pulse supply source for obtaining this predetermined potential, and from now on, as shown in FIG. 3A, a control pulse PC is outputted which is at a high level during the light reception period and at a low level during the readout period. In addition, the region for the channel stopper C8 (1υ and the island region circle are fixed at zero potential. During the light reception period.

In the middle, the transfer pulse PT shown in FIG. 3B is supplied to the transfer electrode (power). Therefore, this example is an example of two-phase drive.

Now, when configured in this way, on line I-I to I-1
Figure 4 shows the potential of each part on the line. In this figure, the horizontal direction is the depth direction of the base (11), and the potential of each part is illustrated with reference to the zero potential in the base Ill.

A and D in the figure are potentials on the l-1 line perpendicular to the sensor region 8BNS, and thus to the plane of the PN junction JPN. Of these, Figure A shows the change in potential during the light reception period, and Figure A shows the change in potential during the readout period.

During the light reception period, a high level control potential VGH is applied to the transparent electrode (15) and the substrate (1), so before light reception, the potential is as shown by the curve Qa,
After receiving light, it changes like a curved sieve. Maximum point φFC is PN
This is caused by the contact potential difference due to the junction JPN. When an optical signal enters the sensor region 8DNS and is photoelectrically converted, the potential on the substrate surface is lowered to a potential like the song 'iIMQC. When the optical signal charge amount Qs increases, the potential becomes like a curve Qc.

Here, the curve Qb shows the potential when the optical signal charge amount Qs is removed just before it overflows, and the maximum point φ at this time. The maximum optical signal charge amount Q that overflows due to
SM is determined.

Since the maximum point φFC is determined by the concentration of the P-type region circle and the depth of this region I, the maximum amount of charge that can be handled is determined by these factors.

When the amount of optical signal charge Qs exceeds QSM, the potential at that time exceeds the maximum point φMe at the time of light reception, so excess optical signal charge is released into the bulk and blooming is suppressed. Therefore, the potential barrier at this maximum point φFC becomes an overflow control gate.

In addition, bribery. is the potential directly below the insulating layer (6) in the readout control gate CG, and the control potential VGHO value is selected so that the maximum point φ'FC does not exceed this potential axis 0 during light reception. The fourth diagram shows the change in potential during readout. A predetermined low potential VGL is applied to the transparent electrode (7), and at the potential (curve Qd) formed by this, the sensor area 5ENS The surface potential is
The level of the potential VGL is selected so that at least the control game (CG) exceeds the surface potential φRO.

FIG. 4B shows the potential relationship at the readout control potential (CG) on the n-n' string in FIG. 2, which changes depending on the potential φ7 of the transfer pulse PT. 2
In the case of phase drive, the potential φVH of the transfer voltage (the first half of the pulse PT is the accumulation period, the second half is assigned to the transfer period, and the accumulation period is) and level is added, and the potential at that time becomes like the curve eh. , during the transfer period, a low level potential φVL is applied, and the potential at that time is curved 9
It will be like this again. The potential φ8 during the storage period is equal to the potential φRO during readout.

In addition, Figure 4C shows the change in potential at the vertical shift register VR on the line -■ in Figure 2.
Curve ε11 shows the potential during the accumulation period, and curve 0
y indicates the potential during the transfer period.

During the optical signal charge readout period, a high potential φ is applied to the transfer electrode (7).
While VH is applied, a low potential ■ is applied to the transparent electrode Uω.

L is added. Due to the low potential vGL, the potential in the sensor region 5ENS is made to exceed the potential φRO on the substrate surface as shown in the second diagram, so that the optical signal charge in the sensor region 5EN8 is transmitted via the control gate CG. Transferred to vertical shift register ■R. After the charge transfer, VG is controlled to VGH and a light reception period begins, and vertical transfer is performed by a transfer pulse PT applied to the transfer electrode (FIG. 4B, C).

During the light reception period, the maximum potential point φFC of the sensor region 8ENS is always higher than the surface potential φ8 of the readout control gate CG, so the optical signal charge is transferred to the vertical shift register VYL via the control gate CG.
It does not flow into.

In this way, in the configuration shown in FIG. 2, when the optical signal charge overflows, all the excess optical signal charge is diffused into the node, forming a vertical overflow drain. By using a mold overflow drain, the device surface can be used effectively and the device can be manufactured easily.

That is, according to the configuration of FIG. 2, the sensor area 8ENS
Since the corresponding substrate (1) has a two-layer structure, there is no need to form an N-type region (4) as shown in FIG. For this purpose, the concentration of the P-type substrate (1) shown in FIG.
depth control becomes unnecessary. For these reasons, when the structure is as shown in FIG. 2, the device can be manufactured much more easily than the structure shown in FIG.

In addition, with a vertical overflow drain structure as shown in Fig. 1, when reading optical signal charges, the optical signal charges cannot be read out unless the transfer pulse PT has three levels. According to the invention, the potential at the maximum point φFC, which is the overflow control point, changes depending on the potential VQ applied to the transparent electrode μ9, as shown in FIGS. 2A and D. The PT has a binary level of high or low, and the optical signal charge can be read out.Therefore, the means for forming the transfer pulse PT is simple and inexpensive.

In addition, when considering interlaced scanning, as shown in the fourth diagram, when applying the low potential VGL, the silicon substrate (
The level of this low potential VGL may be set so that a depletion layer remains on the surface of 1). Further, instead of a pulse signal source (force), a predetermined DC voltage may be applied, and in this case, a three-level clock may be used as the transfer pulse PT.

The present invention relates to a solid-state image sensor having a light receiving section and a storage section, in which the light receiving section uses an interline transfer method and the storage section uses a field or frame transfer method. It can also be applied to an image sensor.

DETAILED DESCRIPTION OF THE INVENTION As described in detail, according to the present invention, it is possible to provide a solid-state image pickup device having a vertical overflow drain configuration that can effectively utilize the device surface and is easy to manufacture.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view showing an example of a conventional solid-state image sensor;
The figure is a cross-sectional view showing an example of a solid-state image sensor according to the present invention.
3 and 4 are diagrams for explaining the operation. (11 is the base, (121 is the island region, C3) is the N-type region for the bulk channel, the circle is the N-type region for forming the sensor region, VR is the vertical shift register, C8 is the channel stopper, 8EN8 is the sensor region, CG is a read control gate.

Claims (1)

[Claims] A channel stop region and an island region of another conductivity type are provided on a substrate of one conductivity type, a transfer region of a negative conductivity type is provided in the island region, and a transfer region of the other conductivity type is provided between the island region and the channel stop region. A solid-state image sensing device comprising: a light-receiving region; a light-receiving electrode provided on the light-receiving region via an insulating layer and the substrate are kept at the same potential; and the potential is made different between a light-receiving period and a read-out period.