JPS5919373B2 - Clock switching method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a clock supply system in which a plurality of clock sources capable of supplying clock signals to a computer system are provided, in which the computer system is stopped for a long time when switching clock signals. The present invention relates to a clock switching method that allows clocks to be switched.

Figure 1 shows a conventional clock supply system,
1 is a configuration controller, e.g. a memory control unit; 2 is a clock source for generating a clock signal; 3-A and 3-
B indicates the main device, and 4-A and 4-B indicate the common devices, respectively.

The main device is, for example, a central processing unit, and the common device is, for example, a memory or a channel. The clock supply system shown in FIG. 1 has a simple configuration, but when system A and system B are logically separated, it is difficult to control the clock independently of each system. Also, system A
If system B and system B are physically separated, a new device implementing a clock source will be required. moreover,
The conventional system of FIG. 1 does not allow maintenance of the clock source. FIG. 2 shows another conventional example of the clock supply system.

In FIG. 2, 5-A and 5-B indicate switching circuits, and 6-A and 6-B indicate switches, respectively. The same reference numerals as in Fig. 1 indicate the same things. When switch 6-A is turned on, the clock signal from clock source 2-A is output from switching circuits 5-A and 5-B, and when switch 6-B is turned on, the clock signal from clock source 2-A is output from switching circuits 5-A and 5-B. A clock signal from the switching circuits 5-A and 5-B is output from the switching circuits 5-A and 5-B. In the conventional system shown in FIG. 2, each system A and B can independently control the clock depending on how the switching circuit and common device are constructed. Furthermore, if system A and system B are physically separated, there is no need for a new device equipped with a clock source. However, with the conventional method shown in Figure 2, the integrity of each system's operation cannot be guaranteed when switching clock sources, and each system must be stopped for a sufficiently long time compared to the clock cycle. It won't happen. The present invention is based on the above considerations, and uses a clock supply system that is equipped with a clock generation mechanism and a clock switching circuit for computers, thereby guaranteeing system operation even during clock switching. It is an object of the present invention to provide a clock switching method that can shorten the clock switching time so as not to affect the operation of the system. Therefore, in a computer system having two computers, a clock generation mechanism is provided for each computer and has one or more internal clock sources, and a clock generation mechanism is provided for each computer and has one or more clock sources inside. A clock switching circuit into which the clock from the clock generation mechanism is input, a clock specifying mechanism that specifies the clock output from the two clock switching circuits, and an interface signal provided between the two clock switching circuits. and each of the clock switching circuits recognizes the state of the clock switching circuit on the other side via the interface signal line, and simultaneously stops and switches the clock before switching at the same time as the clock switching circuit on the other side. In a clock switching system that is configured to transmit the subsequent clock, each clock switching circuit has a local clock transmission control section that controls the transmission of the clock from the local clock generation mechanism, and a clock transmission control section that controls the transmission of the clock from the local clock generation mechanism. and an other-system clock transmission control section that controls the transmission of the clock of the other system, and the own-system clock transmission control section controls the clock designation mechanism to specify the own-system clock and the other-system clock transmission control section of the other-side clock switching circuit. On the condition that the clock is stopped or the power source of the other side is not established, control to send out the own system clock is started, and the designation of the own system clock by the clock designation mechanism is canceled. or when the power supply of the other side is established and the own system clock transmission control section of the other side switching circuit starts clock transmission control, the system is configured to start control for stopping the own system clock, and the above-mentioned other system clock transmission is performed. The control section starts control for sending out the other system clock on the condition that the own system clock transmission control section of the other side clock switching circuit is in the clock sending operation, and also starts the control to send out the other system clock. The present invention is characterized in that the transmission control section starts control for stopping the clocks of other systems on the condition that the clocks are being stopped. Hereinafter, the present invention will be explained with reference to the drawings. FIG. 3 is a diagram showing an outline of one embodiment of the present invention, FIG. 4 is a block diagram of one embodiment of the switching circuit of the present invention, and FIG. 5 is a time chart showing the operation of one embodiment of the present invention. be.

In FIG. 3, 10-A and 10-B are central processing units;
11-A and 11-B are memory control devices/memories, 12-
A and 12-B are channel control devices/channels, 13-A
and 13-B are service processors, 14-A and 14-
B is a switching circuit, 15-A and 15-B are also switching circuits, 16-
A and 16-B are clock sources, 17-A and 17-B
Also clock source, 18 is interface signal line, 1
9-A and 19-B respectively show clock generation mechanisms. Clock sources 16-A and 16-B generate clock signals with regular cycles, and
Sources 17-A and 17-B generate test clocks. The regular clock source has a period of, for example, 100 ns, and the test clock source has a period of, for example, 95 ns. The switching circuit 15-A switches between the clock sources 16-A and 17-A.
Switching circuit 15-B connects clock sources 16-B and 17-
B. Service processor 13-
A, l3-B are clock generation mechanisms 19-A, l9-B.
This specifies which one to use. When systems A and B are physically coupled, it is natural that service processors 13-A and 13-B specify the same clock generation mechanism. When the clock generation mechanism 19-A is specified as the clock generation mechanism to be used, the switching circuits 14-A} and 14B output the clock from the clock generation mechanism 19A, and select the clock generation mechanism as the clock generation mechanism to be used. When 19-B is instructed, switching circuit 14-A and switching circuit 14
-B outputs the clock from the clock generating mechanism 19-B. Memory controller/memo I rivers 1A and 11-B can receive clocks from both switching circuits 14-A and l4-B, and channel controller/channels 12-A and l2
-B can also receive clocks from both switching circuits 14-A and 14-B. The clock generation mechanisms used are divided into clock generation mechanisms 19-A to 19-A.
When switching to B, the following operations are performed.

When the service processors 13-A and 13-B instruct that the clock generation mechanism 19-B should be used, the switching circuit 14-A starts the operation of stopping the clock from the clock generation mechanism 19-A, and Interface line 18
A notification to the effect that the clock stop operation has started is sent to the switching circuit 14-B via the switching circuit 14-B. When the switching circuit 14-B receives this notification, it starts the operation of stopping the clock from the clock generating mechanism 19-A. As a result, switching circuit 1
4-A and 14-B simultaneously stop the clock from the clock generating mechanism 19-A. Moreover, the switching circuit 14-A is
Before ending the operation of stopping the clock from the clock generation mechanism 19-A, this is notified to the switching circuit 14-B. When the switching circuit 14-B receives this notification, it starts the operation of sending out the clock from the clock generation mechanism 19-B, and also starts sending out the clock from the clock generation mechanism 19B to the switching circuit 14-A. The switching circuit 14-A is notified that the operation is being performed. Switching circuit 14
-A, upon receiving this notification, clock generation mechanism 19-
The operation for sending the clock from B is started. As a result, the switching circuits 14-A and 14-B simultaneously send out the clock from the clock generating mechanism 19-B.
The above description describes the operation when switching the clock generation mechanism used from the clock generation mechanism 19-A to the clock generation mechanism 19-B. A similar operation is performed when switching to A. Figure 4 shows the switching circuit 14.
-A block diagram is shown. In addition, switching circuit 1
4-B has the same configuration as the switching circuit 14-A. 20 is a power supply control unit, SEL is a flip-flop, L1 to L
6 is a flip-flop, R1 to R3 are also flip-flops.
Flop, G1 to G25 are gates, SW is short circuit plate,
DLl and DL2 indicate delay circuits, respectively.

Also, PRDYO, PRDYl, PRDYL, OSCO
,OSCi,SELA,SELO,SELi,INST
ALL, CHGO, CHGi, GOO, GOi, USE
RO and USERl are signals having the following contents. A power supply ready signal that indicates to other systems that the PRDYO voltage has been established.

PRDYi Power supply ready signal from another system indicating that the voltage of the other system has been established.

Power ready signal indicating that the PRDYL voltage has been established.

A signal specifying the SELA clock generation mechanism 14-A.

SELO A signal that notifies the state of flip-flop SEL to a switching circuit in another system.

SELi A signal from another system indicating the state of flip-flop SEL of a switching circuit of another system.

INSTALL A signal indicating whether system A and system B are physically coupled.

A signal that notifies the switching circuit of another system of the clock transmission status from the clock generation mechanism of CHGO's own system.

A signal that notifies the switching circuit of another system of the clock transmission status from the clock generation mechanism of GOO's own system. However, the state change of this signal occurs later than the signal CHGO.

CHGi signal A signal from another system corresponding to CHGO.

GOi signal A signal from another system that corresponds to GOi.

A signal indicating whether the remote side clock can be used for the common device of USERO system B.

A signal sent from USERi system B indicating whether the remote side clock can be used.

Clock output from DCLK switching circuit.

Next, the operation of one embodiment of the present invention will be described in detail with reference to FIGS. 4 and 5.

Assume that the system A side is powered on at time I (9). Power is turned on in the order of central processing unit 10-A, memory control unit/memo I river 1A, channel control unit/channel, and 12-A. All flip-flops L1 to L6
, Rl to R3 are undefined, but the signal +PRD
Since Yi is logic "0", gate G3 is opened and flip-flops L1, L2, . . ., L6 are turned on in sequence. Flip-flop L6 and flip-flop R
Until the state of No. 3 is determined, the clock output card DCLK remains undefined, but each device 10-A, 11-A, 12-A is protected by its respective power supply ready signal. When flip-flop R3 is turned off and flip-flop L6 is turned on, the clock from the clock generation mechanism 19-A of system A is changed to clock +DCL by gate G7.
It is output as K from the switching circuit 14-A. Next, assume that system B is powered on at time @.

System B power supply ready signal 10PRDYL is logic “1”
The flip-flop L1 in the switching circuit 14B until
and R1 continues to be set flip-flop L1
Then, the L6 hexagram and the flip-flops R1 to R3 are sequentially turned off.

The other system clock enable signal USERO is sent to the common devices 11-A and 12-A of system A, but this signal is specified by the delay circuit DL2 after the power supply ready signal becomes logic "1". After the elapse of time, the logic becomes "1".
When DYL becomes logic “1”, flip-flop L1
Afterwards, the flip-flop R1 becomes operational. Now, if the signal SELA is logic "1", the flip-flop SEL of the switching circuit 14-A is turned on, and the gate G3 of the switching circuit 14-B is turned off.As a result, 1
Flip-flops L1 through L6 in 4-B remain off. Status signal C input to switching circuit 14-B
Both HGi and GOi become logic "1", which turns on flip-flops R1 to R3 in sequence. The gate G8 of the switching circuit 14-B allows the clock from the clock generation mechanism 14-A to be output from the switching circuit 14-B. Next, assume that time @) = +SELA becomes logic "0". At path 14-A, gate G3 is off and flip-flops L1 to L
6 are turned off sequentially. The signal CHGO, which is the output of the flip-flop L3 of the switching circuit 14-A, is turned off.
This signal +CHGO is the signal of the switching circuit 14-B → -CH
Gi, turns off the gate G6 of the switching circuit 14-B, and sequentially turns off the flip-flops R1 to R3. Flip-flop L6 of switching circuit 14-A and flip-flop R3 of switching circuit 14-B are turned off at the same time. The output +GOi of the flip-flop L5 of the switching circuit 14-A becomes the signal +CHGi of the switching circuit 14-B.

As a result, the gate G3 of the switching circuit 14-B is turned on, and the flip-flops L1 to L of the switching circuit 14-B are turned on.
3 are turned on sequentially. The output +CHGO of the flip-flop L3 of the switching circuit 14-B becomes the signal CHGi of the switching circuit 14-A. As a result, gate G6 of switching circuit 14-A is turned on, and flip-flops R1 to R3 of switching circuit 14-A are turned on in synchronization with flip-flops L4 to L6 of switching circuit 14B. That is, the flip-flop R3 of the switching circuit 14-A and the switching circuit 1
Flip-flop L6 of 4-B is turned on at the same time.
Clock supply is stopped until flip-flop R3 of switching circuit 14-A and flip-flop L6 of switching circuit 14-B are turned on, but by appropriately setting the number of flip-flop stages, this clock supply can be stopped. The stop time can be shortened to the extent that it does not affect the operation of the system.

Next, assume that the power cutoff switch for system A is turned on.

Then, the power ready signal immediately drops and the switching circuit 1
The signal PRDYO of 4-A becomes logic "0". This signal PRDYO becomes the signal PRDYi of the switching circuit 14-B, and the gate G3 of the switching circuit 14-B is turned on. below,
Flip-flops L and L6 of the switching circuit 14B are turned on successively, and the clock of the clock generating mechanism 19-B is output from the switching circuit 14-B. After that, powering off of system A is started. As is clear from the above description, according to the clock switching method of the present invention, system continuity is guaranteed even when the clock source is switched.
The clock switching time can also be shortened to the extent that it does not affect the operation of the system.

[Brief explanation of drawings]

1 and 2 are diagrams showing a conventional clock supply system, respectively, FIG. 3 is a diagram showing an outline of an embodiment of the present invention, and FIG.
The figure shows one embodiment of the switching circuit of the present invention, and FIG. 5 is a time chart showing the operation of one embodiment of the present invention. 10-A and 10-B...Central processing unit, 11-A and 1
1-B...Memory control device/memory, 12-A and 12
-B...Channel control device/channel, 13A and 13
-B. ．． ．． Service processors, 14-A and 14-B
... switching circuit, 15-A and 15-B... switching circuit,
16-A and 16-B...clock sauce, 17-A
and 17-B... clock source, 18... interface signal line, 19-A and 19B... clock generation mechanism.

Claims (1)

[Claims] 1. In a computer system having two computers, a clock generation mechanism provided for each computer and having one or more internal clock sources, and a clock generation mechanism provided for each computer and from the above two clock generation mechanisms. a clock switching circuit into which a clock is input, a clock specifying mechanism for specifying a clock output from the two clock switching circuits, and an interface signal line provided between the two clock switching circuits. , and each of the clock switching circuits recognizes the state of the clock switching circuit on the other side via the interface signal line, and simultaneously stops the clock before switching and transmits the clock after switching at the same time as the clock switching circuit on the other side. In the clock switching method configured to perform this, each clock switching circuit includes a local clock transmission control section that controls clock transmission from the local clock generation mechanism, and a local clock transmission control section that controls clock transmission from the other system clock generation mechanism. and an other-system clock transmission control unit that detects that the clock designation mechanism has specified the own-system clock and that the own-system clock transmission control unit of the other-side clock switching circuit is in a clock stop operation. or when the control to send the own system clock is started on the condition that the power supply of the other side is not established, and the specification of the own system clock by the clock designation mechanism is canceled, or when the other side's When the power supply is established and the own system clock transmission control section of the other side switching circuit starts clock transmission control, the other system clock transmission control section is configured to start control for stopping the own system clock, and the other system clock transmission control section On the condition that the own system clock transmission control section of the side clock switching circuit is in the clock transmission operation, the own system clock transmission control section of the said other side clock switching circuit starts the control for sending out the other system clock, and the own system clock transmission control section of the said other side clock switching circuit starts the clock transmission operation. A clock switching method characterized in that control for stopping a clock of another system is started on the condition that the clock is in a stopping operation.