JPH03230725A - Power-on control method - Google Patents

Abstract

PURPOSE:To suppress a rush current at the time of power supply closing below a limit value by a method wherein a timing signal generating part transmits a timing signal to a closing means in accordance with data stored in a storage part. CONSTITUTION:Delay times T1-Tn between times when switches are closed and times when AC input signals are transmitted to power supplies (not shown in the figure) are stored in a memory 2 as delay time data 4. The delay times 4 are so predetermined as to make their summation not exceed a limit value. A CPU 1 reads the delay time data 4 in accordance with a processing program 3 and sets them in registers RG1-RGn. A counter circuit 6 starts counting by the oscillation output of a clock 5 when the switches are closed. If the output of the counter circuit 6 agrees with the outputs of the registers RG1-RGn, AND gates 71-7n output control signals S1-Sn.

Description

[Detailed Description of the Invention] [Summary] Regarding a power-on method for turning on power from a plurality of power supply units to a plurality of power supply units, it is possible to In a device that aims to reduce the inrush current value at power-on to a limit value or less, and is composed of a plurality of power supply parts and a plurality of power supply parts that are individually connected to the plurality of power supply parts and operate respectively. , a power-on means for individually turning on power to each power supply section, a timing signal generation section for individually supplying a timing signal for power-on to the power supply means, and a timing signal generation section for generating a timing signal. A storage unit is provided in which the timing of the output is stored in advance as data, and the timing signal generation unit transmits a timing signal to the input means based on the data stored in the storage unit, so that the power supply unit supplies power to the power supplied unit. Configure to supply.

[Industrial application field]

The present invention relates to a power-on method for turning on power from a plurality of power supply units to a plurality of power-supplied units.

In recent years, there has been a demand for multifunctional and high performance devices. However, in realizing these demands, the scale of the device becomes larger, and the problem arises that the inrush current generated when the power is turned on also becomes larger. For this reason,
It is necessary to ensure that the inrush current value when the power is turned on is below the limit value.

[Conventional technology]

Conventionally, in order to keep the inrush current value at power-on below a limit value, efforts have been made to develop elements, design, etc. to reduce the current consumption value of each power supplied section.

[Problem to be solved by the invention]

However, with the recent remarkable trend toward multi-functionality and higher performance of devices, it has become impossible to keep up with the reduction in the current consumption value of each power supply unit due to element development, design efforts, etc.

In view of the above-mentioned problems, the present invention has been made to reduce the consumption @'a of each power supply unit.
The purpose is to reduce the inrush current value at power-on to a limit value or less without decreasing the value.

[Means for Solving the Problems] A device consisting of a plurality of power supply units C1 to Cn and a plurality of power supplied units DI-Dn that are individually connected to the plurality of power supply units C1 to Cn and operate respectively. In the above, power-on means RL1 to RLn, l1 to In for individually turning on the power to each of the power supply units C1 to Cn, and a timing for turning on the power to each of the power supply means RL1 to RLn, 11 to In individually. A timing signal generation section that provides a signal, and a storage section 4 that stores in advance the timing at which the timing signal generation section issues a timing signal as data are provided, and the timing signal generation section generates input data based on the data stored in the storage section 4. By transmitting timing signals to the means RL1 to RLn and l1 to In, the power supply units C1 to Cn are configured to supply power to the powered units D1 to Dn.

[Action:.

According to the present invention, each power supply section turns on power to each power supply receiving section according to the timing stored in advance in the storage section.

〔Example〕

FIG. 1 shows an embodiment of the present invention. In the figure, AI is an AC input control section, A2 is a power supply sequence control section, CI-Cn is a power supply section, D1 to Dn are I10 devices, and ASI-ASn is an AC input control section.
AC input signals from the input control unit AI to each power supply unit CI-Cn, and 3l-3n are control signals from the power supply sequence control unit A2 to the AC input control unit A1. In addition, the same parts are given the same reference numerals throughout the figures.

FIG. 2 is an internal configuration diagram of the power supply sequence control section A2. In the figure, 1 is a central processing unit (hereinafter referred to as CPU1)
The delay time Tl-Tn is read out from the memory 2 according to the program 3 and set in the registers 7, to 7n.

A memory 2 stores a processing program 3 and delay time data 4, which will be described later. 3 is a processing program, which is a program for the CPU 1 to execute the above processing. 4 is delay time data, and the delay times T1 to Tn from the time when the switch is turned on until the AC input signal is sent to each power supply unit C1 to Cn in FIG. 1 are stored as data in the memory 2. be. In addition, this delay time data 4 was experimentally determined using time as a parameter.
This is data that is preset based on the results of measuring the inrush current and steady current for each power source so that the sum of them does not exceed the limit value when each power source is turned on. Reference numeral 5 denotes a clock, which outputs oscillation to the counter circuit 6. A counter circuit 6 starts counting based on the output of the clock 5 when a switch (not shown) is turned on. RG1 to RGn are registers in which the delay data 4 read by the CPU when the switch is turned on is stored.

Also, 71-7. , is an AND gate, which takes the logical product of the output of the counter circuit 6 and the registers RGI to RGn, and outputs control signals 5l to 5n if they match.

FIG. 3 is an internal configuration diagram of the AC manual control unit A1, in which TRI to TRn are relay driving transistors, RLI
~RLn is a relay, and 11~ln are relay contacts.

FIG. 4 shows the control signals 5l-3n and the delay times T1-Tn set for each of the voltages aC1-Cn.
[This is a (time) vs (current) curve when voltl is input.

Embodiments of the present invention will be described in detail below with reference to FIGS. 1 to 4 above.

In FIG. 2, when a power switch (not shown) is turned on, the CPU reads out the delay time data 4 for the processing program 3 and stores it in the registers RG1 to RGn. On the other hand, the counter circuit 6 starts counting based on the oscillation output of the clock 5 at the same time as the switch is turned on. Each AND gate 71-7n outputs a control signal 81-Sin when the output of the register RGI-RGn in which the delay time data 4 is sent matches the output of the counter circuit 6.

Next, the AC input control section AI shown in FIG. 3 sequentially applies driving alternating current output voltages to the power supplies C1 to Cn based on the control signals S1 to Sn. That is, when the control signal S1 is output, the relay driving transistor TRI is turned on, and the relay RL1 is excited. As a result, the relay contact 11 becomes a make state, the I10 device driving AC voltage (AClooV) is applied to the power source C1, and the driving AC current output voltage is supplied to the I10 device DI shown in FIG. Next, as shown in FIG. 4, after the delay time T1 has elapsed,
By turning on the control signal S2, I1
A driving alternating current output voltage is supplied to the 0 device D2. Thereafter, the driving alternating current output voltage is applied to the I10 device Dn in the same manner.

〔Effect of the invention〕

According to the present invention, by applying AC inputs of a plurality of power supplies connected to a plurality of I10 devices with a delay time, the inrush current value of a device constituted by a plurality of 110 devices S can be reduced. I can do it. Therefore, there will be no hindrance to realizing multi-functionality and high performance of the device.

In addition, the delay time data stored in the memory can be freely set within the range where the sum of inrush current and steady current does not exceed the limit value, so it is possible to power on multiple I10 devices at the same time. Because of this, after inserting HB, all 1
It is possible to activate 10 devices.

[Brief explanation of drawings]

FIG. 1 is an embodiment of the present invention, FIG. 2 is an internal configuration diagram of a power supply sequence control section, FIG. 3 is an internal configuration diagram of an AC manual control section, and FIG. 4 is an operating waveform diagram. In the figure, the numbers are as follows. A1 ... AC input control section A2 ...
... Power sequence control door section C1~Un...
Power supply D1 to DI... I10 device ■... CPU 2... Memory 3... Processing program 4... Delay time data 5... ... Clock clock ... Counter circuit 7 ...... A N D circuit

Claims (1)

[Claims] A plurality of power supply units (C1 to Cn) and a plurality of power supply units (D1 to Dn) each individually connected to the plurality of power supply units (C1 to Cn) and operating respectively. In the apparatus, power-on means (RL1-RLn, l1-l
n); a timing signal generation unit that individually provides a power-on timing signal to each of the input means (RL1 to RLn, l1 to ln); and a timing at which the timing signal generation unit generates the timing signal is stored in advance as data. A storage unit (4) is provided, and the timing signal generation unit generates input means (RL1 to RLn, l1 to ln) based on the data stored in the storage unit (4).
), the power supply units (C1 to Cn) supply power to the power supplied units (D1 to Dn) by transmitting a timing signal to the power supply units (C1 to Cn).