JPS59189428A - Digital output latch control method - Google Patents

Abstract

PURPOSE:To execute automatic reset by resetting a latched data, when the following data is not inputted before a timer whose period is larger than a necessary period provided on a circuit for inputting a digital output from a processor in said necessary period is operated. CONSTITUTION:A digital data is outputted from a processor 1 in a period T11 of a built-in timer TM1. A digital outputting circuit 2 inputs said digital data to a set terminal S of an FF, and sends it out as a digital signal output to a part to be controlled of the outside of the figure. A timer TM2 contained in the digital outputting circuit 2 starts to count at the same time as the timer TM1, and its count-up period T22 is set larger than T11, and it is connected to a reset terminal of the FF. In this way, when the following digital data is not inputted before attaining to a time-out period T22 due to a fault of software, etc.; the FF is reset, the digital signal output is stopped, the automatic reset is executed, and the device is protected.

Description

[Detailed description of the invention] Technical field of the invention Misfire E! A is a digital output latch control method that allows the digital output that controls gates, bubbles, etc. for a certain period of time to be automatically reset when a failure occurs.Prior art and problems Conventional technology, for example, when opening a gate , as shown in Fig. 1, the digital output is set to "O" at time T, and is set to 'O' at time T2.
The gate is kept open while 91" is output.

However, for example, if a software failure occurs at time T, it will not be possible to recover to ``0'' at time T2, and ``1'' will continue to be output, resulting in the gate opening too much than necessary. was there.

OBJECTS OF THE INVENTION It is an object of the present invention to provide a digital output launch control system that eliminates such drawbacks and enables automatic recovery in the event of a software failure.

According to the present invention, the above object is to provide a system in which a processor inputs a digital output to a digital output circuit, the digital output circuit latches the digital output, and continuously sends out the digital output. , a digital output is input to the digital output circuit at a constant period (TJ), and a timeout period (T22) larger than the period ('ro) is input.
), and if the digital output is not manually input within a timeout period (T2.) of the timer, the digital output latched in the digital circuit is reset. This is achieved by a latch-controlled output system.

Examples of the invention The present invention will be explained below based on examples.

The second factor is a diagram showing an outline of the present invention, in which the digital output is set to "1" at time T1, and then the setting is repeated at a constant cycle 'I'l+.

If it is not set at time T4, the timer times out after T22 and resets the digital output.

The following description will be made based on the specific example shown in FIG.

In the figure, PRO is a processor, DO (is a digital output circuit, TMI, '1' M2 is a timer, and FF is a flip-flop.

The explanation will be given below according to time chaff 4 in FIG.

Processor P RO &w', , Digital output circuit DO
As well as writing the entire flip-flop FFKゝゝゝ1,
Start timer Ti+TM2.

Then, the processor PRO receives the period TI from the timer TMI.
By the interrupt every t, "l" is again input to the flip-flop FF, and the timer TfVj2 is restarted.

If a soft failure causes the flip-flop FF to 91'
’ is no longer damaged by moss, after T22, timer TM2
times out and resets the flip-flop FF.

Effects of the Invention As described above, according to the present invention, digital output can be automatically restored in the event of a software failure.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing a conventional system, FIG. 2 is a diagram showing an outline of the present invention, FIG. 3 is a diagram showing a specific example of the present invention, and FIG. 4 is a diagram showing the operation flow of FIG. 3. be. In the figure, PRO is a processor, DO is a digital output circuit, and F
F is a flip-flop, TMI and TM2 are timers. Negative 1 Audience 2 Tsuba 3rd 4th fl 141-

Claims (1)

[Claims] In a system in which a digital output is input to a digital output circuit, the digital output is multiplied by the digital output circuit, and the digital output is continuously sent out, the digital output is sent to the digital output circuit at a constant rate. period(
'r++) and starts a timer with a timeout cycle M (T22) larger than the cycle (Tll), and if the digital output is not input within the timeout cycle (T22) of the timer, the digital circuit Digital output latch control method 0 characterized by resetting the digital output latched to