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JPS59188373A - Snubber circuit for self-extinguishing semiconductor devices - Google Patents

Snubber circuit for self-extinguishing semiconductor devices

Info

Publication number
JPS59188373A
JPS59188373A JP5930683A JP5930683A JPS59188373A JP S59188373 A JPS59188373 A JP S59188373A JP 5930683 A JP5930683 A JP 5930683A JP 5930683 A JP5930683 A JP 5930683A JP S59188373 A JPS59188373 A JP S59188373A
Authority
JP
Japan
Prior art keywords
capacitor
circuit
thyristor
snubber
turned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5930683A
Other languages
Japanese (ja)
Inventor
Hiroshi Narita
博 成田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5930683A priority Critical patent/JPS59188373A/en
Publication of JPS59188373A publication Critical patent/JPS59188373A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H02GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02MAPPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00Details of apparatus for conversion
    • H02M1/06Circuits specially adapted for rendering non-conductive gas discharge tubes or equivalent semiconductor devices, e.g. thyratrons, thyristors

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Power Conversion In General (AREA)

Abstract

PURPOSE:To provide a snubber circuit of a self-extinguishing type semiconductor element adapted for a large capacity without loss by providing a switch element in a circuit for transferring the charge of a snubber capacitor to the second capacitor. CONSTITUTION:A thyristor ThR is provided in series with a reactor LR, and a snubber capacitor of a freewheel diode DF is commonly used as a regenerative capacitor CR. When an ON signal is applied to the thyristor ThR substantially in synchronization with the turn ON of a GTO thyristor, the charge of a snubber capacitor CS is transferred to the capacitor CR, and the thyristor ThR is then turned OFF. When the GTO thyristor is turned OFF, the charge of the capacitor CR is applied to a load, while the capacitor CS is overcharged. When the GTO thyristor is then turned ON, the charge of the capacitor CS is transferred to the capacitor CR.

Description

【発明の詳細な説明】 〔発明の対象〕 本発明は自己消弧型半導体素子のスナバ回路に係シ、特
にスナバ回路の損失を低減するロスレス・スナバ回路方
式に関する。
DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] The present invention relates to a snubber circuit for a self-extinguishing semiconductor device, and more particularly to a lossless snubber circuit system for reducing loss in the snubber circuit.

〔従来技術〕[Prior art]

第1図は従来の自己消弧型半導体素子(ここではゲート
ターンオフ・サイリスタGTOで示しである)のロスレ
ス・スナバ回路の一例を示す図、第2図は第1図回路の
動作説明図である。第1図において、負荷りに直列接続
したGTOサイリスタにはダイオードDsとコンデンサ
Csの直列体よシ成るスナバ回路を並列接続し、また負
荷りにはフリーホイール・ダイオードDyとそのスナバ
回路(抵抗RnyとコンデンサCDFの直列体)を並列
接続しである。そして、前記GTOサイリスタのスナバ
回路であるダイオードDsとコンデンサCsの接続点か
らりアクドルLRとダイオードDRの直列体を該ダイオ
ードDBのカソードと前記フリーホイール・ダイオード
DFのカソードが同一電位となるように接続し、さらに
リアクトルLRとダイオードDRの接続点と前記フリー
ホイール・ダイオードDyのアノードとの間に第2のコ
ンデンサCBを接続しである。なお、VBは電源電圧、
Ijtは配線インダクタンスを示している。
Figure 1 is a diagram showing an example of a lossless snubber circuit for a conventional self-extinguishing semiconductor device (shown here as a gate turn-off thyristor GTO), and Figure 2 is an explanatory diagram of the operation of the circuit in Figure 1. . In Figure 1, a snubber circuit consisting of a series body of a diode Ds and a capacitor Cs is connected in parallel to the GTO thyristor connected in series to the load, and a freewheeling diode Dy and its snubber circuit (resistance Rny and a series body of capacitor CDF) are connected in parallel. Then, from the connection point of the diode Ds, which is the snubber circuit of the GTO thyristor, and the capacitor Cs, the series body of the accelerator LR and the diode DR is connected so that the cathode of the diode DB and the cathode of the freewheeling diode DF are at the same potential. Further, a second capacitor CB is connected between the connection point of the reactor LR and the diode DR and the anode of the freewheeling diode Dy. Note that VB is the power supply voltage,
Ijt indicates wiring inductance.

この回路の動作を第2図の動作説明図によフ説明する。The operation of this circuit will be explained with reference to the operation explanatory diagram of FIG.

GTOサイリスタのオフ状態ではコンデンサCsK電源
電圧v8が充電されているが、この状態からGTOサイ
リスタをターンオンすると、コンデンサCsの電圧はり
アクドルLR→コンデンサCR−+GTOサイリスタ→
コンデンサCsの閉回路で放電され、最終的にコンデン
サCsの電圧が第2のコンデンサCRに移される。そし
て、GTOサイリスタがターンオフされると、コンデン
サCRの電圧はダイオードDR→負荷し→コンデンサC
Rの閉回路で放電され、コンデンサCRは負荷りに電力
を供給するGTOサイリスタのターンオフによシ、コン
デンサCsには再びダイオードDsを介して電流が流れ
、GTOサイリスタへの再印加電圧上昇率を所要値に抑
制しながらほぼ電源電圧Vs’!:で充電される。
When the GTO thyristor is in the OFF state, the capacitor CsK power supply voltage v8 is charged, but when the GTO thyristor is turned on from this state, the voltage of the capacitor Cs becomes ACDOLE LR → CAPACITOR CR- + GTO thyristor →
The capacitor Cs is discharged in a closed circuit, and the voltage of the capacitor Cs is finally transferred to the second capacitor CR. Then, when the GTO thyristor is turned off, the voltage of capacitor CR is diode DR → load → capacitor C
The capacitor CR is discharged in the closed circuit of R, and due to the turn-off of the GTO thyristor that supplies power to the load, current flows through the capacitor Cs again via the diode Ds, and the rate of voltage increase is reapplied to the GTO thyristor. Almost the power supply voltage Vs' while suppressing it to the required value! : Charged with.

以上に述べた第1図の従来回路においては、GTOサイ
リスタのスナバコンデンサCsに蓄えられたエネルギは
、第2のコンデンサCRを介してほとんど負荷りに供給
されるので、損失の非常に少ない、いわゆるロスレス・
スナバ回路となっている。
In the conventional circuit shown in FIG. 1 described above, most of the energy stored in the snubber capacitor Cs of the GTO thyristor is supplied to the load via the second capacitor CR, so that the so-called Lossless
It is a snubber circuit.

ところで、この回路を大容量のチョッパ装置やインバー
タ装置に使用することを考えると、第1図に図示した配
線インダクタンスLLの影響が無視できなくなシ、次の
ような不都合が生ずる。すなわち、大容量の装置では配
線インダクタンスLLが大きく、またそれに流れる電流
も大きくなるので、GTOサイリスタのターンオフ時に
スナバコンデンサCsに電源電圧Vs以上の電圧が充電
され、第2図に点線で示した如くGTOサイリスタの端
子電圧が振動的になる。この振動の発生は、先ずコンデ
ンサCsの過充電電圧の放電がリアクトルLn→ダイオ
ードDR→配線インダクタンスLt→電源電圧V8→コ
ンデンサCsの閉回路で行われ、次にこのときに蓄積さ
れた配線インダクタンスLtのエネルギ放電がダイオー
ドDF(負荷りの電流が環流して導通状態にある)→ダ
イオードDs→コンデンサCs→電源電圧VIl→配線
インダクタンスLLの閉回路で行われることによシ、コ
ンデンサCaの充放電を繰返し行うために生ずる。この
振動電流のためにダイオードDaが導通中のときに、G
TOサイリスクがターンオンされると、ダイオードDB
がリカバリして電圧阻止能力を回復するまでにコンデン
サCsの電荷がGTOサイリスタに放電され、該GTO
サイリスタには過大な電流上昇率でもって電流が流れ込
み、GTOサイリスタを破損することになる。
By the way, when this circuit is used in a large-capacity chopper device or inverter device, the influence of the wiring inductance LL shown in FIG. 1 cannot be ignored, and the following problems occur. That is, in a large-capacity device, the wiring inductance LL is large and the current flowing through it is also large, so when the GTO thyristor is turned off, the snubber capacitor Cs is charged with a voltage higher than the power supply voltage Vs, as shown by the dotted line in Fig. 2. The terminal voltage of the GTO thyristor becomes oscillatory. This vibration occurs because first, the overcharge voltage of the capacitor Cs is discharged in a closed circuit of reactor Ln → diode DR → wiring inductance Lt → power supply voltage V8 → capacitor Cs, and then the wiring inductance Lt accumulated at this time The energy discharge occurs in the closed circuit of diode DF (current in the load circulates and is in a conductive state) → diode Ds → capacitor Cs → power supply voltage VII → wiring inductance LL, thereby charging and discharging capacitor Ca. This occurs due to repeated actions. When diode Da is conducting due to this oscillating current, G
When TOSirisk is turned on, diode DB
The charge in the capacitor Cs is discharged to the GTO thyristor until the voltage blocking ability is recovered and the GTO
Current flows into the thyristor at an excessively high rate of current rise, damaging the GTO thyristor.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記した従来技術の欠点をなくシ、大
容量装置に適したロスレスのスナバ回路を提供するにあ
る。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art described above and provide a lossless snubber circuit suitable for large-capacity devices.

〔発明の要点〕[Key points of the invention]

本発明の特徴は、スナバコンデンサの電荷を第2のコン
デンサに移す回路内にスイッチ要素を設けたことにある
A feature of the invention is the provision of a switching element within the circuit that transfers the charge of the snubber capacitor to the second capacitor.

〔発明の実施例〕[Embodiments of the invention]

第3図に本発明の一実施例を示す。第3図回路では、第
1図従来回路のりアクドルLRと直列にサイリスタT 
h Rを設け、さらにフリーホイール・ダイオードDr
のスナバコンデンサCDFを回生用コンデンサCRと共
用している。第3図回路において、GTOサイリスタの
ターンオンにほぼ同期してサイリスタThiにオン信号
を与えると、第1図従来回路と同様にスナバコンデンサ
Csの−電圧はコンデンサCnに移され、その後サイリ
スタThRはターンオフされる。GTOサイリスタがタ
ーンオフされると、コンデンサCRの電圧は負荷りに印
加され、一方スナバコンデンサC8には第1図従来回路
と同様に電源電圧711以上の電圧が過充電される。し
かし、第3図回路においては、この過充電電圧がサイリ
スタThRに阻止されて放電することはないので、第1
図で生じた欠点は除去されるばかりでなく、次のGTO
サイリスタのターンオンでコンデンサCRに移され、次
いでGTOサイリスタのターンオフ時に負荷りに供給さ
れる効果がある。すなわち、第1図の回路では回路の配
線抵抗に消費していた配線インダクタンスLtの蓄積エ
ネルギをも負荷りに供給できる特徴がある。
FIG. 3 shows an embodiment of the present invention. In the circuit shown in Figure 3, a thyristor T is connected in series with the axle LR in the conventional circuit shown in Figure 1.
h R is provided, and a freewheel diode Dr
The snubber capacitor CDF is shared with the regeneration capacitor CR. In the circuit of Fig. 3, when an on signal is given to the thyristor Thi almost in synchronization with the turn-on of the GTO thyristor, the negative voltage of the snubber capacitor Cs is transferred to the capacitor Cn, as in the conventional circuit of Fig. 1, and then the thyristor ThR is turned off. be done. When the GTO thyristor is turned off, the voltage across the capacitor CR is applied to the load, while the snubber capacitor C8 is overcharged with a voltage equal to or higher than the power supply voltage 711, similar to the conventional circuit of FIG. However, in the circuit of FIG. 3, this overcharge voltage is blocked by the thyristor ThR and does not discharge, so the first
The defects that occurred in the figure are not only removed, but also the next GTO
The effect is that it is transferred to capacitor CR at turn-on of the thyristor and then supplied to the load at turn-off of the GTO thyristor. That is, the circuit shown in FIG. 1 has the characteristic that the energy stored in the wiring inductance Lt, which was consumed in the wiring resistance of the circuit, can also be supplied to the load.

第4図に本発明の他の実施例を示す。大容量の装置では
、一般に電源電圧VBが高く、GTOサイリスタのター
ンオン時にフリーホイール・ダイオードDFをリカバリ
するための電流が、配線インダクタンスLLのみによシ
抑制されるため、電流上昇率及びリカバリ電流のピーク
値が大きくなシ、GTOサイリスタやフリーホイール・
ダイオードDrを破損するおそれが生ずる。このため、
()TOサイリスタと直列にアノードリアクトルLAを
接続しリカバリ電流を所要値に抑制していた。そして、
GTOサイリスタのターンオフ時にはスナバコンデンサ
Csの過充電電圧が高くならないように第4図に点線で
示した回路でその蓄積エネルギを抵抗に消費していた。
FIG. 4 shows another embodiment of the invention. In large-capacity devices, the power supply voltage VB is generally high, and the current for recovering the freewheel diode DF when the GTO thyristor is turned on is suppressed only by the wiring inductance LL. If the peak value is large, GTO thyristor or freewheel
There is a risk of damaging the diode Dr. For this reason,
() An anode reactor LA was connected in series with the TO thyristor to suppress the recovery current to a required value. and,
When the GTO thyristor is turned off, the accumulated energy is consumed in a resistor in the circuit shown by the dotted line in FIG. 4 to prevent the overcharge voltage of the snubber capacitor Cs from becoming high.

本発明による第4図の回路では、スナバコンデンサCs
の過充電電圧はサイリスタT h nによって放電を阻
止されるため、GTOサイリスタの電圧定格から許容さ
れる点まで過充電電圧を高くすることができ、この過充
電電圧を負荷りに供給できる効果がある。
In the circuit of FIG. 4 according to the invention, the snubber capacitor Cs
Since the overcharge voltage of is prevented from discharging by the thyristor T h n, the overcharge voltage can be increased to the point allowed by the voltage rating of the GTO thyristor, and the effect of supplying this overcharge voltage to the load is be.

すなわち、アノードリアクトルL人の蓄積エネルギを抵
抗で消費させることなく負荷に供給できる特徴がある。
That is, the anode reactor has the feature that it can supply the stored energy to the load without consuming it in resistance.

また、第4図の回路では、リアクトルLRをアノードリ
アクトルLAで兼用することによシ、リアクトルLnを
省略できる効果もある。
Further, in the circuit shown in FIG. 4, by using the anode reactor LA also as the reactor LR, there is an advantage that the reactor Ln can be omitted.

これも、過充電電圧の放電回路を有する第1図の従来回
路では考えられない。
This is also inconceivable in the conventional circuit shown in FIG. 1, which has an overcharge voltage discharge circuit.

何故なら、第1図でリアクトルLaを省略すると、過充
電電圧の電源への放電が配線インダクタンスLLのみを
介して行われるため、その放電電流が非常に大きくなる
欠点が生ずるためである。
This is because if the reactor La is omitted in FIG. 1, the overcharge voltage will be discharged to the power supply only through the wiring inductance LL, resulting in a drawback that the discharge current will be extremely large.

第5図、第6図はさらに本発明の他の実施例を示すもの
で、それぞれ単相インバータに適用した回路例である。
FIGS. 5 and 6 further show other embodiments of the present invention, each of which is an example of a circuit applied to a single-phase inverter.

第5図はりアクドルLR(LRI〜LR4)を設けた場
合、第6図はりアクドルLRをアノードリアクトルL人
(LAI〜Lム4)で兼用した回路で、第3図〜第4図
回路で説明した効果がある。また、インバータ回路では
、負荷電流の環流モード時に例えば、L−+L A a
→GTO4→Dy2→L人2→L の外に、L→LA4
→G T 04→DRI→T h RL−+D 8! 
−hLAI →L  のバイパス回路ができる経路が考
えられるが、本発明の如くサイリスタThR1を設ける
ことにより、このノくイノくス回路を防ぐ効果もある。
Fig. 5: When a beam axle LR (LRI to LR4) is provided, Fig. 6 is a circuit in which the beam axle LR is also used as an anode reactor L (LAI to LM4), and is explained in Figs. 3 to 4. It has the effect of In addition, in an inverter circuit, for example, L-+L A a
→GTO4→Dy2→L person 2→L outside L→LA4
→GT 04→DRI→T h RL-+D 8!
-hLAI→L A bypass circuit can be created, but the provision of the thyristor ThR1 as in the present invention has the effect of preventing this bypass circuit.

〔発明の効果〕〔Effect of the invention〕

以上に詳述したように、本発明によれば、大容量のチョ
ッパ装置やインバータ装置に適したロスレス・スナバ回
路とすることができ、配線インダクタンスやアノードリ
アクトルの電磁エネルギを一旦コンデンサに貯えた後に
負荷に供給できる効果がある。
As described in detail above, according to the present invention, a lossless snubber circuit suitable for large-capacity chopper devices and inverter devices can be provided, and after the electromagnetic energy of the wiring inductance and anode reactor is stored in the capacitor, It has the effect of supplying power to the load.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のロスレス・スナバ回路、第2図は第1図
の動作説明図、第3図〜第6図は本発明のロスレス・ス
ナバ回路で、第3図〜第4図はチョッパ回路に適用した
回路例、第5図〜第6図はインバータ回路に適用した回
路例である。 L・・・負荷、GTO・・・ゲートターンオフ・サイリ
スタ、Cs 、Ca 、Cnr−コンデンサ、DIl、
DR。 Dy・・・ダイオード、Lt・・・配線インダクタンス
、LA’、LR・・・リアクトル、ThR・・・サイリ
スタ。 E 第 1[21 第2の 、 l”。 ターンオン      タージオ) 第3 い 謔4n
Figure 1 is a conventional lossless snubber circuit, Figure 2 is an explanatory diagram of the operation of Figure 1, Figures 3 to 6 are lossless snubber circuits of the present invention, and Figures 3 to 4 are chopper circuits. Figures 5 and 6 are examples of circuits applied to inverter circuits. L...load, GTO...gate turn-off thyristor, Cs, Ca, Cnr-capacitor, DIl,
DR. Dy...diode, Lt...wiring inductance, LA', LR...reactor, ThR...thyristor. E 1st [21 2nd, l”. turn on Targio) 3rd curse 4n

Claims (1)

【特許請求の範囲】[Claims] 1、自己消弧型半導体素子に並列接続されたダイオード
と第1のコンデンサの直列体、上記半導体素子のターン
オン時に上記第1のコンデンサの電荷をリアクトルを介
して第2のコンデンサに移す回路手段、上記半導体素子
のターンオフ時に上記第2のコンデンサの電荷を負荷に
供給する回路手段を備えた自己消弧型半導体素子のスナ
バ回路において、上記第1のコンデンサの電荷を上記第
2のコンデンサに移す回路内にスイッチ要素を設けたこ
とを特徴とする自己消弧型半導体素子のスナバ回路。
1. A series body of a diode and a first capacitor connected in parallel to a self-arc-extinguishing semiconductor element, circuit means for transferring the electric charge of the first capacitor to a second capacitor via a reactor when the semiconductor element is turned on; In a snubber circuit for a self-extinguishing semiconductor device, the circuit includes circuit means for supplying the charge of the second capacitor to the load when the semiconductor device is turned off, and the circuit transfers the charge of the first capacitor to the second capacitor. A snubber circuit of a self-extinguishing semiconductor element, characterized by having a switch element provided therein.
JP5930683A 1983-04-06 1983-04-06 Snubber circuit for self-extinguishing semiconductor devices Pending JPS59188373A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5930683A JPS59188373A (en) 1983-04-06 1983-04-06 Snubber circuit for self-extinguishing semiconductor devices

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5930683A JPS59188373A (en) 1983-04-06 1983-04-06 Snubber circuit for self-extinguishing semiconductor devices

Publications (1)

Publication Number Publication Date
JPS59188373A true JPS59188373A (en) 1984-10-25

Family

ID=13109552

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5930683A Pending JPS59188373A (en) 1983-04-06 1983-04-06 Snubber circuit for self-extinguishing semiconductor devices

Country Status (1)

Country Link
JP (1) JPS59188373A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245727A (en) * 1990-02-21 1991-11-01 Mitsubishi Electric Corp Snubber circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245727A (en) * 1990-02-21 1991-11-01 Mitsubishi Electric Corp Snubber circuit

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