CN115441721B - Circuit for increasing holding time - Google Patents

Abstract

The application relates to a circuit for increasing the holding time, comprising: boost converter, capacitor, switch group, control switch and surge protector; the control switch is provided with a normal closing state of the input power supply and an opening state of the input power supply, and when the control switch is in the closing state, the two capacitors are charged; when the control switch is in an on state, the first capacitor charges the second capacitor; therefore, the maintenance time is prolonged, the cost increase and the size increase caused by the arrangement of the Baby Boost circuit are avoided, the loss caused by the inductance on the Baby Boost circuit during the normal operation of the PFC can be removed, and the efficiency of the PFC is improved.

Description

Circuit to improve hold time

[Technical field]

The present application relates to a circuit for improving holding time, belonging to the field of power factor correction.

[Background technology]

With the rapid development of modern industry, the nonlinear loads of power systems are increasing day by day. The harmonic currents generated by these nonlinear loads are injected into the power grid, causing the voltage waveform of the public power grid to be distorted, seriously polluting the environment of the power grid. In order to reduce and eliminate harmonics, power factor correction (PFC) should be performed to obtain an input current close to a sine wave and a power factor close to 1.

In the event of a sudden power outage, many electronic devices and instruments do not have time to react, resulting in data loss or service interruption. Therefore, more and more electronic devices and instruments require a power-off retention function. In order to achieve this function, it is usually necessary to add an energy storage capacitor between the output end of the PFC and the power load, so that the load can continue to work for a period of time by discharging the energy storage capacitor after power failure. However, the existing PFC and the load are generally connected through a D2D module, and the D2D module requires a higher capacitor output voltage to maintain a stable output. When the output voltage of the capacitor is not within the input range of the D2D module, the capacitor voltage cannot be transmitted to the load.

In order to maintain a longer power-off holding time, PFC in the prior art, especially PFC with two or more energy storage capacitors at the output end, will achieve a longer power-off holding time by adding an additional Baby Boost circuit, such as the circuit shown in Figure 2 of the accompanying drawings of the specification. After power failure, it can transfer the power of C1 to C2 through the Baby Boost circuit to increase the time that the output voltage of the energy storage capacitor is between the input range of D2D, thereby allowing the entire circuit to maintain a longer power-off holding time.

However, the above circuit setting method of maintaining a longer power-off holding time will increase the overall cost and volume of the circuit due to the addition of a whole BabyBoost circuit, and the PFC will also increase the loss caused by the conduction of an inductor and a diode during normal operation, thereby causing the PFC efficiency to become lower.

Therefore, it is necessary to improve the prior art to overcome the above defects in the prior art.

[Summary of the invention]

The purpose of the present application is to provide a circuit for improving the holding time with low cost, small size and high efficiency.

The purpose of the present application is to achieve the following technical solution: a circuit for improving holding time, suitable for connecting to an external load through a D2D module, comprising:

A boost converter is provided with at least two paths, and at least two of the boost converter inputs are connected in parallel;

Capacitors, at least two of which are provided, including a first capacitor and a second capacitor suitable for connecting to the D2D module, each of the capacitors being electrically connected to an output end of at least one of the boost converters;

A switch group, electrically connected to the positive electrode plates or the negative electrode plates or the positive electrode plates and the negative electrode plates of at least two of the capacitors;

A control switch is used to connect at least one input end of the boost converter with the first capacitor; and

A surge protection device connected in parallel with at least two of the boost converters and the control switch;

The control switch has a closed state when the input power is normal and an open state when the input power is off. When the control switch is in the closed state, the two capacitors are charged; when the control switch is in the open state, the first capacitor charges the second capacitor.

Furthermore, the boost converter is a Boost circuit or a buck-Boost circuit.

Further, the circuit for improving the holding time also includes an input switch module electrically connected to the input power supply and the boost converter;

When the control switch is in the on state, the input switch module is in a blocking state.

Furthermore, the input switch module is a rectifier bridge or a relay.

Furthermore, the boost converter includes an inductor whose input end is connected to the positive electrode of the input switch module, and a boost switch tube whose one end is connected to the output end of the inductor and the other end is connected to the negative electrode of the input switch module.

Furthermore, a first switch is provided on the connection line between the first capacitor and the second capacitor.

Furthermore, the first switch element is a slow diode.

Furthermore, the capacity of the second capacitor is less than twice the capacity of the first capacitor.

Furthermore, the control switch is one of MOSFET, IGBT, GaN or thyristor.

Further, the switch group includes a first switch tube connected to one of the two boost converters, and a second switch tube connected to the other of the two boost converters;

The first switch tube and the second switch tube are each one of a diode, a MOSFET, an IGBT or a GaN.

Compared with the prior art, the present application has the following beneficial effects: the present application utilizes a boost converter in the original PFC to replace the Baby Boost circuit additionally provided in the prior art, thereby improving the holding time while avoiding the increase in cost and volume caused by providing the Baby Boost circuit, and can also eliminate the loss caused by the inductance on the Baby Boost circuit when the PFC is working normally, thereby improving the efficiency of the PFC.

【Brief Description of the Drawings】

FIG1 is a schematic diagram of the structure of a circuit for improving the holding time according to an embodiment of the present application;

FIG. 2 is a schematic diagram of a circuit structure of the prior art in the background technology.

[Specific implementation method]

In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are described in detail below in conjunction with the accompanying drawings. It is understandable that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some structures related to the present application are shown in the accompanying drawings, rather than all structures. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

The terms "including" and "having" and any variations thereof in this application are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device comprising a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products or devices.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

Please refer to Figure 1, a circuit for improving the holding time shown in an embodiment of the present application is suitable for connecting to an external load through a D2D module, including a boost converter, a capacitor, a switch group, a control switch Q3, and a surge protection component D5, wherein the boost converter is provided with at least two paths, and at least two boost converter inputs are connected in parallel to form two boost loops, and at least two capacitors are also provided accordingly, including a first capacitor C1 and a second capacitor C2 connected to the D2D module, each capacitor is electrically connected to the output end of at least one boost converter, because the second capacitor C2 needs to be connected to D2D as the output end of the circuit for improving the holding time of the present application, so the voltage at the second capacitor C2 is greater than the voltage at the first capacitor C1.

The switch group is electrically connected to the positive plates or negative plates or the positive plates and negative plates of at least two capacitors to prevent the at least two capacitors from discharging to the ground. The control switch Q3 connects the output end of at least one boost converter to the first capacitor C1. The surge protection component D5 is suitable for being connected in parallel with at least two boost converters to reduce the impact of surge voltage on the boost converters and generate impact current to charge the first capacitor C1 and the second capacitor C2.

The control switch Q3 is closed at a high level, and is connected to the output end of at least one boost converter and the first capacitor C1 at a low level, so that the control switch Q3 has a normal closed state when the input power supply Vin is normal, and an open state when the input power supply Vin is powered off. When the control switch Q3 is in the closed state, the two boost converters operate normally, and the two capacitors are charged. When the control switch Q3 is in the open state, the first capacitor C1 is connected to at least one of the two boost converters through the control switch Q3, and the voltage at the first capacitor C1 is increased through the boost converter, so that it can charge the second capacitor C2, thereby increasing the time for the output voltage of the second capacitor C2 to be between the input range of D2D, increasing the time for the second capacitor C2 to discharge the load to keep the load operating normally, and also avoiding the cost increase and volume increase caused by setting Baby Boost in the prior art, and can also remove the loss caused by the inductance on the Baby Boost when the PFC is operating normally, thereby improving the efficiency of the PFC. In this embodiment, the capacity of the second capacitor C2 is less than twice the capacity of the first capacitor C1, thereby preventing inefficiency when the first capacitor C1 is used to charge the second capacitor C2. The control switch Q3 can be any one of MOSFET, IGBT, GaN or thyristor.

In the present embodiment, the boost converter is provided with two paths, including a first boost converter and a second boost converter connected in parallel with the first boost converter, and the first boost converter and the second boost converter are both the same type of Boost circuit or buck-Boost circuit, which can be determined according to actual needs and is not specifically limited here. The working principles of the Boost circuit or the buck-Boost circuit are both mature prior arts, and the present application does not improve their working principles, so they are not elaborated here. In the present embodiment, the first boost converter and the second boost converter are both Boost circuits, including an inductor and a boost switch tube having one end connected to the output end of the inductor.

The circuit for improving the holding time also includes an input switch module electrically connected to the input power supply Vin and the boost converter, the input end of the input switch module is electrically connected to the positive and negative poles of the input power supply Vin, the input ends of the first inductor L1 of the first boost converter and the second inductor L2 of the second boost converter are both connected to the positive pole of the input switch module, and the other ends of the first boost switch tube Q1 of the first boost converter and the second boost switch tube Q2 of the second boost converter are both connected to the negative pole of the input switch module. In this embodiment, the input switch module is a rectifier bridge, which is sealed together by four diodes D1, D2, D3, and D4 of a connected bridge rectifier circuit, and can realize the rectification of the AC power of the input power supply Vin into the DC power of the Boost circuit. The working principle and structural composition of the rectifier bridge are prior art, and this application has no improvement on it, which will not be repeated here. When the control switch Q3 is in the on state, the input switch module is in the blocking state to prevent the voltage input from the first capacitor C1 to the second capacitor C2 from being lost through the input switch module.

In other embodiments, the input switch module may be selected according to actual needs. For example, the input switch module may be a relay. As long as it can meet the actual needs, no specific limitation is made here.

The switch group includes a first switch tube D6 whose anode is connected to the output end of the first inductor L1 and whose cathode is connected to the positive electrode of the first resistor, and a second switch tube D7 whose anode is connected to the output end of the second inductor L2 and whose cathode is connected to the positive electrode of the second resistor. In this embodiment, both the first switch tube D6 and the second switch tube D7 are diodes. In other embodiments, the first switch tube D6 and the second switch tube D7 can also be selected according to actual conditions, such as MOSFET, IGBT or GaN, etc., which can be determined according to actual conditions and are not specifically limited here.

A first switch element D8 is also provided on the connection line between the first capacitor C1 and the second capacitor C2. In the present embodiment, the first switch element D8 is a slow diode. Since the reverse recovery time of the slow diode is relatively long, part of the energy in the second capacitor C2 will be fed back to the PFC circuit during the reverse recovery process of the slow diode, thereby reducing the loss of the entire PFC circuit.

The specific working process of the circuit for improving the holding time of the present application is as follows: when the input power supply Vin is operating normally, the first boost converter and the second boost converter are operating normally, the control switch Q3 is in a closed state, and the first capacitor C1 and the second capacitor C2 can be charged and stored through the surge protection component D5; after the input power supply Vin is suddenly powered off, the second capacitor C2 transmits electricity to the load through the D2D module for a period of time, at which time the control switch Q3 is in a conducting state, and the first capacitor C1 can form a Boost circuit through the control switch Q3 and the first boost converter, thereby boosting the voltage at the first capacitor C1, so that the electricity in the first capacitor C1 can be transmitted to the second capacitor C2, and then after the electricity of the first capacitor C1 is exhausted, the electricity in the second capacitor C2 continues to be used to supply the load until the output voltage of the second capacitor C2 is less than the input range of the D2D module, and the power supply to the load is stopped, thereby increasing the time of the output voltage of the second capacitor C2 between the input range of the D2D module through the above process, and increasing the time for the second capacitor C2 to discharge the load to maintain normal operation of the load.

In summary: the present application utilizes a boost converter in the original PFC to replace the Baby Boost that is additionally provided in the prior art, thereby improving the holding time while avoiding the increase in cost and volume caused by the provision of the Baby Boost, and can also eliminate the loss caused by the inductance on the Baby Boost when the PFC is working normally, thereby improving the efficiency of the PFC.

The above is only a specific implementation of the present application, and any other improvements made based on the concept of the present application are deemed to be within the protection scope of the present application.

Claims (7)

1. A circuit for improving holding time, suitable for connecting to an external load through a D2D module, characterized by comprising: A boost converter is provided with at least two paths, and at least two of the boost converter inputs are connected in parallel; Capacitors, at least two of which are provided, including a first capacitor and a second capacitor suitable for connecting to the D2D module, each of the capacitors being electrically connected to an output end of at least one of the boost converters; Also included is an input switch module electrically connected to an input power source and the boost converter; The boost converter includes a first inductor and a second inductor whose input end is connected to the positive electrode of the input switch module, and a first boost switch tube whose one end is connected to the output end of the first inductor and the other end is connected to the negative electrode of the input switch module; and also includes a second boost switch tube whose one end is connected to the output end of the second inductor and the other end is connected to the negative electrode of the input switch module; The boost converter also includes a first switch tube and a second switch tube, wherein one end of the first switch tube is connected to the output end of the first inductor, and the other end is connected to the positive plate of the first capacitor; one end of the second switch tube is connected to the output end of the second inductor, and the other end is connected to the positive plate of the second capacitor; A control switch is used to connect at least one input end of the boost converter to the positive electrode plate of the first capacitor; and A surge protection component connected in parallel with the control switch; The control switch has a closed state when the input power is normal and an open state when the input power is off. When the control switch is in the closed state, the two capacitors are charged; when the control switch is in the open state, the first capacitor charges the second capacitor. When the control switch is in the on state, the input switch module is in the blocking state; A first switch is provided on the connection line between the positive plate of the first capacitor and the positive plate of the second capacitor. 2. The circuit for improving the holding time according to claim 1, wherein the boost converter is a Boost circuit or a buck-Boost circuit. 3. The circuit for improving the holding time as claimed in claim 2, characterized in that the input switch module is a rectifier bridge or a relay. 4. The circuit for improving the holding time as claimed in claim 1, wherein the first switch element is a slow diode. 5. The circuit for improving the holding time as claimed in claim 1, wherein the capacity of the second capacitor is less than twice the capacity of the first capacitor. 6 . The circuit for improving the holding time according to claim 1 , wherein the control switch is one of MOSFET, IGBT, GaN or thyristor. 7. The circuit for improving the holding time according to claim 1, characterized in that the first switch tube and the second switch tube are both one of a diode, a MOSFET, an IGBT or a GaN.