JPS59186360A - Monolithic microscopic integrated circuit - Google Patents

Abstract

PURPOSE:To obtain the monolithic microscopic integrated circuit of uniform characteristics by a method wherein the FET part of which is divided into two parts, and one of which is used as a variable capacitor. CONSTITUTION:Gate fingers A(10A) and B(10B) are tied up in bundles of gate electrodes A(13A) and B(13B) respectively, and a bias circuit 17 for fine adjustment is connected to the electrode B(13B). Now, when the prescribed positive voltage is applied to a drain electrode 12 and when a voltage a little lower than said positive voltage is applied to the circuit 17, a capacitance is generated between the electrode B(13B), the electrode 12 and the source electrode B(11B) by having Schottky junction. Also, capacity is given in parallel to the FET which is formed by the finger A(10A), the electrode 12 and a source 11A. Accordingly, the irregularity of characteristics of the FET can be corrected by changing the voltage applied to the circuit 17, thereby enabling to adjust and make uniform the amplification characteristics.

Description

[Detailed description of the invention] This invention relates to a monolithic machine C.

FIG. 1 shows an example of a conventional monolithic MIC.2 Here, a small signal NET one-stage amplifier is taken as an example. (
l]Fi"aAs substrate, (2) is FKT section, (3) is input matching circuit, (4) is output matching circuit, (5) is gate bias circuit, 16) is drain bias circuit, (7) is ground Metal film, (8A), (8B) are MIM capacitors, (9A), (9B), (90), and (9D) are trishing parts. and output matching circuit (3) +4) Gate and drain bias circuit (51, +61° grounded metal film f
71. M engineering M capacitor A, B (8A), (
8B) using techniques such as photoengraving.

Here, the FET section (2) has the structure shown in FIGS. 3(a) and 3(b). Figure 3 (a) is a plan view of the FET section,
Figure (B) is a diagram showing the AA' cross section of Figure 3 (A). QO) is the gate finger, 0I) is the source electrode, 0 is the drain electrode, tl is the gate electrode, +14) is the via hole, and (C is the ground electrode).

A number of gate fingers 00) are connected to source electrodes (1, 11).
and the drain electrode uz.

They are bound together by a gate electrode 13).

The source electrode aD is grounded to the earth electrode a9 via a via hole 14) over a very short distance.

The input and output matching circuits +3) and +4+ in Figure 2 are usually determined as follows. The S' parameter was measured for a sample in which only the FET part was embossed as shown in FIG.

Find the average characteristics from a large number of foot measurement results. For this purpose, we also optimized the input and output matching circuits.

Determine electrical dimensions. Therefore, if F'ET is distributed at a location that deviates from the average characteristic, it naturally exhibits an amplification characteristic that deviates from the desired characteristic. This requires modification of the input and output matching circuits.

(9A) (9B) (9C) (9D) in Figure 2 are trimming parts where a part of the input and output matching circuits are cut with a laser beam, etc., and by modifying part of the 9 circuits, the desired However, this method uses heat to melt the metal on the aAS substrate and remove it, and the droplets of melted metal can cause damage to nearby FETs.
(2), etc., causing contamination.

This may lead to an accident such as a short circuit between the gate finger 00) and the north electrode α1 shown in FIG. Even if you try to make adjustments by peeling off the metal film with a cutter, etc., it is difficult to make accurate cuts.

The present invention provides a method for solving such problems.

The FBT section (2) in FIG. 2 is replaced with the one in FIG. 3.

Here, (10A) and (10B) are gate fingers A
,B.

(11A), (11:s) are source electrodes A and B
, (13A), (16B) are gate electrodes A, B, (
1f9 is a metal film for short circuiting, and the fin is a bias circuit for fine adjustment. Gate finger A (IOA) is connected to gate electrode A (13
In A), the gate fingers B (10B) are each bundled with the gate electrode B (13B). A fine adjustment bias circuit αD is connected to the gate electrode B (13B).

Here, M I is used to short-circuit the gate using microwaves.
M capacitor C (SC) is buried.

The source electrode p, (11A) is grounded to the earth electrode 05) by the bias hole α, as in the case of FIG. The source electrode B (11B) is connected to the drain electrode 0 through a short-circuit metal film 0e instead of being grounded.

Now, when a predetermined positive voltage is applied to the drain electrode (12) and a voltage slightly lower than the aforementioned positive voltage is applied to the fine adjustment bias circuit, the gate electrode B (16B), the drain electrode U, and the source electrode A capacitance is generated between the PET and B (11B) due to a 7-way junction.This means that a capacitance is introduced in parallel to the PET formed by the gate finger (10A), the drain electrode t12, and the source electrode (11A). Therefore, by changing the voltage applied to the fine adjustment bias circuit, variations in the characteristics of the FKT can be corrected, and the amplification characteristics can be adjusted and made uniform without physically changing the shape of the input and output matching circuits.

The above explanation was based on a FET + stage amplifier, but you can change the voltage applied to the fine adjustment bias circuit.

Since the output power can be varied, the circuit described above can also be used as a modulator. It is obvious that the FET section having such a structure can also be used as a FET switch or a FET phase shifter.

As described above, by dividing the FET section into two and using one of -C1 as a variable capacitance, it is possible to absorb variations in FET characteristics and obtain a monolithic MC with uniform characteristics.

[Brief explanation of drawings]

Figure 1 shows N as an example of a conventional monolithic MIO.
ET Front view of 1-stage amplifier, Figure 2 is 'E' in Figure 1
Detailed diagram of the F and T sections. FIG. 3 is a diagram showing the FET section of a one-stage FET amplifier showing an example of the present invention. here(
1) is GaAs substrate, (2) is FET section, (3) is input matching circuit, (4) is output matching circuit, (5) is gate bias circuit, (6) is drain bias circuit, (7) is ground Metal films (8A), (8B), and (8c) are MIM capacitors A. B, a, (qp,) (qB) (qc) (qD) is the trimming part, +10) is the gate finger, (I
DA) (1oB) is gate finger A. B, (11) is the source electrode, (11A) (11B) is the source electrode A. B, +13 is the drain electrode, (12A012B) is the train electrode A, B, (+3) is the gate electrode 1? ,
(13A) (13B) tri gate electrode A, B
, Q4) is a via hole (15) is a ground electrode. af9 is a metal film for short circuiting, and 07) is a bias circuit for fine adjustment. In FIG. 9, parts corresponding to the same 1 are designated with the same reference numerals. Agent Masuo Oiwa No. 1 Figure 2 (2) (a) 514

Claims (1)

[Claims] In a monolithic MC that includes a large number of unit FETs consisting of a source, gate, and drain, the drains of all unit FETs are connected to each other with metal, and the unit FE is divided into two groups.
The sources and gates of T are each connected by one metal within the group, the sources of one group are grounded, and the sources of the other group are connected to the drains by metal.
Monolithic M construction C8 characterized by including F and T