JPS59180666A - Calculating circuit of difference degree - Google Patents
Calculating circuit of difference degreeInfo
- Publication number
- JPS59180666A JPS59180666A JP58053610A JP5361083A JPS59180666A JP S59180666 A JPS59180666 A JP S59180666A JP 58053610 A JP58053610 A JP 58053610A JP 5361083 A JP5361083 A JP 5361083A JP S59180666 A JPS59180666 A JP S59180666A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- value
- adder
- complement
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
- G06F17/10—Complex mathematical operations
- G06F17/15—Correlation function computation including computation of convolution operations
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computational Mathematics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computing Systems (AREA)
- Data Mining & Analysis (AREA)
- Mathematical Physics (AREA)
- Algebra (AREA)
- Software Systems (AREA)
- Databases & Information Systems (AREA)
- Complex Calculations (AREA)
- Character Discrimination (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（１）発明の技術分野
本発明は２つの非負の値の絶対値の累積オロを求める相
違［Ｗ計算回路に関するものである。DETAILED DESCRIPTION OF THE INVENTION (1) Technical Field of the Invention The present invention relates to a difference [W calculation circuit for calculating the cumulative value of the absolute value of two non-negative values.
（２）従米独術と問題点
例えば音声認識等の分野において２つの成形の類似度を
求める場合ＶＣ２つの波形の対応する非負の値ＡｉとＢ
ｉの差の絶対値ｌＡ１−Ｂ１１を求めこれを各点ＶＣつ
いて累積した累積和。Σ１Ａｉ−Ｂｉｔ１＝１
−１
を用いることが行なわれる。(2) Problems with American-American-German techniques For example, when determining the similarity of two shapes in the field of speech recognition, the corresponding non-negative values Ai and B of the two VC waveforms
A cumulative sum obtained by calculating the absolute value lA1-B11 of the difference between i and accumulating this for each point VC. Σ1Ai-Bit1=1
−1 is used.
この目的に用いられる従来の回路を第１図に示す。第１
図において１は比較器、２は選択回路、３は補数回路、
４は選択回路、５および６は加算回路、７はレソスタで
ある。第１図の回路において比較器１は入力する値Ａｉ
およびＢｉの大小を比較してその大小の情報を選択回路
２および４に送る。選択回路２は入力値Ａｉ ｓ Ｂｉ
をそのま＼入力し、選択回路４は補数回路３を介して入
力値Ａｉ、Ｂｉの１の補数値肩および酊 を入力する。A conventional circuit used for this purpose is shown in FIG. 1st
In the figure, 1 is a comparator, 2 is a selection circuit, 3 is a complement circuit,
4 is a selection circuit, 5 and 6 are adder circuits, and 7 is a resistor. In the circuit of FIG. 1, comparator 1 has an input value Ai
and Bi, and sends information on the magnitude to the selection circuits 2 and 4. The selection circuit 2 selects the input value Ais Bi
are input as they are, and the selection circuit 4 inputs the one's complement values of the input values Ai and Bi through the complement circuit 3.
比較器１がＡｉ＜Ｂｉであると判定した場合は選択回路
２は大きい方の値Ｂｉを出力し、選択回路４は小さい方
の値Ａｉの１の被数凋 を出力し両方の値と値ｌは加算
回路５において加算されその値ＩＡｉ−Ｂｉｔはつぎの
加算回路６に送られる。加算回路６においては加算回路
５の出力値とレヅスタ７に蓄積された値を加算してレノ
スタフに送る。When the comparator 1 determines that Ai<Bi, the selection circuit 2 outputs the larger value Bi, and the selection circuit 4 outputs the decimal point of 1 of the smaller value Ai, and selects both values. l is added in an adder circuit 5, and the value IAi-Bit is sent to the next adder circuit 6. In the adder circuit 6, the output value of the adder circuit 5 and the value accumulated in the register 7 are added together and sent to the Renostaph.
ｌ ＡＩ Ｂｌ ｌをレノスタフに送る前に信号Ｃ
ＩＪＡＲによシレソスタ７の値を０にしておけばレノス
タフの出力には＄積和、ΣｌＡ１Ｂ１１ が得られｌ＝
１
る。l AI Bl Signal C before sending l to Lenostav
If you set the value of the sire so star 7 to 0 using IJAR, you will get $ product sum, ΣlA1B11 in the output of Renostaph, and l=
1.
第１図のごとき従来の相違度計算回路においては比較器
や選択回路等回路部品の点数が多くな９回路が複雑且つ
冒価なものとなる。In the conventional dissimilarity calculation circuit as shown in FIG. 1, the nine circuits have many circuit parts such as comparators and selection circuits, making the circuit complex and expensive.
（３）発明の目的
本発明はか＼る従来技術の欠点にかんがみ選択回路や比
較器を有することなく筒片な回路構成によシ冥現できる
相違度計算回路を提供することを目１’１勺とする。(3) Purpose of the Invention In view of the drawbacks of the prior art, it is an object of the present invention to provide a dissimilarity calculation circuit that can be realized with a simple circuit configuration without having a selection circuit or a comparator. 1 person.
（４）発明の構成
この目的は本発明によればＡｉとＢｉなる２つの非負の
値の差の絶対値ｌＡｉ Ｂｉｌの総和、Σ１Ａｉ−−
１
Ｂｉｌを求める回路において、値Ａｉと値Ｂｉの１の補
数百１ を加算回路によシ加算を行ない、該加算回路の
出力にあられれるキャリーにより前記ＡｉおよびＢｉＯ
値の大小を判定してその計算結果より累積和Σ１Ａｊ−
Ｂｉｌを求めることを特徴とす１−す
る相違度計算回路を提供することによって達成さオＬる
。(4) Structure of the Invention According to the present invention, the purpose is to obtain the sum of the absolute value lAi Bil of the difference between two non-negative values Ai and Bi, Σ1Ai--
In the circuit for calculating 1 Bil, the value Ai and the 1's complement 101 of the value Bi are added together in an adder circuit, and the Ai and BiO are added by the carry at the output of the adder circuit.
Determine the magnitude of the value and use the calculation result to calculate the cumulative sum Σ1Aj−
This is achieved by providing a dissimilarity calculation circuit that is characterized by calculating Bil.
（５） 発明の実施例
以下本発明にか＼る回路の実施’ｖ弓について詳細に説
明する。(5) Embodiments of the Invention The implementation of the circuit according to the present invention will now be described in detail.
い捷２種類の値をＡｌｔ 、Ｂｔとしこれら（ｌ″ｉｎ
ｉｎピノ絶対値表現されたものとすると、０＜Ａ１＜２
−１ ｆｌｌＯ≦Ｂｌに２ −１
１２１またＢｉ の各ビットの０．
１を反転したもの（１の補数）をＢｉ で表わすと
Ｂｉ＝（２−１） Ｂｉ ｔ、３１
となる。こ＼にＤｉ＝ｌＡｉ −Ｂｉ ｌとすると第（
３）式％式％
（４）
）
（５）
ここでＡｉ十Ｂｉの演算ヲ考えるとＰＪ（３１式よりＡ
ｉ＋Ｂｉ＝２ｎ １士（Ａｊ Ｂｉ） （
６）であるから、
（１） Ａｊ＞Ｂｉのと＠は
Ａｊ−Ｂｉ）Ｏｌつ捷りＡ１−Ｂ１〉１であるから第（
６）式より
ＡｌｔＢｉ＞２
となりｎビットの演算を行なうとキャリー（桁上り）が
発生する。Let the two types of values be Alt and Bt, and these (l″in
If expressed in pinot absolute value, 0<A1<2
-1 flIO≦Bl 2 -1
121 and 0.121 of each bit of Bi.
If the inverted version of 1 (1's complement) is expressed as Bi, then Bi = (2-1) Bi t, 31
becomes. If we set Di=lAi −Bi l, then the (
3) Formula % Formula % (4) ) (5) Here, considering the calculation of Ai + Bi, PJ (from formula 31, A
i+Bi=2n 1st person (Aj Bi) (
6), so (1) Aj>Bi and @ are Aj-Bi)Ol and A1-B1>1, so the (th)
From equation 6), AltBi>2, and when n-bit operations are performed, a carry occurs.
（ｆｉｌ Ａｉ≦Ｂｉのときは
この関係と第（１）式、第（２）式よシー（２ｎ−１）
＜Ａ１−Ｂ１＜０
であるから冴」、（６）式より
０＜Ａｉ＋Ｈｉ≦２−１
となりｎビットの演算を行なうとキャリー（桁上り）が
発生しない。(fil When Ai≦Bi, this relationship, equation (1), equation (2), C(2n-1)
<A1-B1<0, so from equation (6), 0<Ai+Hi≦2-1, and when n-bit operations are performed, no carry occurs.
ＩＴってＡｉ十酊ニよるキャリーでＡｉ、Ｂｉの大小！
１４Ｉ定ができる。IT is a carry that depends on Ai and Bi, and the size of Ai and Bi!
14I can be determined.
そこでＡｉ ＋ ］３ｉの演算によるキャリーをｃｉ
としこれをｎビット並べた数値をＣＩ とすると（
Ａ） Ａｉ＞Ｂｉのとき第（４）式および（１）より
０１−１であるので
Ｄｉ＝＝Ａｉ＋Ｂ１−２ｎ＋１＝Ａｉ＋Ｂｉ＋１＝（Ａ
ｉ士Ｈｉ）ｅ、）Ｃｉ士ｃｉ（７）
第（７）式において−２は下位ｎビットはオール“０″
であるからｎビット′ＬＡ算では無お２し、てよい。Therefore, the carry by the operation of Ai + ]3i is ci
If the number obtained by arranging n bits is CI, then (
A) When Ai>Bi, it is 01-1 from equation (4) and (1), so Di==Ai+B1-2n+1=Ai+Bi+1=(A
ishiHi)e,)Cishici(7) In equation (7), -2 means that the lower n bits are all “0”
Therefore, n-bit 'LA calculation can be done without any problem.
ｔＢ） Ａｉ（：Ｂｉのときは第・５）式および（１
１）よｐｃｉ二〇であるので
〈
１）ｉ ＝ （Ａｉ十Ｂｉ）［有］Ｃ１−１０ｉ
ｔ９）となる。こ＼に■は２数の対応する
ビットの排他的論理λ［１を意味する。tB) Ai (:When Bi, the fifth) formula and (1
1) Since pci is 20, < 1) i = (Ai 10 Bi) [Yes] C1-10i
t9). Here, ■ means exclusive logic λ[1 of two corresponding bits.
つさ゛に本発明の実施例を第２図に示す。An embodiment of the present invention is briefly shown in FIG.
４２図において８は補数回路のインバータ群、９は加算
器、１０はインバータ、１１は排他論理来日・洋、１２
はカ目算著、−，，１３はレノスタをそれぞれ示す。In Figure 42, 8 is the inverter group of the complement circuit, 9 is the adder, 10 is the inverter, 11 is the exclusive logic, 12
The letters ``Kame Sansho'' and ``-,'' and 13 indicate "Renosta," respectively.
記２図の回路において入力データＡｉ 、 Ｂｉはクロ
ック（ＣＬｏＣＫｉ）に同期してその１直が変る。筐た
最初の入力データＡ、 、 Ｂ、の入力以前にｖ−）ヌ
タ１３はクリア（０ＬＥＡ１．ｔｌ、 ）によシフリア
して訃く。In the circuit shown in FIG. 2, the input data Ai and Bi change in synchronization with the clock (CLoCKi). Before inputting the first input data A, , B, v-) Nuta 13 clears (0LEA1.tl, ) and dies.
入力データＢｉ はインバータ＃８にそシその補数値π
１ に変換される、この値頂 と入力データＡｉ は加
Ａ器９によシ加算される。加算器９の出力がＡｔ ＋頂
と桁上りＣ１となるとインバータ１０と排他論理オロ群
１１によシ゛（Ａｉ十百Ｄり百が出力される。その出刃
は加算器１２に送られレジスタ１３の出力５ｉ−１と（
Ａｔ士■）■函とＯｉが加算されるので
Ｓｉ−＋ 十（Ａｉ −１−Ｊ３ｉ ）■Ｃｉ十Ｏｉが
出力される。これをレジスタ１３で捉えてＳｌを出力す
る。すなわち
５ｉ＝Ｓｉ＝１・＋（Ａｉ ＋ Ｂｉ ） ＯＣｉ ＋
０ｉ＝Ｓｉ−１＋ｌ Ａｔ −Ｂｉ ｔ （第（９）
式による）レジスタ１３は予めクリアされているのでＳ
。二〇であるから
となる。Input data Bi is input to inverter #8 and its complement value π
This value Ai, which is converted to 1, and the input data Ai are added by an adder 9. When the output of the adder 9 becomes At + top and carry C1, the inverter 10 and the exclusive logic group 11 output Ai100D minus 100.The output is sent to the adder 12 and stored in the register 13. Output 5i-1 and (
Since Atshi (■)■box and Oi are added, Si-+ 10(Ai-1-J3i)■Ci0Oi is output. This is captured by the register 13 and outputted as Sl. That is, 5i=Si=1・+(Ai + Bi) OCi +
0i=Si−1+l At −Bi t (No. (9)
Since register 13 (according to the formula) is cleared in advance, S
. This is because it is twenty.
第３図は不され明の他の実施例を示す。第３図において
インバータ井１４、加算器１５．１９、レジスタ２０は
それぞれ第２図の８．９．１２および１３と同じである
。たソ第２図と異なるところｒよレジスタ１６か刀口わ
ったことである。この実施レリ９こおいてはなも２図の
ぢ“、合に比べてクロックの周Ｊｌをよシ早くできる。FIG. 3 shows another embodiment of the present invention. In FIG. 3, inverter well 14, adder 15, 19 and register 20 are the same as 8.9.12 and 13 in FIG. 2, respectively. The difference from Figure 2 is that the register 16 has been changed. In this case, the clock frequency Jl can be made much faster than in the case shown in Figure 2.
最小周期は入力Ａｔ 、 Ｂ１７５；仰足し期］算器１
５の出力が確定する１での１寺間Ｔｉとレジスタ１６の
値が４’ｊｉ定してから加算器１９の出力する捷での時
間Ｔ２ の大きい方の値Ｕ、’ ＝ ｍａｘ （Ｔ、
、 Ｉ２ ）により決まる。The minimum period is input At, B175; exaggeration period] Calculator 1
The larger value U,' = max (T,
, I2).
丑だレジスタ１６を加′σ器１５の直後に置かず加′ｓ
、器１９の直前に１４＜ことも可能である。Addition register 16 should not be placed immediately after adder 15.
, 14< just before the vessel 19 is also possible.
（６） 発明の突ノ果
以上詳細に説明したように、本発明によれば従来技術に
比較して１ン６単な回路で実現できしかも年号の通過ダ
ート数が少ないのでクロックを速くすることができるの
で製品が安価にでき且つ高速演算が可能であるという効
果がある。(6) Outcomes of the Invention As explained in detail above, according to the present invention, compared to the prior art, it can be realized with a 1-6 simple circuit, and the number of passing darts of the year number is small, so the clock speed can be increased. This has the advantage that the product can be manufactured at low cost and high-speed calculation is possible.
第１図は従来の相違＋６１泊算回路の１し１］のブロッ
ク図、第２図は本発明にか＼る相違度計算回路の１実施
例のブロック図、第３図は本発明にか＼る他の実施例を
示す。
図面において
８、Ｉ４・・・インバータ計、９，１２．１５゜１９・
・・力Ｄ′く慴￥：Ｊ、１０．１７・・・インバータ、
１１゜１８・・・排イ１！；論理和群、１３．Ｉ６．．
２０・・・レジスタをそれぞれ示す。
特許出願人
富士通株式会社
を時許出願代理人
弁理士 青 木 朗
弁１里士 西 舘 和 之
づ「埋土 内 １） 幸 男
弁理士 山 （コ 昭 ｌ
３５Fig. 1 is a block diagram of a conventional difference + 61 night calculation circuit, Fig. 2 is a block diagram of an embodiment of a dissimilarity calculation circuit according to the present invention, and Fig. 3 is a block diagram of an embodiment of a dissimilarity calculation circuit according to the present invention. \Other examples are shown below. In the drawing, 8, I4...Inverter total, 9,12.15°19.
・・Power D'kuei ¥: J, 10.17...Inverter,
11°18...Excretion 1! ; disjunctive group, 13. I6. ．．
20...Represents each register. Fujitsu Limited, the patent applicant, is represented by Patent Attorney Aoki Roben 1, Roshi Nishidate Kazunozu (1) Yukio Patent Attorney Yama (Ko Sho 35)
Claims (1)
ｉｔの総和、Σ１Ａｉ−Ｂｉｌｉ求める回路において、
ｌ：１ 値Ａｔ と値Ｂｉ の１の補数Ｂｉ を加算回路に
よシ加′Ｊ！、′ｔ−行ない、該加算Ｂｉ路の出力にあ
られれるキャリーにより前記Ａｉ およびＢｉ の値
の大小を判定してその計算結果より累積和、Σ１Ａｉ−
Ｂｉｌを１＝１ 求めることを特徴とする相違度計算回路。[Claims] Absolute value IAi-B of the difference between two non-negative values Ai and Bi
In the circuit that calculates the sum of it, Σ1Ai-Bili,
l:1 Add the 1's complement Bi of the value At and the value Bi to the adder 'J! , 't- is carried out, and the magnitude of the values of Ai and Bi is determined based on the carry present in the output of the addition Bi path, and from the calculation result, the cumulative sum, Σ1Ai-
A dissimilarity calculation circuit characterized by calculating Bil as 1=1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58053610A JPS59180666A (en) | 1983-03-31 | 1983-03-31 | Calculating circuit of difference degree |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58053610A JPS59180666A (en) | 1983-03-31 | 1983-03-31 | Calculating circuit of difference degree |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59180666A true JPS59180666A (en) | 1984-10-13 |
Family
ID=12947665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58053610A Pending JPS59180666A (en) | 1983-03-31 | 1983-03-31 | Calculating circuit of difference degree |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59180666A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50152632A (en) * | 1974-05-27 | 1975-12-08 | ||
| JPS55121483A (en) * | 1979-03-07 | 1980-09-18 | Ibm | Absolute difference generation mechanism |
-
1983
- 1983-03-31 JP JP58053610A patent/JPS59180666A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50152632A (en) * | 1974-05-27 | 1975-12-08 | ||
| JPS55121483A (en) * | 1979-03-07 | 1980-09-18 | Ibm | Absolute difference generation mechanism |
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