JPS59165088A - Matrix array for thin film transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION 111 The present invention relates to a 7-trix array of thin film transistors, and more particularly, to a 7-trix array of thin film transistors that can be applied to switching elements of a liquid crystal display panel.
It concerns arrays.

``Ll'' Conventionally, the WII11 transistors that drive and control each pixel in matrix display devices, etc.
When forming an array, as in Japanese Patent Laid-Open No. 54-154289, an insulating layer is formed between the interconnections at the intersection of the vertical interconnection and the horizontal interconnection, so that the interconnections can be separated from each other. Make sure not to connect electrically. Therefore, the thin film transistor is provided at a position laterally shifted from the intersection of the horizontal wiring and the vertical wiring. Therefore, the number of manufacturing steps is relatively large, and when applied to switching elements such as liquid crystal display panels, one Rl1jl t" transistor is provided for each pixel, but IJI
It is difficult to reduce the area occupied by the I-transistor relative to the pixel, and there is a problem in improving the resolution in display.

Purpose The present invention has been made in view of the above points, and it simplifies the manufacturing process of a matrix array of thin film transistors, and also reduces the number of thin film transistors for one pixel when used as a switching element for a liquid crystal display panel or the like. Reduce the occupied area and display the resulting height @
The purpose of the present invention is to provide a matrix array of Wl film t'' transistors that can be used to increase

Configuration The configuration of the present invention will be described below based on examples. 1 is a plan view of a 7-trix array of thin film transistors according to the present invention used as a switching element of a liquid crystal display panel 1, and FIG.
= A sectional view taken along the I line. LCD display panel 1
A matrix is formed by dividing a glass substrate 1a into pixels each having a transparent electrode film 1b having a predetermined shape, and each pixel is provided with one thin film 1 and one transistor 2. The first arrangement a12a forms the gate electrode 28' in the thin film transistor 2 and interconnects the thin film transistors 2 in each pixel in the lateral direction. -.j On the other hand, the second wiring 2b forms a source electrode 2b- in the thin film transistor 2, and also vertically interconnects the thin film transistors 2 in each pixel. First wiring 2a
Examples of the material include NiCr, Ivlo,
Using Aj+ etc. to a film thickness of 2,000 to 3,000 people,
The second wiring 2b is made of, for example, NiCr or Mo.

It is preferable to form the film using Aj2 or the like to a thickness of 1 pm by a known vapor deposition or sputtering method. In the region 4 where the first wiring 2a and the second wiring 2b intersect, an insulating layer 2 is interposed between both front lines.
0 and a semiconductor layer 2d are formed, and the semiconductor layer 2d
A drain electrode 2e is provided so as to overlap the electrode film 1b. That is, in region 4, an insulating layer 2C is formed on the first wiring 2a (gate electrode 2a-), a semiconductor layer 2d is formed on it, and a second wiring 2b is further formed on it.
(The source electrode tffi2bi and the drain electrode 2e are formed to constitute the thin film transistor 2.A particularly preferred embodiment for forming the semiconductor layer 2d and the insulating layer 2C below it is shown in FIG. As shown, it is preferable to form it in a self-aligned manner, and when such a structure is adopted, the manufacturing process is simplified as described later.Insulating layer 2C
is, for example, St 3 N4.

S i 02, S I ONW 2 film 713,0
In addition, the semiconductor layer 2d is made of, for example, a-3i (amorphous silicon) or polycrystalline silicon with a film thickness of 3.0
It is preferable to form the film by a glow emission 1cVD method, an atmospheric pressure CVD method, or the like, which is well known in the art. Note that the drain ffft1j2e is created by forming a button from the second wiring 2b.

Another glass substrate 1d has a transparent electrode film 1e formed on its entire surface, and this glass substrate 1d and the glass substrate 1
A liquid crystal is sealed between the

The electrode film 1b and the electrode film 1e are preferably formed of, for example, ITO or the like to a thickness of 2,000 yen by a known sputtering method. The first distribution F2a and the second distribution on the glass substrate 1a! 2b extends to the peripheral edge of the liquid crystal display panel 1 and is connected to an external drive circuit l\, respectively. iv? which is provided in a desired pixel by applying a signal to the first arrangement 2a and the second wiring 2b from an external drive circuit. By selectively driving the membrane transistor 2, the electrode film 1b of each pixel is charged through the drain qlf2c of the group membrane transistor 2, and an electric field is generated between it and the opposing electrode film 1e (usually set at ground potential). Then, the display state of the liquid crystal 1C is controlled by I11. Regarding the layer formation of the thin film transistor 2, a second arrangement 121) (source electrode 2b') and a drain electrode 2e are formed on the glass substrate 1a, then a semiconductor layer 2d is formed, and an insulating layer 2C is formed thereon. It is also possible to cover the structure in the order of forming the first wiring 2a (gate electrode 2a') and finally forming the first wiring 2a (gate electrode 2a'), and a cross-sectional view in that case is shown in FIG. 3 for reference. In addition, in FIG. 2, after forming the thin film transistor 2,
Protective passivation film 1f (see Figure 17)
and a light shielding II for blocking light at the thin film transistor 2 part.
(If (see FIG. 19)) is formed.

Next, an example of the manufacturing process for the glass substrate 1a on which the thin film transistor 2 is integrated will be described with reference to FIGS. 4 to 19. First, as shown in FIGS. 4 to 6, a glass substrate 1
A as a transparent conductive film 1b, ITOfl is sputtered onto Il! The pixel pattern is formed to a thickness of 2,000 mm, etched and etched using a photomask button, and etched using the resist shown in FIG. 3A as a mask to form a pixel pattern of a predetermined shape. Here, the resist 1 layer 3a is removed.

Next, as shown in FIGS. 7 to 9, the first wiring 2a
As the gate electrode 2a-, a NiCr film is formed to a thickness of 2,000 yen by vapor deposition or sputtering, and etching is performed using the resist layer 3b etched with a photomask button as a mask to form a predetermined first wiring 2a.
and the gate electrode 28'. Here, the resists 1-1m and 3b are removed. Next, as shown in Figs. 10 and 11, 5fOz is used as the insulating WA2C.
The film thickness was 3,000 mm using the D method (film forming temperature 350°C).
Furthermore, an a-8i film (amorphous silicon film) is formed thereon as a semiconductor layer 2d to a thickness of 3,000 yen by the PCVD method (film formation temperature: 350 DEG C.). Thereafter, as shown in FIGS. 12 and 13, the semiconductor layer pd is first etched using the resist 1m3c etched by the photomask pattern as a mask.
(7) The insulating layer 2C is further etched using a different etching solution for four rows of etching to form a pattern corresponding to region 4 in FIG.

Here, the resist ll3c is removed.

Next, as shown in FIGS. 14 to 16, a resist layer 3d is formed and etched using a photomask pattern, and then Aβ is evaporated to form a second electrode 112b (source electrode 2b') and a train electrode t12e, and the film thickness is After forming the resist layer 3d to a thickness of 1 μm, the resist layer 3d is removed and a lift-off method is applied.
A button for the second wiring 2b, a button for the source electrode 2b-, and a button for the drain electrode ti2e are formed.

Next, as shown in FIGS. 17 to 19, 813N4 is formed as a passivation film 1 by evaporation or sputtering to a thickness of 3,000, and a resist layer 3e is formed thereon.
After forming and etching with a photomask pattern, NiCr is deposited to a thickness of 2,000 as a light-shielding film 1g, and the resist@3e is removed by lift-off method to form a light-shielding film 11 (+ button).

In the conventional structure shown in FIG. 20(b), the semiconductor layer 2d of the thin film transistor is disposed laterally offset from the intersection of the first wiring 2a and the second wiring 2b. In order to obtain electrical separation between the wiring in both directions, it is necessary to form an insulating layer 2C between both door wires.
A special mask and photolithography process are required for this purpose. Incidentally, even if the insulating layer 2C interposed between both door lines remains entirely, at least the drain electrode 2e of the thin film transistor 2 and the pixel electrode Il! Since it is necessary to open a contact ball in the insulating layer 2C for electrical connection with J1b, a special mask and photolithography process are also required for this purpose. In the present invention, the 20th (a)
As shown in the figure, since the semiconductor layer 2d is interposed between both door lines at least at the intersection of both front lines, the same mask can be used to form the semiconductor layer 2d and the insulating layer 20. In this case, since the electrode film 1b of the pixel is exposed, there is no need to form a contact ball for electrically connecting the drain electrode 2e and the electrode film 1b. That is, as shown in FIG. 2, the semiconductor layer 2d and the insulating tFJ
2c is formed in a self-aligned manner, and one mask and 74 trilithography steps are omitted compared to the conventional method. Furthermore, by forming the thin film transistor 2 at the intersection of the first wiring 2a and the second wiring 2b, the area occupied by the thin film transistor 2 for one pixel is reduced from FIG. 20(b) to FIG.
a) It becomes smaller as shown in the figure. Figure 20 <8) shows the case of a matrix array of thin film transistors of the present invention,
FIG. 20(b) shows the conventional case.

Effects As described above, according to the present invention, the process of forming the semiconductor layer and the insulating layer, which conventionally required two photomasks in a thin film transistor matrix array, can be performed using one photomask. This can be done by using a mask and changing only the etching solution. As a result, the manufacturing process is simplified, manufacturing costs are reduced, and the yield is improved because mask alignment only needs to be done once. Furthermore, when applied to a switching element of a display panel such as a liquid crystal or EL, the area occupied by a thin film transformer or transistor for one pixel can be made smaller than that of the conventional method, so that it is possible to improve the WI image quality. The present invention is applicable not only to liquid crystal displays, but also to the display of images by selectively turning on and off a plurality of electrodes arranged in a 71 to 60-square shape to selectively emit light or absorb light on the screen. It goes without saying that the present invention can be applied to any driver 1 to matrix type display device that performs display.

[Brief explanation of the drawing]

FIG. 1 is a plan view of a liquid crystal display panel 1 using a matrix array of thin film transistors according to the present invention, and FIG.
The figure is a sectional view taken along the line I--I in FIG. 1. Figure 3 shows
3 is a cross-sectional view showing a reference example in which the order of layer formation is reversed with respect to the structure of the thin film transistor in FIG. 2. FIG. 4 to 19 are cross-sectional views for explaining one example of the manufacturing process of the liquid crystal display panel 1. FIG. 20(a) and 20(b) show ri for one pixel! Il! 1~
FIG. 4 is a reference diagram for comparison showing the area occupied by transistors in a conventional case and a case according to the present invention, respectively. 7 intervals (explanation of symbols) 1: Liquid crystal display I Neu panel 2: Thin film 1 transistor 2a: First wiring 28': Gate electrode 2b=
Second wiring 2b-: Source electrode 2C: Insulating layer 2d: Semiconductor layer 2e: Drain electrode la, same: Glass curtain plate 1b, Ie: Transparent electrode film IC = Liquid crystal 1f: Passion film 1g = Light shielding film 1\ '1 Applicant Riko Co., Ltd.
Tadashi Kohashi
10th 1st 1st! 11th 12th 1st r 131st 1d Figure 14d Figure 15th Figure 16th Figure 17th Figure 18th Figure 2b Figure 19th Figure 20(b) Figure b

Claims (1)

[Claims] 1.4-a+-first interconnecting transistors laterally
In a matrix array of thin film transistors having a second wiring vertically interconnected with the wiring, the thin film transistor has a source electrode, a drain electrode, and a semiconductor film, and the semiconductor film is connected to at least the first wiring. A matrix array of thin film transistors, characterized in that the thin film transistors are interposed between both wirings at the intersection with the second wiring.