JPS59164244U - Hybrid IC package - Google Patents
Hybrid IC packageInfo
- Publication number
- JPS59164244U JPS59164244U JP5905983U JP5905983U JPS59164244U JP S59164244 U JPS59164244 U JP S59164244U JP 5905983 U JP5905983 U JP 5905983U JP 5905983 U JP5905983 U JP 5905983U JP S59164244 U JPS59164244 U JP S59164244U
- Authority
- JP
- Japan
- Prior art keywords
- hybrid
- package
- resin
- framework
- board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のハイブリッドＩＣパッケージ例を示す側
断面図、第２図は本考案パッケージ実施例を示すハイブ
リッドＩＣ正面図、第３図は第２図のＡ部拡大斜視図、
及び第４図は第２図指標線Ｓ−Ｓ切断の断面図である。
図中、１はセラミック基板又は基板、２は個別部品、３
はケース、４は外部端子、５と６は枠組体のＬ形アング
ル、７は１の電極、及び８はＬ形アングル枠組体内基板
面である。FIG. 1 is a side sectional view showing an example of a conventional hybrid IC package, FIG. 2 is a front view of a hybrid IC showing an embodiment of the package of the present invention, and FIG. 3 is an enlarged perspective view of section A in FIG.
4 is a sectional view taken along the index line SS in FIG. 2. In the figure, 1 is a ceramic substrate or substrate, 2 is an individual component, and 3
1 is a case, 4 is an external terminal, 5 and 6 are L-shaped angles of the frame body, 7 is an electrode of 1, and 8 is a board surface inside the L-shaped frame body.
Claims (1)
脂被着をなすパッケージ構成に於いて、Ｌ形アングルを
基板の四方側面に設けて樹脂注入の枠組体を形成し、該
枠組体内に樹脂を注入することを特徴とするハイブリッ
ドＩＣのパッケージ。In a package configuration in which a hybrid IC board on which individual components are mounted is coated with an exterior resin, L-shaped angles are provided on the four sides of the board to form a framework for resin injection, and the resin is injected into the framework. A hybrid IC package that is characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5905983U JPS59164244U (en) | 1983-04-20 | 1983-04-20 | Hybrid IC package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5905983U JPS59164244U (en) | 1983-04-20 | 1983-04-20 | Hybrid IC package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS59164244U true JPS59164244U (en) | 1984-11-02 |
Family
ID=30189319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5905983U Pending JPS59164244U (en) | 1983-04-20 | 1983-04-20 | Hybrid IC package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59164244U (en) |
-
1983
- 1983-04-20 JP JP5905983U patent/JPS59164244U/en active Pending
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