JPS59163653A - Debug device - Google Patents

Abstract

PURPOSE:To avoid the generation of a useless break operation and to improve the debug efficiency by performing the break operation only in case the data of the prescribed value is written to a specific address of a memory of an actual device computer system. CONSTITUTION:A data bus 12, an address bus 13 and a control bus 14 are connected to a processor 11 of an actual device computer 10. Then a multiplexer 3, a comparator 5 and a break point control circuit 7 of a debug device 1 are connected to the buses 12-14, respectively. An AND gate 8 is connected to the output side of the multiplexer 3 via a bit map memory 4, and at the same time the memory writing signal sent from the bus 14 and the output of the comparator 5 are applied to the gate 8. The break point detection signal sent from the gate 8 is applied to the circuit 7 and a processor 2. Then a break operation is performed by the circuit 7 only when the data of the prescribed value is written to a specific address of the memory 4. Thus a useless break operation is prevented to improve the debug efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of the Invention) The present invention relates to a debugging device for debugging a device in which a processor such as a microprocessor is mounted, and in particular, the present invention relates to a debugging device for debugging a device equipped with a processor such as a microprocessor. The present invention relates to a debug device that performs a break operation when a write is performed.

(Background of the Invention) A break function provided in a conventional debug device mainly performs a break operation such as stopping an actual computer system when any of the following conditions is satisfied.

A1 When an instruction at a specific address in the memory of an actual computer system is executed When data at a specific address in the memory of a Bs8m computer system is referenced In such a conventional device, 1. A break under condition B above is performed only when data at a specific address is referenced, and the contents of the data are not used as a basis for determining the break condition; only the address where the data is stored is considered as the break condition. was. Therefore, in the conventional type, even when a break is required only when the data stored at a specific address in the memory of the actual computer system is one or more predetermined values, the break is made under condition B above. Since it is manually determined whether or not the reference Aviles data is at the predetermined value, there is an inconvenience that an extra break occurs and debugging efficiency deteriorates.

(Object of the invention) In view of the problems in the conventional type described above, the object of the present invention is to
In a debugging device that has a break function, the break operation is performed only when data of a predetermined value is placed in a specific address of the memory of the actual computer system, thereby preventing the occurrence of unnecessary breaks and improving debugging. The goal is to improve efficiency.

(Structure and Effects of the Invention) The present invention is based on the concept of providing a single-core debugging device with a bitmap memory that uses a data signal on a data bus of an actual computer system as an address in a debugging device having a break function. By using such a concept, it becomes possible to perform a break operation only when data with a predetermined value is written to the memory of a real computer system, thereby avoiding unnecessary breaks. The occurrence of this problem is prevented and debugging efficiency is improved.

(Explanation of Implementation Criteria) The present invention will be described in detail below with reference to the drawings. Fig. 1 shows a schematic configuration of a debugging device according to an embodiment of the present invention. In the figure, a debugging device 1 includes a processor 2, a processor 2, Multiplexer 3, bitmap memory 4, ratio 1 bit circuit 5
, register 6, breakpoint control circuit 7,
It is composed of AND gate 8 and the like. Also, an actual computer 10 that executes a program to be debugged.
includes a processor 11 and a memory (not shown). The debug device 1 is connected to the real computer 10 through a data/bus 12, an at9/res node 13, a control bus 14, etc., which are connected to the processor 11 of the real computer 10. If the processor 11 of the actual computer 10 is 8 bits, the bitmap memory 4 has a storage capacity of, for example, 256.times.1 bit. The address input of the bitmap memory 4 is connected via the multiplexer 3 to the data bus 12 of the real computer 10 or to the address 15 connected to the processor 2 of the differential gear device 1. The register 6 stores the address value to be broken, and the comparison circuit 5 compares the contents of the register 6 with the data on the Aviles bus 13 of the actual computer 10. Address data is written to the register 6 from the processor 2 via the data bus 16 of the debug device 1.

The operation of the apparatus shown in FIG. 1 will be explained with reference to FIG. O(
The controller first inputs the address 1 and data 1 to be broken into the processor 2 of the debugging device via a keyboard (not shown). Processor 2 stores the address value to be broken via data bus 16 in accordance with this input information. In addition, a data value to be broken is input to the address input of the bitmap memory 4 via the address bus 15 and the multiplexer 3, and the bit at the address represented by the data value is turned on, for example '1'.
''. At this time, bits other than the specified one are off, for example, O
11. If there are multiple data values to be broken, the bits at multiple addresses in the bitmap memory 4 are respectively turned on. Next, the actual computer 1
0 causes the program to be debugged to be executed. As a result, address values and data values appear on the address bus 13 and data bus 12 of the actual computer 10, respectively, in accordance with each instruction of the program.

In the debugging device 1, the comparison circuit 5 compares the address value stored in the register 6 with the address data on the Aviles bus 13 of the real computer 10.

If they match, the comparator circuit 5 outputs, for example, a high signal and applies it to one input of the AND gate 8. Further, the data signal on the data bus 12 of the real computer 10 is applied to the address input of the bitmap memory 4 via the multiplexer 5. The bitmap memory 4 reads out the data value as an address and outputs a high level signal to be applied to the AND gate 8 if the abiles bit is on. Furthermore, if the memory write signal inputted from the control bus 14 of the actual machine control 10 to the ant 9 gate 8 at this time is high and low, that is, if the actual machine computer 10 is writing to memory, the AND gate 8 becomes high level, and the high level signal is input to the breakpoint control circuit 7 and processor 2 as a breakpoint detection signal. The breakpoint control circuit 7 halts the processor 11 of the real computer 10 in response to the input of the breakpoint detection signal. In this way, data at a predetermined address in the memory of the real computer 10 is referenced, and if the data is a prespecified value and the memory of the real machine controller 10 is being written, a break operation is performed. .

Note that the input signal W input from the processor 2 to the bitmap memory 4 and the multiplexer 3 switches the bitmap memory 4 between the write mode and the read mode, and also switches the input of the multiplexer 3. used to control.

[Brief explanation of drawings]

FIG. 1 is a schematic block circuit diagram showing the configuration of a debugging device according to an embodiment of the present invention, and FIG. 2 is a flowchart for explaining the operation of the device shown in FIG. DESCRIPTION OF SYMBOLS 1...Debug device, 2...Processor, 3...Multiplexer, 4...PiI map memory, 5...Comparison circuit, 6 ...
...Register, 7...Break point control circuit, 8...Ant 9 gate, 10.
... Actual computer, 11 ... Processor, 12 ... Data bus, 13 ...
Aviles bus, 14... Control bus, 1
5...Address input, 16...Data bus. Patent applicant Tateishi Electric Co., Ltd. Agent Patent attorney Tatsuo Ito Agent Patent attorney Tetsuya Ito

Claims (1)

[Claims] A debugging device that debugs a program by extracting at9res signals, data signals, and control signals from an actual computer system, and the debugging device has a register that stores an abyss value that should be broken, and a register that corresponds to the data value that should be broken. It is equipped with a bitmap memory that stores data of a predetermined value in the address bits to be read, and a comparison circuit that detects a match between the address signal from the actual computer system and the address signal read from the register, and the operation of the actual computer system. When a match is detected in the comparator circuit, the output of the bitmap memory from which the data signal of the actual computer system is read out as at9less is the predetermined value, and the memory of the actual computer system is in the process of writing, a break occurs. A debug device characterized by performing operations.