JP3110222B2 - Microcomputer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer.

[0002]

2. Description of the Related Art Conventionally, a microcomputer generally has a writable / readable register formed of a RAM or the like in order to hold internal data or create / process data, and a user who uses the microcomputer. Also, a RAM and a register which can be freely written and read are provided.

FIG. 4 is a block diagram showing a main part of a conventional microcomputer. As shown in FIG. 4, in this conventional example, a CPU 101 including an address generation circuit 102 and an instruction control circuit 103 corresponds to an internal bus 106.
And the RAMs 104 and 105. The instruction control circuit 103 has a function of receiving the instruction code 110 and performing internal control according to the instruction code. Hereinafter, with reference to FIG. 4, an operation of writing / reading to / from a RAM and a register incorporated in a conventional microcomputer will be described.

[0004] In FIG. 4, an instruction code 110 generated by a program created by a user is a CPU.
The instruction is input to the instruction control circuit 103 included in the instruction control circuit 101, and an operation according to the instruction code is executed through a signal control operation of the instruction control circuit 103. In response to the execution operation by the instruction control circuit 103, the instruction control circuit 103 outputs a normal write signal 111 during a write operation according to a normal instruction, and outputs a special write signal 112 during a write operation according to a special instruction. Is output. In general, there are two types of write instructions for registers and the like, a normal write operation and a special write operation, each of which is specified as a different instruction by the instruction code 110. Regarding the difference in operation between these two types of instructions,
This will be described with reference to the flowchart at the time of the normal write operation shown in FIG. 5A and the flowchart at the time of the special write operation by the special command shown in FIG. 5B. In the normal write operation, as shown in FIG. 5 (a), 2 steps of reading of data is performed in step S _11, in step S _12, the read data is written to any address The operation is completed by the processing procedure of (1). On the other hand, in the special write operation, FIG.
As shown in (b), which read the data performed in step S _21, in step S _22, data is taken to check writing address is correct or not, and what data write address is correct and If confirmed,
In step S _23, the read data is written to the address. The operation in step S _22, if the confirmation that data write address is correct can not be obtained without executing the write processing in step S24, the three-step procedure that ends a command by outputting an interrupt signal Is performed.

Therefore, in the normal write operation, the operation is simple because the instruction is executed according to a two-step processing procedure, and the speed of instruction execution is high, but an unintended write code is included in the instruction code due to noise or the like. In the case of inputting, there is a problem in that write processing that is originally unnecessary is performed, and data stored in the RAM and the internal registers is destroyed. In addition, in the special write operation, the instruction execution is performed according to a three-step processing procedure including a processing procedure for executing a write address confirmation operation, so that the instruction execution speed is lower than the normal write operation. However, even when an unintended write code is input to the instruction code due to noise or the like, the write processing using the write code is not performed, and the RO is not performed.
There is an advantage that data in M and internal registers is not lost.

Normally, a control register of a watchdog timer, a control register of a standby mode, and the like incorporated in a microcomputer are not frequently accessed, and are required to have high reliability. Only in the write operation for, an instruction for performing the special write operation according to the above special instruction is designated. Generally, when data is written to the internal ROMs 104 and 105, the instruction code 110
A write code is specified for the instruction control circuit 103 included in the PU 101. In response to this, address signal 117 is generated in address generation circuit 102, and R
AM 104 and 105 are input. Also, a normal write signal 112 is output from the instruction control circuit 103,
These are input to these RAMs 104 and 105,
RAMs 104 and 105 receive address signal 117 and normal write signal 112, respectively, and write data on internal bus 106 to an arbitrary corresponding address.

[0007] In recent years, due to technological advances in semiconductor integrated circuits, miniaturization, low cost, and high performance of the semiconductor integrated circuits have been progressing. It is used effectively in a variety of fields, and the field of use is expanded over a range where high reliability is required, including fields related to human life such as antilock brakes and airbags for automobiles. Along with this, not only a measure for ensuring high reliability as a set, but also for a microcomputer alone, a circuit for guaranteeing high reliability of operation of a watchdog timer or the like has been widely considered. The watchdog timer and other circuits have a function for detecting program runaway or deadlock. If an abnormality is detected in the program operation, an abnormality detection interrupt is generated. In addition, a process of stopping the operation of the microcomputer, a process of resetting the microcomputer, a process of comparing data in the internal RAM and the internal register by an interrupt process, and the like are performed.

[0008]

In the conventional microcomputer described above, in order to guarantee the high reliability of the microcomputer alone, when an abnormality occurs in the program operation, a circuit such as a watchdog timer is used. Is configured to detect an abnormality of the program operation. Upon receiving the detection result, an abnormality detection interrupt process is executed, and the operation of the microcomputer is stopped or reset. The processing performs data comparison processing for the built-in RAM, internal registers, and the like. However, in this case, a conventional microcomputer cannot arbitrarily select a writing means intended by a user as a method of accessing the built-in RAM and the internal registers, and therefore, as a countermeasure, In order to maintain the reliability of the microcomputer, as a method of accessing the built-in RAM and the internal registers, etc., when a special write operation is executed by a special instruction with respect to the RAM and the internal registers, the access to the RAM and the internal registers, etc. -There is a disadvantage that the speed is limited, which affects the overall performance of the microcomputer and lowers the performance. Further, if a normal write operation is performed with a normal instruction on the RAM and the internal registers while giving priority to access speed, there is a disadvantage that the reliability of the microcomputer deteriorates.

[0009]

Means for Solving the Problems First data storage means
Second data storage means; and the first and second data storage means.
The bus connected to the data storage means and the normal write instruction
When input as a command code, the data on the bus
Write to the specified address of the data storage means,
When a separate write command is input as the command code
Write data on the bus to the specified address
Make sure that the specified address is correct
A central processing unit for executing a special write instruction to be written from the
The first data storage means and the second data storage means
Each having a corresponding write control register.
If the control register holds the level indicating normal write
The corresponding first or second data storage means
Special write to the write control register
Holds the level indicating the special writing
The corresponding first or second data storage means
Having means for prohibiting normal writing
I have.

The central processing unit is provided with the instruction code
Outputs a normal write signal when
When a separate write command is issued, a special write signal is output, and the
Receiving the normal write signal and the special write signal,
The normal write signal and the characteristic are selectively provided to the storage means.
Even with a switching circuit that outputs a separate write signal,
And the switching circuit writes to the write control register.
Before the data storage means according to the level inserted
Select the normal write signal or the special write signal
And output the data to the data storage means.
Is also good.

[0011]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. As shown in FIG. 1, in the present embodiment, a CPU 101 including an address generation circuit 102 and an instruction control circuit 103 and a RAM 10
4 and 105, a write control register 107, and switching circuits 108 and 109. The instruction control circuit 103 has a function of receiving an instruction code 110 and performing internal control according to the instruction code. Have.
FIG. 2 is a circuit diagram showing the internal configuration of the switching circuit 108.
A circuit 203 and an inverter 204 are provided. Hereinafter, with reference to FIG. 1 and FIG. 2, an operation of writing / reading to / from a register or a RAM incorporated in the present embodiment will be described.

In FIG. 1, an instruction code 110 generated by a program created by a user is
The instruction is input to the instruction control circuit 103 included in the instruction control circuit 101, and an operation according to the instruction code is executed through a signal control operation of the instruction control circuit 103. In response to the execution operation by the instruction control circuit 103, the instruction control circuit 103 outputs “
1 "level normal write signal 112 is output, and at the time of special write operation by a special instruction, " 1 "level
Special write signal 111 is outputted. There are two types of write instructions for registers and the like corresponding to a normal write operation and a special write operation.
10 as a different instruction. These two
The difference in operation due to the type of instruction has already been described in FIG.
This has been described with reference to (a) and (b).
A special write signal 111 based on a special command and a normal write signal 112 based on a normal command output from the command control circuit 103 are branched and input to switching circuits 108 and 109, respectively. On the other hand, a write setting signal 113 output from the write control register 107 is input to the switching circuit 108, and a write setting signal 114 output from the write control register 107 is input to the switching circuit 109. Is entered.

Here, RAMs 104 and 105
Perform a normal write operation using a normal instruction
Thereafter, an operation in a case where it is specified that a normal write operation according to a normal instruction is performed on the RAM 104 and a special write operation according to a special instruction is performed on the RAM 105 will be described. First, "1" level is set to an arbitrary bit of the write control register 107 via the internal bus 106 in order to set a normal write operation by a normal instruction in the RAMs 104 and 105. When the "1" level is set in the write control register 107, both of the write setting signals 113 and 114 output from the write control register 107 are output at the "1" level. Is input to the switching circuit 108, and the write setting signal 114 is input to the switching circuit 109. Switching circuits 108 and 109 are
It is configured as a completely identical circuit, as shown in the circuit diagram of FIG.

In the switching circuit 108, the “1” level write setting signal 113 output from the write control register 107 is input to the AND circuit 202, and is inverted by the inverter 204 to be inverted.
1 is input. For the AND circuit 201, a special write signal 111 of “0” level is sent from the instruction control circuit 103.
(It is executed only during a normal write operation.)
Then , the logical product of these two signals is taken and a signal of "0" level is outputted, and inputted to one input terminal of the OR circuit 203. As a result, the special write signal 111 becomes AND
Blocked by circuit 201. Also, an AND circuit 202
, The "1" level normal write signal 112 is also input from the instruction control circuit 103 (the operation is executed
Because of the normal write operation, the logical product of the above two signals is taken and a normal write signal is output, which is input to the other input terminal of the OR circuit 203. As a result, the normal write control signal is output from the OR circuit 203 as the write control signal 115. On the other hand, the operation of the switching circuit 109 is exactly the same as that of the switching circuit 108, and the OR circuit 203 of the switching circuit 108 outputs a normal write control signal as the write control signal 116. These write control signals 115 and 116 are input to RAMs 104 and 105 via a bus, respectively. In this case, when a normal write instruction is input by the instruction code 110, as described above, the address generation circuit 1
02 through the address signal 117 output to the RAMs 104 and 105, respectively.
A write operation is performed on any of the addresses 4 and 105.

Next, when the RAM 104 is set to perform a normal write operation by a normal instruction and the RAM 105 is set to perform a special write operation by a special instruction, the write control register 1 via the internal bus 106 is used.
The "1" level and the "0" level are set in arbitrary bits 07, respectively. Write control register 107
Are set to "1" level and "0" level, the write setting signal 113 output from the write control register 107 is output at "1" level, and the write setting signal 114 is set to "0". Output at the level,
The write setting signal 113 is input to the switching circuit 108, and the write setting signal 114 is input to the switching circuit 109. In the switching circuit 108, the “1” level signal 113 output from the write control register 107 is input to the AND circuit 202 and inverted by the inverter 204 and input to the AND circuit 201. The special write signal 111 is also input from the instruction control circuit 103 to the AND circuit 201, and the logical product of these two signals is taken to output a “0” level signal.
03 is input. Thereby, the special write signal 111
Is cut off by the AND circuit 201. The normal write signal 112 is also input from the instruction control circuit 103 to the AND circuit 202. The AND signal of the two signals is taken to output the normal write signal.
Is input to the other input terminal. Therefore, the OR circuit 203
Rather, a normal write control signal is output as the write control signal 115. On the other hand, in the switching circuit 109, a “0” level signal 114 output from the write control register 107 is input to the AND circuit 202 and inverted by the inverter 204 and input to the AND circuit 201. For the AND circuit 201, the instruction control circuit 103 outputs a "0" level (normal write operation).
) Or a special write signal 111 at the “1” level (during a special write operation), a logical product of these two signals is taken and a special write signal is output, and one input terminal of the OR circuit 203 is input. Is input to Further, the instruction control circuit 103 outputs a “0” level to the AND circuit 202.
(At special write operation) "1" level (normal write operation
), The AND signal of the two signals is obtained, and a signal of “0” level is output, and is input to the OR circuit 203. Thus, the normal write signal 112 is cut off by the AND circuit 202.
Therefore, the write control signal 116 is output from the OR circuit 203.
Is output as a special write control signal. These write control signals 115 and 116 are input to RAMs 104 and 105 via a bus, respectively. In this case, when a normal write command is input by the command code 110, as described above, the write control signal 115
Is output from the address generation circuit 102 to the RAM 104 to which the normal write control signal is input.
A write operation according to a normal write command is executed via an address signal 117 input to M104. Is performed, the write operation is not executed for it, and the special write operation is executed only when the instruction code 110 makes an access by a special write instruction.

FIG. 3 is a block diagram showing a second embodiment of the present invention. As shown in FIG. 3, in the present embodiment, a CPU 101 including an address generation circuit 102 and an instruction control circuit 103 and a RAM 1
04 and 105, and switching circuits 108 and 109. The instruction control circuit 103 has a function of receiving an instruction code 110 and performing internal control according to the instruction code. The difference between the present embodiment and the first embodiment is that in this embodiment, the write control register 1
07 is not provided, and instead, the write control external terminals 302 are connected to the switching circuits 108 and 109, respectively.
And 301 are connected. Also in this embodiment, the internal configuration of the switching circuits 108 and 109 is the same as that of FIG. Hereinafter, FIGS. 3 and 2
The operation of writing / reading to / from the RAM and the registers incorporated in the present embodiment will be described with reference to FIG.

In FIG. 3, an instruction code 110 generated by a program created by a user is a CP
The signal is input to the instruction control circuit 103 included in U101, and the operation according to the instruction code is executed through the signal control operation of the instruction control circuit 103. Instruction control circuit 103
In response to the execution operation of the instruction control circuit 103, the instruction control circuit 103 outputs a normal write signal 112 during a write operation according to a normal instruction, and outputs a special write signal 111 during a write operation according to a special instruction. .
The special write signal 111 based on the special write command and the normal write signal 112 based on the normal write command output from the command control circuit 103 are branched and input to the switching circuits 108 and 109, respectively. In addition, the write control external terminal 30
Write setting signals 118 and 119 are input from 2 and 301, respectively.

Next, in this embodiment, a normal write operation according to a normal write instruction is performed on the RAMs 104 and 105, and thereafter, a normal write operation according to a normal instruction is performed on the RAM 104, and a special write operation is performed on the RAM 105. The operation in the case where a special write operation by an instruction is designated will be described. First, RAM10
4 and 105, write control external terminals 302 and 3
01 and write setting signals 118 and 119
Are both set to the “1” level and input to the switching circuits 108 and 109. Switching circuits 108 and 109
Are constituted by exactly the same circuit, as shown in the circuit diagram of FIG. In the switching circuit 108, the “1” level write setting signal (118)
Input to the D circuit 202 and the
And input to the AND circuit 201. AN
The special write signal 111 is also input to the D circuit 201 from the instruction control circuit 103. The logical AND of these two signals is taken to output a "0" level signal, and the special write signal 111 is cut off. Is done. The AND circuit 20
2, the normal write signal 112 is also input from the instruction control circuit 103, the logical product of the two signals is taken, the normal write signal is output, and the normal input signal is input to the other input terminal of the OR circuit 203. You. As a result, a normal write control signal is output from the OR circuit 203 as the write control signal 115. Similarly, also in the switching circuit 109, the switching circuit 109 outputs a normal write control signal as the write control signal 116. These write control signals 115 and 116 are supplied to RA
It is input to M104 and M105. In this case, when a normal write instruction is input by the instruction code 110, it is output from the address generation circuit 102,
Address signal 117 input to M104 and M104
, A normal write operation to an arbitrary address in the RAMs 104 and 105 is performed.

Next, when a special write operation by a normal instruction is performed on the RAM 104 and a special write operation by a special instruction is performed on the RAM 105, the signal is input from the write control external terminal 302. The write setting signal 118 is set to “1” level and input to the switching circuit 108, and the write setting signal 119 input from the write control external terminal 301 is set to “0” level and input to the switching circuit 109. Referring to FIG.
In the switching circuit 108, the “1” level write setting signal (118) is input to the AND circuit 202, and is also inverted by the inverter 204 to be output to the AND circuit 2.
01 is input. The special write signal 111 is also input to the AND circuit 201 from the instruction control circuit 103. The AND of these two signals is taken to output a signal of "0" level, and the special write signal 111 is cut off. Is done. The normal write signal 112 is also input to the AND circuit 202 from the instruction control circuit 103. The AND signal of the two signals is ANDed to output the normal write signal, and the other input of the OR circuit 203 is output. Entered at the end. Thereby, the write control signal 115 is output from the OR circuit 203.
And a normal write control signal is output. Also, on the other hand,
In the switching circuit 109, the “0” level write setting signal (119) is input to the AND circuit 202, and is inverted by the inverter 204 to be output to the AND circuit 2.
01 is input. The special write signal 111 is also input from the instruction control circuit 103 to the AND circuit 201, the logical product of these two signals is taken, a special write signal is output, and one input terminal of the OR circuit 203 is input. Is input to The normal write signal 112 is also input to the AND circuit 202 from the instruction control circuit 103, and the logical AND of the above two signals is taken to output a “0” level signal. Is shut off. Thereby, the write control signal 11 is output from the OR circuit 203.
As 6, the special write signal is output. These write control signals 115 and 116 are input to RAMs 104 and 105 via a bus, respectively. In this case, when a normal write command is input by the instruction code 110, the output from the address generation circuit 102 to the RAM 104 to which the normal write control signal is input as the write control signal 115 as described above. And RAM
A write operation according to a normal write command is executed via an address signal 117 input to the RAM 104, but the RAM 105 to which a special write control signal is input as the write control signal 116 accesses the RAM 105 according to the normal write command. Is performed, the write operation is not executed for it, and the special write operation is executed only when the instruction code 110 makes an access by a special write instruction.

That is, in this embodiment, the type of the write command can be dynamically changed at an arbitrary timing by the write setting signals 118 and 119 input from the outside instead of the level signal set in the write control register 107. It is possible to switch.

[0022]

As described above, according to the present invention, it is possible to select the type of a write instruction to a register or a RAM incorporated in a microcomputer in accordance with the intended use of the user, and to specify the type of instruction by the user. This makes it possible to prevent writing due to a malfunction caused by this, thereby improving the reliability of the internal data of the built-in register or the RAM.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a switching circuit according to the present embodiment.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

FIG. 4 is a block diagram showing a conventional example.

FIG. 5 is a flowchart showing a processing procedure in a normal write operation and a special write operation.

[Explanation of symbols]

 101 CPU 102 Address generation circuit 103 Instruction control circuit 104, 105 RAM 106 Internal bus 107 Write control register 108, 109 Switching circuit 110 Instruction code 111 Special write signal 112 Normal write signal 113, 114, 118, 119 Write setting signal 115, 116 Write control signal 117 Address signal 118, 119 Write control signal 201, 202 AND circuit 203 OR circuit 204 Inverter 301, 302 Write control external terminal

Continuation of the front page (56) References JP-A-54-2026 (JP, A) JP-A-5-127894 (JP, A) JP-A-60-230248 (JP, A) JP-A-2-239351 (JP) , A) JP-A-57-100695 (JP, A) JP-A-57-170000 (JP, U) (58) Fields investigated (Int. Cl. ⁷ , DB name) G06F 9/34, 12/14, 15/78

Claims (3)

(57) [Claims] A first data storage unit; a second data storage unit; a bus connected to the first and second data storage units; Writes data on the bus to a specified address of the data storage means, and writes a data on the bus to the specified address when a special write command is input as the command code. A central processing unit for executing a special write instruction for writing after confirming that the designated address is correct; and a write control register corresponding to each of the first data storage means and the second data storage means, writing
When the control register holds a level indicating normal writing, special writing to the corresponding first or second data storage means is inhibited, and the write control register
And a means for prohibiting normal writing to the corresponding first or second data storage means when the data holding level indicates the special writing. 2. The central processing unit outputs a normal write signal when the instruction code is a normal write instruction, and outputs a special write signal when the instruction code is a special write instruction. 2. The microcomputer according to claim 1, further comprising a switching circuit for selectively outputting said normal write signal and said special write signal to said data storage means. 3. The switching circuit selectively outputs the normal write signal or the special write signal to the data storage means to the data storage means in accordance with a level written in the write control register. 3. The microcomputer according to claim 2, wherein: