JPS59159558A - Semiconductor substrate - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION The present invention relates to semiconductor substrates for bipolar integrated circuits that can be used in the manufacture of a variety of bipolar integrated circuits.

[Wise Ha Circulation Background and its Problems]

The gate array h'' is known as a gate array suitable for high-mix, low-volume digital integrated circuits, but in bipolar integrated circuits, the analog circuit of the gods, the final metal wiring σ
)) (hereinafter referred to as ``analog array'').As shown in Figure 1, this is a transistor, 7.ri2 (B is a base contact, E is an emitter A contact % (JJ collector contact) and a diffused resistor 3 are formed on a wafer in advance, and these circuit elements and metal wiring are combined arbitrarily to manufacture a desired analog circuit. Two chip sizes are predetermined, and according to the chip sizes, dicing lines 4 are determined and bonding pads 1 are formed.

In this way, in conventional analog arrays, transistors and resistors are formed at predetermined positions on the wafer using -f, and the characteristics and resistance values of the transistors are also already determined. 1. When configuring an analog circuit with various functions, the position of the circuit elements is fixed, so it is difficult to determine the optimal layout. I can't take it. In particular, the characteristics of analog circuits are affected by their layout, and the fatal l11'j
Problems may occur. Analog 1 should be realized based on the characteristics of transistors and resistors that have already been formed.
Is the characteristic of LIJ path also a limitation? If you receive it, please send it to me) -1. Furthermore, since the chip size is predetermined, the scale of the circuit may be limited, or conversely, equivalent elements may be left over, resulting in waste. Although analog arrays are suitable for high-volume, low-volume production, they still have a number of limitations.

[Purpose of the invention]

The present invention was made in consideration of the above-mentioned circumstances, and has a wide range of freedom in the arrangement of circuit elements, waiting conditions, etc., and the chip size can be arbitrarily determined. <
The purpose is to provide a single bipolar stack (semiconductor substrate for bath) suitable for high-mix, low-volume production.

[Summary of the Invention] In order to achieve this object, a semiconductor substrate according to the present invention is characterized in that a semiconductor substrate according to the present invention is formed in a regular manner on a silicon wafer with a unit pattern consisting of predetermined device isolation diffusion regions. The element isolation diffusion region of the unit pattern is
It is highly desirable to have at least a portion of the N+ layer.

[Embodiments of the invention]

The present invention σ) - In an actual 1 Ali example, a semiconductor substrate for a biholami % product circuit is shown in Fig. 2 - this semiconductor substrate Q'
j:.

δ unit pattern 10 care entire surface consisting of 3 vertically long element isolation diffusion regions 11 of 2 N''-buried layers J2 and diffusion regions 13 for each of 4 horizontally long elements having 14 N+1 application layers. Each element isolation diffusion region I3 is arranged regularly as shown in FIG.

There are 14 KN buried layers at the bottom of 13 sub-expanded memorial areas of the Song Dynasty. The semiconductor substrate according to this example is in the state of σ before circuit element formation and σ after element isolation and diffusion.

Figure 4 shows the state of the conventional analog array shown in Figure 1 after element isolation and diffusion. (Characteristics of the semiconductor substrate according to There is no area 22, and it is at point 5.

Next, we will describe how to form σ1 circuit elements such as resistors and transistors using this semiconductor substrate. First, for the resistor, a thin LiQ abrasive resistor such as a polysilicon resistor is used instead of a diffused resistor as in the conventional case. The diffusion resistance is shown in Figure 5 (a
), , (1), it is necessary to form the element isolation diffusion region 32A on which the buried layer 31 is located.The diffusion resistor 33 is a wiring formed on the silicon oxide film 34. It is wired by the resistor metal 35 for the purpose of wiring.As shown in this figure (a), the thin film resistor 1 is restricted by the diffusion F sandwiching (element isolation diffusion region 32σ) pattern.
, In the pattern of the element isolation diffusion region 42 in (b): t
IlJ limited is not accepted c, N + embedded lap 41? 44 silicon oxide films are formed on the element isolation diffusion region 42, and 43 thin film resistors made of polysilicon or the like are formed thereon. The wiring of this thin film resistor 43 is the wiring metal 4
Be done by 5. In this way, the resistor formed on the semiconductor substrate according to this embodiment uses regular element molecules lf? by using a thin film resistor. Transistor 4Q, which can be freely arranged in columns without being restricted by the diffusion region balloon! , are formed on isolation diffusion regions, similar to conventional analog arrays. For example, as shown in FIG. 7, base contacts [3. Emitter contact E
, the collector contact C. When a circuit element is formed on the semiconductor substrate according to this embodiment, as in the case of NIPN transistors having the shape 1 & 1 "0 or more, 41. The transistor is formed on the element isolation diffusion region, and the resistor is Since it can be formed in a selective relationship with the element isolation diffusion region, it is possible to design the circuit with the optimal layout for the desired circuit. g) Layout example 8
9 is the central part of the FIG. 8 schematic,
FIG. 9 (This is the peripheral part of the etching.Element isolation diffusion region 5
It can be seen that a transistor 52 is formed on the transistor 1, and a resistor 53 having the size and width of a persimmon is formed independently of the element isolation diffusion region 51.

In the chip peripheral area shown in FIG.
1 Bonding Patsudora 4 regardless of Tsuba turn and Sheet
ke form. However, the dicing line 55 needs to be arranged in a manner that allows the chips to be arranged continuously, considering the pitch of the unit pattern 10. In this way, by using the semiconductor substrate F according to this embodiment, (Ipolar integrated circuit design-f
In cases where one circuit element is optimally arranged, the chip size can be determined, and both large-scale bipolar integrated circuits and small-scale bipolar integrated circuits can be manufactured on the same semiconductor substrate.
It is possible to create lJ.

In the first embodiment, a higher order pattern as shown in FIG. 2 was used, but this melon pattern may be one of the gods. For example, as shown in 11.10ν1.

The device isolation diffusion regions may be arranged regularly in units of 62 square patterns. Element isolation diffusion region 62
1I engineering N + 61 layers? If the square element has one toad scattering area 62, the first
As shown in Figure 1, the NPNI' transistor? It is possible to manufacture with arrangement in four directions, allowing for more optimal arrangement of circuit elements.

Moreover, as shown in FIG. 12, a one-ton pattern 74? Of the constituent element isolation diffusion regions 71 and 73.

This includes those that do not have 72 N+ buried layers.
The device isolation diffusion region 71 which does not have the N+ buried layer 72 is the only one that forms a transistor (N1'N) which serves as a substrate collector. This is because more NPN transistors may be required in bipolar integrated circuits.

〔Effect of the invention〕

As described above, the semiconductor substrate according to the present invention has device isolation diffusion regions regularly arranged.

The arrangement of the transistors can be optimized, and the thin film resistor can be formed independently of the pattern of the resistor and element isolation diffusion region, so that the circuit can be designed freely. In addition, the chip size can be freely determined according to the size of the chip, and there is no waste.

As described above, it can be said that the semiconductor substrate according to the present invention is truly suitable for high-mix, low-volume production.Since the pattern of the element isolation diffusion region of the semiconductor substrate according to the present invention is regular, it can be designed by CAD. It can be said that it is also suitable for

[Brief explanation of the drawing]

Figure 1 is a plan view of a conventional analog array, and Figure 4 is the state of the analog array after element isolation and diffusion. 2 is a plan view of a semiconductor substrate according to the first σ) embodiment of the present invention, and FIGS. 3(a) and 3(b) are plan views and cross sections of element isolation diffusion regions of quarter and four-piece substrates, respectively. Figures 5(a) and 5(a) are a cross-sectional view and a plan view of the diffused resistor formed on the element isolation diffusion region, respectively, and Figure 6(a).
). (b) is a cross-sectional view of a thin film resistor formed on the element isolation diffusion region 1 and a plan view, respectively. Figure 1π7 is a plan view of an NPN transistor formed in the shape 17 on the element isolation diffusion region 1. FIG. 9 is a plan view showing a specific example of the arrangement of circuit elements formed on a semiconductor substrate according to the first embodiment of the present invention, and FIG. 10 is a plan view showing a specific example of the arrangement of circuit elements formed on a semiconductor substrate according to the first embodiment of the present invention. FIG. 11 is a plan view of a transistor formed on an element isolation diffusion region of the same semiconductor substrate. FIG. 12 is a plan view of a unit pattern b of a semiconductor substrate according to a third embodiment of the present invention. , 10...
・Unit turn, 11. 13... Element isolation diffusion region, 12° 14... N buried layer, 21... Head mounting for resistor, 22... Bonding pad area, 23...・Dicing line area, 31.41...N+ buried layer, 3
2.42... Element isolation diffusion region, 33... Diffused resistor, 43... Thin film resistor.

Claims (1)

[Scope of Claims] (1) A semiconductor substrate with features and characteristics: (1) A nest pattern consisting of predetermined element isolation diffusion regions regularly formed on a silicon wafer. 2. The above-mentioned nest position pattern σ) The 1°C 1t diffusion region outside the element is:
A semiconductor substrate according to claim 1, characterized in that at least a portion of the semiconductor substrate has a KN+ buried layer.