JPH01274450A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase an integrating density in the same LSI area, by providing the diffused region of a unit cell which is bent inward, and forming a base on which a contact for substrate potential is provided. CONSTITUTION:Two channel gates 15 comprising polycrystalline silicon which are bent inward are provided on a P-type diffused-layer forming regions 11 and N-type diffused-layer forming regions 13. N-type diffused layers 1A and contacts 17 for substrate potential are provided in the vicinities of the bend parts at both ends of the P-type diffused-layer forming regions 11 beneath a power source line 18 which crosses the P-type diffused-layer forming regions 11. P-type diffused layers 1B and contacts 16 for substrate potential are provided in the vicinities of the bend parts of both ends of the N-type diffused-layer forming regions 13 beneath a power source line 19. Thus, CMOS type unit cell ts formed. Since source and drain regions are bent inward, spaces where contacts for the substrate potential are arranged can be provided, and the inte grating density is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit, and particularly to supplying a potential from a power supply line to a contact for substrate potential.

[Conventional technology]

FIG. 2 shows a plan view of a conventional example, which consists of two polycrystalline silicon layers each on a P-type diffusion layer formation region 21.22 and an N-type diffusion layer formation region 23.24 on a predetermined wiring pitch. A gate channel 25 is provided, and an N-type diffusion layer 2A is formed between the P-type diffusion layer formation regions 21 and 22, and a P-type diffusion layer 2B is surrounded between the N-type diffusion layer formation regions 23 and 24 to form a P-type diffusion layer. By placing a contact 27 at a portion intersecting the power supply line 28 that crosses the center of the region 21.22, the substrate potential of the P-type diffusion layer formation region 21.22 is supplied, and N is supplied to the center of the diffusion layer formation region 23.24. Crossing power supply line 29 and P type diffusion layer 2B
By placing a contact 26 at the intersection with the N-type diffusion layer formation regions 23 and 24, a substrate potential of the N-type diffusion layer forming regions 23 and 24 was supplied, thereby forming an 0MO3 type transistor. The figure shows two CMOS unit cells. Note that the term "P-type or N-type diffusion layer forming region" is used to represent a part of the device region in which a source/drain region made of a P-type or N-type diffusion layer is provided, except for the region immediately below the gate channel.

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, each power supply line 28, 29
crosses the P-type diffusion layer formation regions 21 and 22 and the N-type diffusion layer formation regions 23 and 24, respectively, so that a contact 2 for substrate potential is formed between the two P-type diffusion layer formation regions 21 and 22.
7 and two N-type diffusion layer formation regions 2
There was a drawback that the area of the LSI chip became large in order to secure enough space to place the contact 26 for the substrate potential between 3.24 and 3.24.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a basic cell in which two gate channels and a power supply line are arranged vertically and horizontally on a predetermined diffusion layer formation region. The gate channel is bent inward at each portion crossed by the power supply line, and a contact for a basic potential is provided near the bent portion of the diffusion layer forming region.

〔Example〕

FIG. 1 shows a plan view of an embodiment of the invention.

The structure has two gate channels 15 made of polycrystalline silicon bent inward over the P-type diffusion layer formation region 11 and the N-type diffusion layer formation region 13, and the P-type diffusion layer formation region 11. In the power supply lines 18 and 19 that cross the N-type diffusion layer formation region 13, an N-type diffusion layer IA for substrate potential and a contact 17 are located near the bends at both ends of the P-type diffusion layer formation region 11 below the power supply line 18. , by placing P diffusion Jti 71B and contacts 16 for substrate potential near the bends at both ends of the N-type diffusion layer forming region 13 under the power supply line 19, CM
It constitutes an O8 type O8 cell. Since the source/drain regions are bent inward, a space can be taken for arranging contacts for substrate potential, and a structure is formed on the collection surface.

Although this embodiment has a CMO3 structure, a single channel MOS transistor may also be used.

〔Effect of the invention〕

As explained above, in the present invention, by bending the diffusion region of the unit cell inward to form a space in which a contact for substrate potential can be placed, the size of the unit cell can be made smaller than that of the conventional method. The degree of integration can be increased by area.

[Brief explanation of the drawing]

FIG. 1 is a plan view of the first embodiment of the present invention, and FIG. 2 is a plan view of the conventional side. 11.12, 21.22... P-type diffusion layer formation region, 1
．． 3,14,23.24...N type diffusion layer, 15°25
...Gate channel, 16.17, 26.27...
・Contact, 18, 19, 28.29...power line,
LA, 2A...N-type diffusion layer (for substrate potential), 1.2.
2B...P-type diffusion layer (for substrate potential).

Claims (1)

[Claims] In a semiconductor integrated circuit having a basic cell in which two gate channels and two power lines are arranged vertically and horizontally on a predetermined diffusion layer formation region, the diffusion layer formation region and the gate channel are arranged so that the power supply line is 1. A semiconductor integrated circuit, wherein the semiconductor integrated circuit is bent inward at each crossing portion thereof, and a contact for substrate potential is provided near the bent portion of the diffusion layer forming region.