JPS5866342A - Semiconductor integrated circuit device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides q# with OA D (Oomputer A
14edDcsign) also uDA ('Design
The present invention relates to a semiconductor device suitable for a large-scale integrated circuit device (hereinafter sometimes referred to as an LSI) whose layout is designed using a design technique such as Automation.

This type of layout design is performed using a computer especially from the viewpoint of designing a multi-product fiL8I, shortening the design period, reducing design man-hours, and improving design quality.
For this purpose, a design automation method has been introduced in which virtual coordinates are determined in advance on a semiconductor wafer and mutual wiring layers, through holes, contact holes, various circuit elements, etc. are formed at the predetermined coordinate positions. In this specification, the pitch of these virtual coordinates is particularly referred to as a "system wiring pitch," and the pitch of wiring running within a large number of unit cells provided on a semiconductor wafer is referred to as a "cell wiring pitch."

For example, as a unit cell, a group of P-channel MO8FETs is formed in an N-type semiconductor region in a semiconductor wafer, and an N-channel MO8FET group is formed in another P-type semiconductor region (P-type well).
When configuring a 0M08 unit logic circuit by forming a group of 8FETs, a PNPN button can be formed between both PETs.
In order to prevent the thyristor structure from operating and inhibiting the logic function, the semiconductor substrate where the P-channel MO8FET group is formed and the P-type well where the N-channel MO8FgT group is formed are placed at a high potential (power supply potential). vDD) and a low potential (earth potential v11.). However, for cells that are not included in the power supply arrangement 111, power supply wiring must be provided for each cell to supply each of the above potentials. In order to supply this potential, an N+ type substrate potential supply region and a P+ type well potential supply region 17 are formed between each cell, or these supply regions 111E are formed.
When a region is formed in the wiring channel ilS between cell columns,
Not only does this take up area, but since each power supply area is placed in the remaining area after the layout is completed, it is difficult to place it on the coordinates of the layout described above, and automatic placement by DA is inappropriate. Become.

Therefore, the object of the present invention is to have a power feeding function by itself;
Another object of the present invention is to provide an integrated circuit device provided with a unit cell that is compatible with automatic placement.

For this purpose, according to the present invention, the power supply regions for supplying the substrate potential and the well potential are located near the source or drain region of each of the MO8 PETs constituting the unit cell, respectively, within the cell. The power supply areas are formed in such a way that each cell wiring for power supply can be connected to these power supply areas.

In the example described below, a polysilicon layer (PS) constituting the gate electrode of MO8FFiT formed in a silicon semiconductor chip, a first layer of aluminum Layer (A
IF) and a second aluminum layer provided on the first aluminum layer AII via a second interlayer insulating layer.

#1! [As shown, the logic circuit as one system formed on the semiconductor chip 2 is composed of logic blocks 1 having medium-sized logic functions. Although only representative ones are illustrated, between each logical block, there are multilayer wiring layers 12 (2 layers 1) AJ layout 1) along virtual coordinates.
Kl(1111)Ajffial) etc.
The system as a whole has several large-scale functions. The logic block itself consists of a large number of unit cells (5F) each column provided at the power supply terminals 3 and 4 at both ends as shown in the figure 2mK, and between the columns or rows of each unit cell is a polysilicon wiring P.
'8 and Ajl, and the wiring is done, for example, by aFiA12, which skips one column. The unit cell 5 is, for example, NOR, OR, AND, NAND.

Like an ethical circuit such as Alikupfrog, it consists of cells having a small-scale nested logic IIa.

When creating such an LSI, each design can be performed using an electronic computer using OAD. In order to achieve this, in particular in arrangement design or layout design, regular grid-like coordinates are virtually provided in advance in the semiconductor uni-eight or chip kKY direction as shown in No. 3 #1, and predetermined coordinate positions are Programming is performed so that 1c41 interconnections are located and through holes or contact holes for interconnection are located at the lattice points. That is, the above Ajl is 4ICII in the horizontal direction, and Muj2 is both 4ICII! In the direction, they are arranged so as to exist on the pseudo AM standard at equal intervals, forming regular X-Y coordinates as a whole. In FIG. 3, the area of each unit cell 5 is shown by diagonal lines, but the areas between adjacent cells are shown by thick lines.
12-AJI-P8. Note that a third layer of kl wiring Aj3 can be further provided on AJZ, but the AI wiring of each layer including this Aj34 and P
For the S wiring, in order to reduce the level difference and prevent the wiring from breaking,
It is placed between other wirings so that they do not overlap each other.

As shown in Figure 3, each wiring is provided along a pitch of predetermined coordinates, that is, a logical wiring pitch, but what is important in this example is that the cell itself has a power supply area and therefore In addition, the pitch of the input/output terminals of the polysilicon wiring ps or gate electrode group in the cell should be set to the logic wiring pitch of 1. It's about making them consistent. This is shown in Figure 4~
FIG. 6 will be explained in detail.

4 to 6, 0MO constituting the unit cell 5 is shown.
8 logic circuits are shown. According to this 0MO8, N
type silicon substrate 6vc, P-channel MO8FET section 7 and N-channel M surrounded by a thick silicon oxide film
O8FET section 8 is provided, and common N-type polysilicon gate electrodes ps, +'P
S,,ps,.

ps,, ps, extend in parallel to the cell periphery, and each terminal A, B, 0. D.B.

A1. B/, o/, Dl, and W are formed, respectively. These terminals are arranged at the same pitch as the polysilicon wiring PS shown in the IfIB diagram. This pitch is 1.5 mm in the horizontal direction in FIG. 3.
5. This corresponds to the system wiring pitch indicated by an odd number of 7°9. In order to accommodate this, in this example, the following unique innovations are made to the shapes of the gate electrodes PS, ~PS. It is formed by ion implantation or diffusion using each gate electrode as a mask, and Alfji is formed at appropriate positions for each P medium region 9 of nine FET7Ilil and each N+ type region 0 of FBT89i11.
．． Contact hole 16, 17.1g, 19, 20° 21.22.23 where -15 contacts with ohmic contact
．． 24 and 25 are formed respectively. What should be noted here is that each of the contact balls 16 to 20 and 21 to 25 are arranged side by side in the horizontal direction, and the gate electrode does not run in each contact hole, but in a fixed manner as shown in Fig. 4. They are arranged vertically with the regularity of
It is bent at an angle of .

In this way, by bending the gate electrode at the necessary locations, each contact hole, for example holes 17 and 2, can be bent.
0.18 are arranged side by side in the horizontal direction, the gate electrodes ps,, ps, can be arranged at a predetermined distance from each hole even if the distance between them is narrower by arranging them alternately vertically as shown in the figure. can be provided. That is, for example, when the contact holes 17 and 20 are arranged horizontally, the distance between the holes can be reduced to a smaller distance D' by arranging the contact holes 17 and 20 diagonally vertically according to this example. For example, while D is about 10 μm, D′ is about 8 μm.
You can make m and jin. By appropriately forming such a positional relationship between the contact holes and the gate electrodes at various locations, the overall distance between the contact holes (and eventually between the gate electrodes) can be reduced, and the terminals A present at both ends of each gate electrode can be reduced. -g, A' to B' can be located on coordinates that match the target logic wiring pitch.

Note that gate terminal A, B' and E' are connected to AJ wiring 11.
-15, they are connected to each other by the first layer AI wiring 26, 27-. A of the first layer inside these cells
l Layout can be set in advance to various patterns according to the desired unit logic function, but in the design of the entire LSI, the first layer of AI wiring should be arranged at the logic wiring pitch shown in Figure 3 (in Figure 4, it is shown vertically). even numbered coordinates). Fifth
and the cross section of FIG. 6 (in which 31 is the field 5to
32 is a gate oxide film, and 33 is a phosphosilicate glass film. Although not shown, the phosphosilicate glass group is further deposited as an interlayer insulating film on the AJ wiring in the 11th layer and on the -Aj wiring in the second layer, and KH silane is deposited on the A/wiring in the third layer. The membrane is applied as a badge-base membrane.

If each wiring is provided as shown in FIG. 4, P channel MO8Fg with each region 9 as a source or drain region.
'rQ, -Qa -Qs -Qy -Qa is constructed,
and an N-channel M08FETQl in which each region IO is a source or drain region.

Q4=Ql-Qa-Q-0 is configured, and these FBTs are connected as shown in FIG. 7 to form one exclusive OR (1i:xclusive OR). In this Exclusive OR, the contact holes shown in Figure 4 need to be arranged alternately in the upper and lower positions at locations where a plurality of FITs are connected in parallel in terms of the circuit. It is desirable to have a sufficient length (c channel width) to form a contact hole. Also, contact holes are not necessarily required where multiple FETs are connected in series, but considering the case where these FETs can be used in parallel, the width of the channel that can be formed with contact holes above and below should be determined in the same manner as above. It is good to secure it. In FIG. 4, five FET elements are provided in each FBT section, but if it is desired to increase the number of elements, similar structures may be arranged side by side in the horizontal direction of the figure.

What should be noted in the exceptional cell structure described above is that both FETs 17 and 8FK in cell 5
1 and 12 are provided, respectively, and a predetermined potential is applied to the substrate 6 and the well 29 via these power supply wirings. That is, in the FET 857, the N+ type region 28 is formed so as to protrude in contact with one P+ type region 9, and the power supply voltage vDD is supplied to a part of each P+ type region 9 and the N+ type region 28. The power supply wiring 11 for this purpose is provided with sufficient original width. Therefore, vDD is connected to the P+ type region 9 through the contact hole 16.
is provided, and a contact hole 3 is provided for the substrate 6.
vDD (substrate potential) is applied to the N+ type region 28 via the N+ type region 28. On the other hand, in the FET section 8, there are three P+ type regions M, 30 adjacent to the N+ type region 10.
- protruding into the mold well 29, and these peripheral areas 30;
and 10 on earth level voltage v11. A power supply wiring Ia 12 for supplying the power is provided with the original sufficient width, and is connected to the three N"ffl areas 1 (1) through the contact holes 23 to 25, and is connected to the contact holes 35.36° 37. Each P+ type region 30KI[I is connected through the P+ type region 30KI[I].

Therefore, a predetermined fixed potential (earth level well potential) must be applied to the well 29 by the power supply wiring @12WC. Note that the N medium-sized region 28 that provides the substrate potential
The upper contact hole 34 and the contact holes 35 to 37 on the P medium-sized region 30 that provide the well potential are respectively arranged on grid points of coordinates of a prescribed pitch (in FIG. 4, on the intersections of even-numbered coordinates). , corresponds to the system wiring pitch.

In this way, the power supply area for supplying the substrate potential and the potential is provided inside the cell itself at a logical wiring pitch, and each power supply wiring for that purpose is also provided within the cell.
Since the cell itself is provided with a power supply function and the area occupied by the power supply region is not so large, the increase in cell size can be minimized as much as possible. Also,
In terms of electrical characteristics, the above-mentioned power supply method fixes the substrate and the well at a predetermined potential, so even if unexpected abnormal human power is applied, potential fluctuations are suppressed, and both FgTs as described above By preventing the operation of the thyristor structure in between, local latch-up phenomena can be eliminated.

Furthermore, by arranging a large number of the cell structures shown in FIG. 4 as shown in FIG. 2, the above-mentioned power supply area and power supply wiring can be reliably arranged in a prescribed positional relationship. Moreover, by bending the polysilicon gate electrode as the intra-cell wiring near the necessary contact hole, the pitch can be reduced and the input/output points can be matched to the minimum logic wiring pitch. Automatic placement and routing using CλDK becomes possible, and both the system placement pitch and cell size can be reduced. As a result, it is possible to increase the density of the unit cells, and also to greatly increase the number of wiring channels sK related to the unit cells, and as a result, the chip size itself can be significantly increased. <This means that it can be reduced.

In addition, in the above cell structure, N-type polysilicon PS, ~
Since the PS is directly connected between both FETs, the cell size is small, but the output of one FET can be input directly to the polysilicon gate by Aj distribution in the space existing between both FETs. It becomes possible.

Next, another example of the present invention! ! Let's talk about Figure 8.

In this example, parts common to the above-mentioned embodiments are given the same reference numerals and their explanations are omitted. bi3
9 and the P+ type region 42 for supplying a well potential do not protrude from the periphery of the P+ castle region 9 and the N+ type region 10, respectively.

Even if the pattern of each semiconductor region is modified in this way, the contact holes 40, K, contact holes 40,
4.1, supplying the substrate potential through the contact hole 4
Well potential can be supplied via 3. In addition,
The contact hole for applying these potentials is the eighth
In the example shown in the figure, two are provided on the substrate side (one in Figure 114) and one on the well side (three in Figure 4), but the number of these is determined by the position of the diffusion area that becomes the power supply terminal. Well, 1
In principle, each cell should be provided with a length of 1 m or more.

Next, further embodiments of the present invention will be described with reference to FIGS. 4, 7, and 9.

In this example, the cell structure Fi may be almost the same as that shown in FIG. 4, but a measure is taken to clamp a predetermined polysilicon gate electrode to the power supply potential. In other words, as shown in Fig. 4 (AND, NAND, NOR,
In a unit cell such as an OR, input terminals may not be used depending on the circuit configuration for system design. In this case, if the human-powered electronic device is left as it is, its impedance will increase, causing malfunction. Therefore, it is necessary to fix the input terminal to a predetermined potential in order to prevent this flipping operation.

For this purpose, according to this example, in FIG.
If is the above input terminal, polysilicon PS,
A through hole 44 is formed at the location indicated by the X mark above,
Through this through hole, power is distributed to Pa (i.e., terminal A) and Iw11Kg! It is configured to continue.

This structure is shown in an enlarged view in Figure 1!9. That is, by clamping the terminal to the power supply voltage vDD, the seventh
Exclusive OR transistor Q shown in the figure
, can be turned off and this circuit can be used as an inverter using the input terminal. On the other hand, regarding terminal AK, polysilicon P8. If connected to the wiring 12 in the power supply wiring @12@ through the same through hole 45 as above and clamped to the ground level ■□, the circuit in Fig. 7 will be turned on, so that the transistor Q1 will be turned on, so that the It can also be used as an inverter.

In this way, instead of leaving terminals that are not used for their original logic functions, they can be set to a predetermined potential vDD or (1) using a simple structure. Since IIc is fixed, the logic circuit itself will not malfunction. Further, since such fixing work can be easily performed for any gate electrode, the device for logic design or its modification can be made larger. Furthermore, the positions for potential fixing (clamping), that is, the positions of the through holes 44°45, are located at the polysilicon P8. This position can be determined in accordance with the system wiring pitch of automatic placement and wiring, which is very convenient. Moreover, since the through hole is formed on the field 5tOt film 31, the diffusion of AI in the wiring 11 deposited thereon is blocked by the thick field StO, film 11, and the gate breakdown voltage deteriorates in the channel portion of each FF2T. There will be no other adverse effects. On the other hand, if the through hole is formed on the channel part or the gate oxide film,
There is a risk that the etching solution may get into the gate oxide film while forming the through holes, causing deterioration of the gate breakdown voltage.
There is no such thing in this embodiment.0 Although the present invention has been illustrated above, the above-mentioned embodiment can be further modified based on the technical idea of the present invention.

For example, the pattern of the power feeding region described above can be modified in various ways, and the bending angle and shape of the polysilicon gate electrode are not limited to those described above, and can be modified in various ways. In addition, the gate electrode is a metal gate made of a material other than polysilicon, such as Mo8i, -polysilicon.
Or Aj Gate is fine. Note that the above-described unit cell structure may be applied to Exclusive NORkC, and of course can be applied to various other logic circuits.

The present invention, as described above, forms first and second high concentration regions near the source or drain region of 0MO8, and connects these regions with intra-cell wiring to control the substrate potential and well potential. Since the cell is configured to supply power to each cell, latch-up can be effectively prevented by equipping the cell itself with such a power supply function, and the chip size can also be significantly reduced to achieve high integration.

[Brief explanation of drawings]

The drawings show embodiments of the present invention, and FIG.
FIG. 2 is a schematic plan view of one of its logic blocks, FIG. 3 is a schematic diagram for explaining coordinates indicating the system distribution pitch, and FIG. Uni-IT cells (OMO) that make up the block
8 logic circuit), and FIG. 5 is a cross-sectional view taken along line X-X in FIG. 4, g6ilt! g4tm y-y line Ka
5 Vertical 111) r[Q, 117@ is the equivalent circuit diagram of gxclusive OR that constitutes the unit cell in Figure IIA,
Figure 8 is an enlarged plan view of a unit cell according to another embodiment,
The ninth section is a5 at 2-2@ in Fig. 4 showing another example.
FIG. Regarding the codes used in Fmm1lC, l is one block, 5 unit cell, 7tfP channel MO8PFiT part, 8 is N channel MO8PET part,
9 P+ type regions, 10 N'f' type regions, 11 to 15a
AJE■, 16-25.34-37 and 40,41.4
3! Contact hole, 28°38 and 39IfiN+
type power supply area, 30 and 42 are P+ type power supply areas, 44 and 45 are through holes, 1st layer AI wiring from 11 companies, 1 person
2 is the second layer M wiring, P8 and PS, ~P8. is a polysilicon gate electrode, and A-E and λ' to E' are terminals. Figure 1 Figure 3 Figure 4 ? Fifth
Figure 6 Figure 7 Figure 9 Continuation of Figure 1 Page 0 Inventor Shinji Kamitono 1-280 Higashi Koigakubo, Kokubunji City, Hitachi, Ltd. Central Research Laboratory 0 Inventor Katsuji Horiguchi 3-9-11 Midoricho, Musashino City 0 Inventor: Hiroshi Yoshimura Musashino Telecommunications Research Institute, Nippon Telegraph and Telephone Public Corporation, 3-9-11 Midoricho, Musashino City.0 Inventor: Ryota Kasai, Musashino Telecommunications Research Institute, 3-9-11 Midoricho, Musashino City. Applicant Nippon Telegraph and Telephone Public Corporation

Claims (1)

[Claims] 1. In a semiconductor integrated circuit device in which unit cells are connected by mutually arranged layers extending vertically and horizontally at a predetermined pitch on a semiconductor substrate, there are many unit cells composed of 0MO8. formed on the semiconductor substrate, and the 0MO8
A first insulated gate field effect transistor of the same conductivity type as the semiconductor base is located near the source or drain region of a first insulated gate field effect transistor of the first conductivity type provided in the semiconductor base to constitute the semiconductor base.
a source or drain region of a second insulated gate field effect transistor of a second conductivity type provided in a semiconductor region of a conductivity type opposite to that of the semiconductor substrate to constitute the OMO8; A second high-concentration region of the same conductivity type as this region is formed in the semiconductor region near the semiconductor region, and with both the Ill and the second high-concentration region disposed within the unit cell, a power supply The semiconductor substrate K is connected to the wiring within each cell.
A device characterized in that a potential of N1 is applied and a potential of Line 2 is applied to the semiconductor region. 2. The device according to claim 1, wherein the first and second high concentration regions are arranged to protrude from the source or drain regions, respectively. 3. The intra-cell wiring for power supply extends from above a portion of the source or drain region to above the protruding high concentration area, and the source or drain region and the high concentration 3. The device according to claim 2, wherein a predetermined portion of the gate electrode of the OMO8 is connected to the intra-cell wiring at a position where both regions do not exist.