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JPS59157332U - signal processing device - Google Patents

signal processing device

Info

Publication number
JPS59157332U
JPS59157332U JP1983050961U JP5096183U JPS59157332U JP S59157332 U JPS59157332 U JP S59157332U JP 1983050961 U JP1983050961 U JP 1983050961U JP 5096183 U JP5096183 U JP 5096183U JP S59157332 U JPS59157332 U JP S59157332U
Authority
JP
Japan
Prior art keywords
signals
processing device
signal processing
delay means
converter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1983050961U
Other languages
Japanese (ja)
Other versions
JPH039385Y2 (en
Inventor
赤井 孝至
克郎 岡本
臼井 支朗
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to JP1983050961U priority Critical patent/JPS59157332U/en
Publication of JPS59157332U publication Critical patent/JPS59157332U/en
Application granted granted Critical
Publication of JPH039385Y2 publication Critical patent/JPH039385Y2/ja
Granted legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図1は心電信号の1例を示す図、図2は低域微分処理に
おける理想周波数特性を示す図、図3は外部制御信号に
より加算と減算を切換えできる構成例を示す図、図4は
微分や平滑処理ができるプロセッサの構成を示す図、図
5は図4のプロセッサを木構造に配置した場合を示す図
、図6は本考案の一実施例を示す図。図7は本考案の動
作を説明するための波形図。
Figure 1 is a diagram showing an example of an electrocardiogram signal, Figure 2 is a diagram showing ideal frequency characteristics in low-frequency differential processing, Figure 3 is a diagram showing an example of a configuration in which addition and subtraction can be switched by an external control signal, and Figure 4 is a diagram showing an example of a configuration in which addition and subtraction can be switched by an external control signal. FIG. 5 is a diagram showing the configuration of a processor capable of performing differentiation and smoothing processing; FIG. 5 is a diagram showing a case where the processors of FIG. 4 are arranged in a tree structure; FIG. 6 is a diagram showing an embodiment of the present invention. FIG. 7 is a waveform diagram for explaining the operation of the present invention.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 入力生体信号を時系列のデジタル信号に変換するA/D
変換器と、前7A/D変換器からのデジタル信号を受け
てクロックのタイミングによる各種遅延時間をもつ複数
の信号を作る遅延手段と、前記遅延手段からの複数の信
号を受は所定のフィルタリング処理をするプロセッサと
、前記プロセッサの出力とその出力と同位相で前記遅延
手段から抽出された信号とを取り出す手段とを具備する
ことを特徴とする信号処理装置。
A/D that converts input biological signals into time-series digital signals
a converter, a delay means that receives the digital signal from the A/D converter and generates a plurality of signals having various delay times depending on the clock timing, and receives the plurality of signals from the delay means and performs a predetermined filtering process. What is claimed is: 1. A signal processing device comprising: a processor that performs the following steps; and means for extracting an output of the processor and a signal extracted from the delay means in the same phase as the output.
JP1983050961U 1983-04-06 1983-04-06 signal processing device Granted JPS59157332U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1983050961U JPS59157332U (en) 1983-04-06 1983-04-06 signal processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1983050961U JPS59157332U (en) 1983-04-06 1983-04-06 signal processing device

Publications (2)

Publication Number Publication Date
JPS59157332U true JPS59157332U (en) 1984-10-22
JPH039385Y2 JPH039385Y2 (en) 1991-03-08

Family

ID=30181391

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1983050961U Granted JPS59157332U (en) 1983-04-06 1983-04-06 signal processing device

Country Status (1)

Country Link
JP (1) JPS59157332U (en)

Also Published As

Publication number Publication date
JPH039385Y2 (en) 1991-03-08

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