JPS59155172A - Non-volatile semiconductor memory device - Google Patents
Non-volatile semiconductor memory deviceInfo
- Publication number
- JPS59155172A JPS59155172A JP58028514A JP2851483A JPS59155172A JP S59155172 A JPS59155172 A JP S59155172A JP 58028514 A JP58028514 A JP 58028514A JP 2851483 A JP2851483 A JP 2851483A JP S59155172 A JPS59155172 A JP S59155172A
- Authority
- JP
- Japan
- Prior art keywords
- silicon substrate
- oxide film
- floating gate
- insulating film
- projecting section
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
Landscapes
- Non-Volatile Memory (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の属する技術分野〕
本発明は、浮遊ゲートと制御ゲートを有する不揮発性半
導体メモリ装置に係り、特に電気的に書き換え可能なメ
モリ装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a nonvolatile semiconductor memory device having a floating gate and a control gate, and particularly to an electrically rewritable memory device.
浮遊ゲートを有する電気的に書き換え可能な不揮発性メ
モリとして、例えば第1図に示すものが知られている。As an electrically rewritable nonvolatile memory having a floating gate, for example, the one shown in FIG. 1 is known.
第1図の(8)は平面図であり(bl 、 (C)はそ
れぞれ(a)のA−A’、B−B’ 断面図である。(8) in FIG. 1 is a plan view, and (bl) and (C) are cross-sectional views taken along line AA' and line B-B' in (a), respectively.
P型シリコン基板(IJ)に形成され−t: n層m
(121) (122)。Formed on a P-type silicon substrate (IJ) -t: n layer m
(121) (122).
これらの一層(121)、(122)間に絶縁膜を介し
て積層された浮遊ゲート0制御ゲートIによりメモリト
ランジスタが構成されている。また一層(122)。A memory transistor is constituted by the floating gate 0 control gate I stacked between these layers (121) and (122) with an insulating film interposed therebetween. Even more (122).
(123)とこれらのn層層(122)、 (123)
間に絶縁膜を介して形成されたゲー)11極(I5)に
より選択用トランジスタが構成されている。記憶内容の
書き換えはn層IN (122)と連続的に形成された
一層(124)上にトンネル電流の流れつる薄い絶縁膜
(16)を介して浮遊ゲー) (13を延在させ工、浮
遊ゲー)(1→とn層(124)間の電荷の授受により
行なわれる。(17)はフィールド絶縁膜である。(123) and these n-layer layers (122), (123)
A selection transistor is constituted by a gate electrode (I5) formed with an insulating film in between. Memory contents can be rewritten by extending a floating gate (13) through a thin insulating film (16) through which a tunnel current flows over a layer (124) formed continuously with the n-layer IN (122). (1) is performed by transferring and receiving charges between the n-layer (124) and the n-layer (124). (17) is a field insulating film.
この様な構造のメモリトランジスタにおいては、通常の
書六込み条件(プログラム電圧(パルス)■pp=20
v、10m5)によって記憶内容な書き換えるには、ト
ンネル絶縁膜(161の厚さを〜120久程度に薄くす
る必要があり、素子形成方法及び、記憶内容と保持を保
障する上で問題点があった。In a memory transistor with such a structure, normal write conditions (program voltage (pulse) pp=20
In order to rewrite the memory contents using the tunnel insulating film (161), it is necessary to reduce the thickness of the tunnel insulating film (161 to about 120 m5), which poses problems in the element formation method and in ensuring the memory contents and retention. Ta.
即ち、前記書き込み条件で記憶内容の1゛き換えが可能
であれば、トンネル絶縁膜(161の厚さは厚い方が望
ましい。That is, if it is possible to change the memory contents by 1 under the above write conditions, it is desirable that the tunnel insulating film (161) be thicker.
本発明は上記の点に鑑みなされたもので、トンネル絶縁
膜厚を厚く保ちながら、通常の書き込み条件で書き換え
可能な記憶素子を提供する事を目的としている。The present invention has been made in view of the above points, and an object of the present invention is to provide a memory element that can be rewritten under normal write conditions while maintaining a thick tunnel insulating film.
本発明では第2図に示す如く、トンネル絶縁膜08を介
して凸型に形成されたシリコン基板(11)と浮遊ゲー
トαりが対向におり浮遊ゲー) (13)は凸型シリコ
ン基板端部な被う如く対向させる事により端部での電界
集中を起こし、厚いトンネル絶縁膜Oeを用いた場合に
おいても、通常の書き込み条件で書き換えの行える記憶
素子を実現している。尚、第2図(al 、 (b)は
、第1図(a)に平面図で示された記憶素子において、
本発明を用いた場合についてそれ、ぞれA−A’ 、B
−B’断面図を示している。In the present invention, as shown in FIG. 2, a silicon substrate (11) formed in a convex shape and a floating gate (13) are opposite to each other with a tunnel insulating film 08 interposed therebetween. By facing each other so as to cover each other, an electric field is concentrated at the end, and even when a thick tunnel insulating film Oe is used, a memory element that can be rewritten under normal write conditions is realized. Note that FIGS. 2(a) and 2(b) show that in the memory element shown in plan view in FIG. 1(a),
In the case of using the present invention, A-A' and B, respectively.
-B' cross-sectional view is shown.
本発明によれば、トンネル絶縁膜の厚さを厚くする事が
できるため、素子製造が容易となり素子製造の歩留りが
向上する。また、厚い絶縁膜で浮遊ゲートが被われるた
め、記憶情報の保持特性が良好であり、信頼性の高い素
子が実現できる。According to the present invention, since the thickness of the tunnel insulating film can be increased, device manufacturing is facilitated and the yield of device manufacturing is improved. Furthermore, since the floating gate is covered with a thick insulating film, the retention characteristics of stored information are good, and a highly reliable device can be realized.
次に、□本発明を実施例を用いて説明する。第3図(a
)に示す如く、P型シリコン基板(11)上に凸部形成
のためのマスク材(Lりを所望の形状に残置した後、シ
リコン基板1Bを除去し、凸部を形成する。次に、形成
された凹部に酸化膜Q31をシリコン基板(11)の表
面に一致する如く埋め込む(bl。次に、(C1に示す
如くシリコン基板aυの凸”部と埋め込まれた酸化膜u
3の一部を含む領域以外を被うマスク材(14)を残置
しシリコン基板aυ内のn+層a9の形成及び酸化膜(
13)の一部除去を行いシリコン基板aυの凸部表面よ
り酸化膜表面を後退させる。次に、(d)に示す如く、
シリコン基板Uの凸部にトンネル酸化膜αeを例えば2
00^成長させ多結晶ケイ素より成る浮遊ゲートa7)
を形成し、以降は公知の如く、制御ゲートを積層し、素
子を形成する。尚、本実施例では第3図(blの工程で
凹部への酸化膜の埋め込みを81基板表面にまで一致す
る如く行う場合について説明したが、埋め込みを途中ま
で行っても同様の効果を得る事ができる。Next, □The present invention will be explained using examples. Figure 3 (a
), after leaving a mask material (L) for forming a convex part on a P-type silicon substrate (11) in a desired shape, the silicon substrate 1B is removed and a convex part is formed.Next, An oxide film Q31 is buried in the formed recess so as to coincide with the surface of the silicon substrate (11) (bl. Next, as shown in C1, the convex part of the silicon substrate aυ and the buried oxide film u
A mask material (14) covering the area other than a part of 3 is left, and an n+ layer a9 is formed in the silicon substrate aυ and an oxide film (
13) is partially removed to retreat the oxide film surface from the convex surface of the silicon substrate aυ. Next, as shown in (d),
For example, 2 tunnel oxide films αe are formed on the convex portions of the silicon substrate U.
00^Floating gate a7) made of grown polycrystalline silicon
After that, control gates are stacked to form devices as is known in the art. In this embodiment, a case has been described in which the oxide film is buried in the recessed portion in the process shown in FIG. Can be done.
第1図(alは従来例を説明するための平面図、(b)
(C)はその断面図、第2図(a)(b)は本発明を説
明するための断面図、第3図(a)〜(dlは本発明の
一実施例を示す断面図である。
代理人 弁理士 則 近 憲 佑
(他1名)Fig. 1 (al is a plan view for explaining the conventional example, (b)
(C) is a sectional view thereof, FIGS. 2(a) and 2(b) are sectional views for explaining the present invention, and FIGS. 3(a) to (dl) are sectional views showing one embodiment of the present invention. .Representative: Patent Attorney Noriyuki Chika (and 1 other person)
Claims (1)
不揮発性メモリ装置において、前記浮遊ゲートへの電荷
の授受は、半導体基板表面に形成された前記半導体基板
と逆電溝型の高濃度不純物領域との間でトンネル電流の
流れうる薄い絶縁膜を介して行なわれ、かつM記高濃度
不純物領域は半導体基板上に形成された凸型領域表面に
形成されており、前記半導体基板の凸型領域の他の部分
は凸型領域表面が突出する如く、絶縁膜によって埋めら
れる如く形成されている墨を特徴とする不揮発性半導体
記憶装置。In an electrically rewritable non-volatile memory device having a floating gate and a control gate, charge is transferred to and from the floating gate through a process between the semiconductor substrate and a reverse trench type high concentration impurity region formed on the surface of the semiconductor substrate. The high concentration impurity region M is formed on the surface of a convex region formed on the semiconductor substrate, and is formed on the surface of a convex region formed on the semiconductor substrate. A non-volatile semiconductor memory device characterized in that the portion is filled with an insulating film so that the surface of the convex region protrudes.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58028514A JPS59155172A (en) | 1983-02-24 | 1983-02-24 | Non-volatile semiconductor memory device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP58028514A JPS59155172A (en) | 1983-02-24 | 1983-02-24 | Non-volatile semiconductor memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS59155172A true JPS59155172A (en) | 1984-09-04 |
JPH0427714B2 JPH0427714B2 (en) | 1992-05-12 |
Family
ID=12250788
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP58028514A Granted JPS59155172A (en) | 1983-02-24 | 1983-02-24 | Non-volatile semiconductor memory device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59155172A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5889304A (en) * | 1996-06-28 | 1999-03-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
-
1983
- 1983-02-24 JP JP58028514A patent/JPS59155172A/en active Granted
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5889304A (en) * | 1996-06-28 | 1999-03-30 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
Also Published As
Publication number | Publication date |
---|---|
JPH0427714B2 (en) | 1992-05-12 |
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