JPS61228672A - Insulated gate type non-volatile semiconductor memory and manufacture thereof - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an insulated gate nonvolatile semiconductor memory having a floating gate and a method for manufacturing the same.

[Conventional technology]

In recent years, insulated gate semiconductor nonvolatile semiconductor memories having floating gate electrodes have become widely popular due to their advantages such as ease of manufacturing and good retention characteristics. Among these, recently, highly integrated electrically erasable and rewritable non-volatile semiconductor memories (hereinafter referred to as EEFROMs) have begun to appear.

This EEP OMK is designed with memory transistors each having a lattice structure. However, among these, there is a thin insulating film (hereinafter referred to as tunnel insulating film) on the impurity diffusion layer on the substrate.
Fowler Nordheim inside (k'owler -N
(Ordheim) Memory transistors that utilize the electron tunnel phenomenon have the highest reliability and are suitable for large-capacity nonvolatile semiconductor memories. Next, EgFR of this structure
A conventional structure and manufacturing method of an OM memory transistor will be explained with reference to the drawings.

FIG. 5 is a sectional view showing the structure of a conventional memory cell. This memory cell is a selector transistor (hereinafter referred to as 8
eLTr. ) and memory transistor (hereinafter referred to as N
, Tr. ) and consists of trout. Here, 1 is a semiconductor substrate, 2 is a tunnel impurity diffusion layer which is a substrate side electrode for tunneling phenomenon, 31 is a 5all, Tr dreno impurity diffusion layer, 3b is an M, Tr dreno impurity diffusion layer, and 8eJ1. Tr source impurity diffusion layer, 3C is M,
This is a source impurity diffusion layer of Tr. Here, 3b is connected to the Doornel impurity diffusion layer 2. 4 is 8ejl,
5 is a gate insulating film of the Tr, 5 is an M, a first gate insulating film of the Tr, and 6 is a tunnel insulating film. A floating gate electrode 7 covers the M and Tr channel regions and covers the tunnel region via a tunnel insulating film 6 so as to serve as a counter electrode to the tunnel impurity diffusion layer 2 . 10 is an insulating film between gate electrodes on the floating gate 7% 11 is a control gate 11E of M, Tr
Extreme, 12 is Sej! , TrO gate electrode, 13 is an interlayer insulating film, 14 is 8eJ1. This is a Tr dreno electrode.

In this structure, electron injection into the floating gate electrode 7 is performed by M
, Tr control gate electrode 11, 8eA, high voltage t-8ej! to the Tr gate electrode 12! , Tr drain/electrode 1
This is done by applying a low voltage to 4 and using the electron tunneling phenomenon in the tunnel insulating film 6. For electron emission, set the control gate electrode 11 of M and Tr to a low potential, 867! , Tr+2) gate electrode 12 , 5e11. A high voltage is applied to the I'r drain/electrode 14, and an electric field in the opposite direction to the electron injection is applied to the tunnel insulating film 6.

Next, a method for manufacturing a memory cell with this conventional structure is shown in Fig. 6 (
This will be explained with reference to sectional views taken along the line 0B-337 in FIG.

First, as shown in FIG.
After forming, impurities are introduced onto the substrate.

) The t resist film 17 is patterned and reshaped using the well-known 7t resist technique so that only the tnonnel impurity diffusion layer 2 is exposed.

Thereafter, as shown in FIG. 6(b), after removing the insulating film 16t, the first gate insulating film 5 is formed. Next, the well-known step
Using the resist technique, a foot resist film 18 is formed in order to selectively etch only the region that will become the thin layer insulating film. Thereafter, after removing the first layer, a tunnel insulating film 6 is formed. Furthermore, a floating gate electrode material film 7a is formed.

Next, as shown in FIG. 6 (dl), the gate electrode insulating film l
A control gate electrode material film 11a is formed thereon. Thereafter, the control gate electrode material film 11a, the gate interelectrode insulating film 1O, and the floating gate electrode material film 7at are etched into a predetermined pattern, a source/drain impurity diffusion layer is formed on the substrate, and an interlayer insulating film 13 is formed. @This manufacturing method is an example of a conventional manufacturing method, and other examples are also known.

[Problem that the invention seeks to solve]

However, what these conventional manufacturing methods and structure examples have in common is that the step of forming the tunnel impurity diffusion layer 2t and the step of forming the tunnel insulating film region 6t are performed using separate photoresist masks. It is. Therefore, the process is long, and a margin portion for a predetermined alignment must be provided between the region boundary of tunnel impurity layer 2 and the region boundary of tunnel insulating film 6 on the tunnel structure. This margin portion prevents the reduction of M and Tr.

Forming the tunnel impurity diffusion layer and the tunnel insulating film in a self-aligned manner as described above greatly contributes not only to reducing the number of photoresist mask steps but also to reducing the size of M and Tr. One of the self-alignment formation methods is to make use of the difference in film thickness between the tunnel insulating film and the ml gate insulating film. One possible method is to form the impurity region only on the semiconductor substrate in the tunnel insulating film portion.However, this method requires that the first gate insulating film be thick enough to mask ion implantation.
, Tr=7 is unrealistic in terms of ductance deterioration.

Further, impurities are introduced into the substrate by ion implantation or the like using a patterned photoresist film on the first insulating film,
A method may also be considered in which the first insulating film is then removed only in the tunnel region to expose the substrate, the photoresist film is removed, and then a tunnel insulating film is formed. However, in this method, when the T resist film is removed, the substrate surface in the tunnel impurity region is exposed and remains intact, so the substrate surface is affected and a good quality tunnel insulating film cannot be obtained.

An object of the present invention is to provide an insulated gate nonvolatile semiconductor memory having a nine memory cell structure suitable for high integration, which is capable of forming a high-quality tunnel insulating film in a self-aligned manner with a tunnel impurity diffusion layer, and a method for manufacturing the same. Our goal is to provide the following.

[Means for solving problems]

The insulated gate nonvolatile semiconductor memory of the present invention includes a first semiconductor memory of an opposite conductivity type formed on one principal surface of a semiconductor substrate of one conductivity type.
．． a second impurity diffusion layer; a channel region in which the first impurity diffusion layer is a drain and the impurity diffusion layer of sR2 is a source; a first insulating film provided to cover the channel region; a floating gate electrode of 8gl provided in contact with the first insulating film, a second insulating film provided so as to cover the first floating gate electrode, and an opposite conductive film connected to the first impurity diffusion layer. The third impurity diffusion layer is thinner than the first insulating film provided on the surface of the third impurity diffusion layer. a second floating gate electrode provided in contact with the second insulating film and the third insulating film, and a fourth insulating film provided so as to cover the second floating gate electrode. and a control gate electrode provided so as to be in contact with the fourth insulating film. The area boundaries substantially coincide with each other.

Further, the method for manufacturing an insulated gate nonvolatile semiconductor memory of the present invention includes the steps of forming a first insulating film on one main surface of a semiconductor substrate of one conductivity type, and forming a first floating film on the first insulating film. forming a gate electrode material film; providing an opening in a predetermined region of the first floating gate electrode material film; and using the floating gate electrode material film as a mask, impurities are removed from the semiconductor below the opening. a step of exposing the surface of the semiconductor substrate under the opening using the first floating gate electrode material film as a mask; and a step of introducing a third insulating I [tube formation At the same time, the first
forming a second insulating film on the floating gate electrode material film; and forming a second floating gate electrode material film on the second insulating film and the third insulating film. There is.

〔Example〕

The present invention will be explained in detail below based on examples.

FIG. 1(al) is a cross-sectional view showing the structure of a memory cell according to an embodiment of the present invention, and FIG. 1(b) is a cross-sectional view of FIG.
It is a sectional view taken along the line A'. The memory cell consists of a memory transistor (M, Tr) and a selector transistor (8eL).
Tr).

Here, 21 is a semiconductor substrate, 22 is a tunnel impurity diffusion layer, and 23ari8eJL is a Tr drain impurity diffusion layer.

23b is M, Tr Doornel impurity diffusion layer, 8
It also serves as the eCTr source impurity diffusion layer and is connected to the tunneler impurity diffusion layer 22. 24 is aeJ! ,Tr
25 is a first gate insulating film of M, Tr, 26 is a tunnel insulating film, and 27 is a first floating gate electrode which covers the M, Tr channel region. 28 is a second gate insulating film on the first floating gate electrode, and 29 is a second floating gate electrode that covers the floating gate electrode 1h27 of Ill and the tunnel insulating film a26. 30 is a third gate insulating film on the second floating gate electrode, and 31 is an M, Tr control gate electrode. 32 is 8ej! , gate electrode of Tr,
33 is an interlayer insulating film, and 34 is an 8efi, Tr drain electrode.

A feature of this structure is that the tunnel insulating film 26 is provided so as to coincide with the first layer and is in contact with the second floating gate electrode 29 .

Next, a method for manufacturing a memory cell with this structure is shown in FIG. 2(a).
Each step will be explained in accordance with the structural diagram in the same cross section as FIG. 1 (bl) shown in (d).

First, as shown in FIG. 2(a), after forming an insulating film 35' for element isolation in a predetermined region on a semiconductor substrate 21, M, T
r 07JA 1 (A first floating gate electrode material film 27a is formed on the D gate insulating film 25'i-1 and the first gate insulating film 25. After that, the tunnel insulating film region is made into an opening) t resist The film 37 is formed using a well-known photophosphorography technique.

After this, as shown in Figure 2 (b), the floating gate electrode material film 27! The photoresist film 31 is removed after etching and forming an opening. Next, impurities are introduced into the semiconductor substrate 21 using the whl floating gate electrode material film 27a as a t-mask, and the t-channel impurity diffusion layer 22t is
- form. After that, the first gate insulating film 2 on that area is
5 is removed to expose the surface of the semiconductor substrate 21.

Next, as shown in FIG. 2 (cl), a tunnel insulating film 26 is formed on the tunnel impurity diffusion layer 22.
A second gate insulating film 28 is simultaneously formed on the floating gate electrode material film 27a. Then the second floating goo)i
K pole material peritoneum 29a is formed, and the first. A photoresist film 38 that determines the width of the second floating gate electrode in the direction perpendicular to the channel is formed using a well-known photolithography technique.

Next, as shown in FIG.
8T-mask, second floating gate electrode material film 29
a, second gate insulating film 28. T-etch the first floating gate electrode material film 27a.

After that, a 30th gate insulating film 30 is formed, and a control gate electrode material film 31a is formed thereon. After this, a control gate electrode material film 31! , third gate insulating film 30. Second
floating gate electrode material film 29a, second gate insulating film 2
8 and the first floating gate electrode material film 27a are etched into a predetermined pattern. Further, source/drain impurity diffusion layers 23a123b and 23C are formed on the semiconductor substrate 21, and interlayer insulating films 33 and 8eJ1. A transistor drain/pole 34'e is formed to obtain the memory cell of this embodiment shown in FIGS.

As soon as the predetermined pattern is formed, impurities are introduced into the substrate and the tunnel insulating film is formed using the first floating gate electrode material film 27a as a mask, so that the tunnel insulating film 26 and the tunnel impurity diffusion layer 22 are The boundaries of both regions are formed to substantially coincide with each other in self-alignment after the 17t resist mask process. Further, the substrate surface on the tunnel impurity diffusion layer 22 is not affected when the resist is removed, and a tunnel insulating film 26 of extremely high quality can be obtained.

FIG. 3(a) shows a schematic flannel showing the planar structure of the above embodiment. Next, the operation of this embodiment will be explained with reference to these drawings.

When injecting electrons into the floating gate electrode, 8ei.

A high voltage is applied to the Tr"r-) electrode 32 and the control gate electrode 31, and the drain electrode 34 of the Tr is fixed at a low potential. Electrons are transferred from the tunnel impurity diffusion layer 22 to the WL2 via the tunnel insulating layer 26. When emitting electrons from the second floating gate electrode 29, the control gate middle electrode 31' is fixed at a low potential, and the voltages of 8ej!, Tr gate electrode 32, 8ej1.Tr are injected into the floating gate electrode 29. A high voltage is applied to the drain electrode 341C.Thereby, electrons are emitted from the second floating gate electrode 29 to the tunnel impurity diffusion layer 22.

At the time of reading, voltages V CG , 5eJl , T are applied to the control gate electrode 31 of M and Tr (CG of C1 in the same figure).
A voltage VD is applied to the drain electrode 34 of r. At this time, the potential VFGI11 of the first floating gate electrode 27, which is the effective gate voltage of M, Tr, is set to the voltage V(g, Vo
and the capacitance between each electrode CFDC (the capacitance between the second floating gate electrode and the drain electrode) *CFC (@2 floating gate electrode -
(capacitance between control gate electrodes), Crt (capacitance between first and m2 floating gate electrodes), and ICFg (capacitance between first floating gate and substrate). Among these, the capacitance OFF has a very large value compared to other capacitances because the insulating film between the electrodes is the thin second gate insulating film 28 formed at the same time as the tunnel insulating film 26, and the direct product of the electrodes is large. . Therefore, VFGI
becomes almost the same potential as vrog. Charges are accumulated in the second floating gate electrode 1fk29 due to the electron injection or emission described above, causing a fluctuation in the second floating gate electrode potential vrat.

However, the first floating gate electrode potential VFGI 4 Vr
Since it has almost the same potential as os, similar potential fluctuations can be obtained. Therefore, the channel current corresponding to the accumulated charge is M.

It will flow through TrQl.

FIG. 4 is a schematic plan view showing a memory cell transistor according to another embodiment of the present invention.

In this embodiment, the first floating gate electrode &27 and the second floating gate electrode 29 in the embodiment shown in FIG. 4 are connected. This is done by adding a foot resist mask step and selectively etching the second gate insulating film 28t to form the opening 36 after forming the tunnel insulating film 26 and the second gate insulating film 2B. achieved. In other words, the first (
D floating gate electrode 27 and second floating gate electrode 29 are connected through this opening 36 . In this case VFGI
``VFGI'', and the charge on the second floating gate electrode 29 spreads to the first floating gate electrode 27, giving an effective gate voltage.In this case, the disadvantage is that the number of steps increases, but the main purpose of the present invention is tunneling. There is no difference from the previous embodiment in that the insulating film and tunnel impurity diffusion layer can be manufactured in a self-aligned manner.

〔Effect of the invention〕

As described above in detail, according to the present invention, it is possible to form a tunnel insulating film and a tunnel impurity diffusion layer in a self-aligned manner with their region boundaries substantially aligned. Therefore, in the multi-layer cell structure to which the present invention is applied, there is no need to set an extra alignment margin between the impurity diffusion layer region and the tunnel insulating film region, and the cell area can be reduced. 12) When introducing the nonel impurity diffusion layer, the mask material is a floating gate electrode material film.9.The impurity diffusion layer can be formed by the same method as the well-known method of introducing self-aligned impurities when forming source/drain electrodes. Since the substrate surface of the tunnel impurity diffusion layer can be manufactured while always being protected with an insulator, it is possible to form a high quality tunnel insulating film.

Therefore, according to the present invention, an insulated gate nonvolatile semiconductor memory having memory cells of high quality and suitable for high integration can be obtained.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are cross-sectional views showing a memory cell of an embodiment of the present invention, and FIGS. 6(a) to (dl
is a cross-sectional view of the main manufacturing process. 21...Semiconductor substrate, 22...Tunnel impurity diffusion layer, 23a, 23b, 23C...
Source drain/impurity diffusion layer, 24...gate insulating film, 25...gate insulating film of wll, 2
6...Tunnel insulating film, 27...I!
1 floating gate electrode, 27m... floating gate electrode material film of sBl, 28... second gate insulating film, 29... second floating gate electrode, 29・・・
...Gate electrode, 33...Interlayer insulating film, 3
4... Drain chisel electrode, 35... Insulating film for element isolation, 36... Opening part, 3'1.3g.
...Futresist film. East f Toki￥-2＠ 3chi'V=4ヅ茅! r drama 11) l victory

Claims (3)

[Claims] (1) First and second impurity diffusion layers of opposite conductivity type formed on one main surface of a semiconductor substrate of one conductivity type, and using the first impurity diffusion layer as a drain and the second impurity diffusion layer as a drain. a channel region serving as a source, a first insulating film provided to cover the channel region, a first floating gate electrode provided in contact with the first insulating film, and the first floating gate electrode. a second insulating film provided to cover the first impurity diffused layer, a third impurity diffused layer of an opposite conductivity type connected to the first impurity diffused layer, and a third impurity diffused layer provided on the surface of the third impurity diffused layer. a third insulating film thinner than the first insulating film; a second floating gate electrode provided in contact with the second insulating film and the third insulating film; An insulated gate nonvolatile semiconductor memory including a fourth insulating film provided to cover the fourth insulating film and a control gate electrode provided in contact with the fourth insulating film, the region of the third impurity diffusion layer An insulated gate nonvolatile semiconductor memory characterized in that a boundary substantially coincides with a region boundary of the third insulating film. (2) The insulated gate nonvolatile semiconductor memory according to claim (1), wherein the first floating gate electrode and the second floating gate electrode are electrically connected. (3) forming a first insulating film on one main surface of a semiconductor substrate of one conductivity type; forming a first floating gate electrode material film on the first insulating film; a step of providing an opening in a predetermined region of the floating gate electrode material film; a step of introducing an impurity into the semiconductor substrate under the opening using the floating gate electrode material film as a mask; and a step of introducing an impurity into the semiconductor substrate under the opening. exposing the surface of the semiconductor substrate under the opening using an electrode material film as a mask; forming a third insulating film on the exposed semiconductor substrate surface; and simultaneously forming a third insulating film on the first floating gate electrode material film. an insulated gate type nonvolatile semiconductor comprising the steps of: forming a second insulating film; and forming a second floating gate electrode material film on the second insulating film and the third insulating film. Memory manufacturing method.