JPS59148370A - Metallic oxide semiconductor field effect type semiconductor device - Google Patents

Abstract

PURPOSE:To improve the write efficiency of an FPROM and contrive to increase the withstand voltage by a method wherein a semiconductor layer of a low impurity concentration and that of a high one are provided on the same semiconductor substrate, and a memory transistor is formed at the region of a high impurity concentration, and the other transistor at the region of a low one. CONSTITUTION:A semiconductor single crystal growth layer 24 of a low impurity concentration of the same conductivity type is formed on the semiconductor substrate 23 of a high impurity concentration of one conductivity type, and, in the grown layer 24, the region 25 of the same conductivity type and higher impurity concentration than that of said layer 24 which reaches from the main surface of said layer 24 to the substrate 33 is formed. The EPROM memory transistor 21 is formed in the region 25, and the peripheral circuit transistor 22 is formed in the grown layer 24. Therefore, the write efficiency is improved, and the source-drain withstand voltage can be increased by forming the memory transistor at the region of a high impurity concentration.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an MO8 field effect semiconductor device, and particularly to an MO8 field effect semiconductor device including a nonvolatile memory device.

[Prior art]

In recent years, the exhibition of non-volatile MO8O8 type conductor devices has seen a remarkable number of various products being devised, announced, or put into practical use. A very high voltage is applied or generated internally.Therefore, the MOS transistor that controls this programming voltage (hereinafter referred to as Vp) and the nonvolatile memory transistor to be programmed must be set at a high voltage so that they will not be destroyed even if Vp is applied. To increase the voltage resistance of peripheral transistors other than memory cells, technologies such as double gate type high voltage transistors and offset type high voltage transistors are known. However, these technologies are not suitable for memory cells. It is difficult to apply this method to memory transistors because it causes deterioration of programming efficiency in transistors. Generally speaking, due to this limitation, in memory transistors, it is not possible to have a large voltage difference between the voltage at which programming starts and the withstand voltage. This will be explained using the most common type of nonvolatile memory device, EFROM (ultraviolet erasable electrically programmable nonvolatile memory device).

FIG. 1 shows a cross-sectional view of the structure of a conventional N-channel EPROM device. 1 is an E P ROM memory transistor, and 2 is a peripheral single-gate type MO8) transistor.

Furthermore, 3 is a substrate of one conductivity type, 4 is an insulating film for isolation between elements,
5 is an impurity diffusion layer forming a source/drain region; 6
7 is a high concentration channel doping region having the same conductivity type as the substrate introduced to make EPROM programming efficient; 7 is a floating gate electrode specific to the EPROM memory transistor; 8 is a memory transistor control gate electrode; 9 is a memory transistor control gate electrode; Peripheral transistor gate electrode, lO
1 is a first gate insulating film of the memory transistor, 11 is a second insulating film, and 12 is a peripheral transistor gate insulating film. Programming of this device involves applying a high voltage to the drain and applying a voltage to the control gate electrode 9 so that the channel is in a pinch-off state, and moving high kinetic energy electrons, which are generated by being accelerated and scattered by the electric field in the depletion layer, into the vicinity of the drain. is injected into the floating gate by the electric field. This programming mechanism generates a large number of electron-hole pairs in the depletion layer near the drain. Among these holes, the holes are injected into the substrate 3 as a substrate current. This substrate current increases depending on the increase in channel surface concentration, but this fact has already been extensively studied and published4 (e.g. L ij j'ap
anese J-own 'of GH-ed
Phyi. s, Vo115, No 6.1127~1
133 (1976), Takao Kanata M
Ginshi y Naha゛5 YshitokeA 7”u 7
″°Kyozi Tanabashi and K
eizo Kobayashi). - Since this substrate current flows through the substrate resistance, the substrate 3 is biased to the positive side, and the bottom of the barrier of the junction 3 on the source side eventually becomes forward biased, and the parasitic current formed from the source-substrate-drain When a bipolar transistor is ONI, a large amount of electrons are injected from the source to the drain. In this mode, the drain current increases extremely, causing abnormal programming of the memory transistor, Junson glass breakdown, gate short-circuit breakdown, etc.

It is well known that in order to improve the write efficiency in the conventional EFROM structure described above, it is sufficient to increase the impurity concentration in the region 6, but as explained above, the substrate current also increases accordingly. The withstand voltage between the source and drain of the memory transistor decreases due to an increase in the drain current due to the parasitic bipolar transistor. It has already been predicted that in order to prevent this decrease in source-drain breakdown voltage, it would be necessary to lower the substrate resistance based on the mechanism by which it occurs. (Reference, 1978 f) 'i'get't 'o'
f T'ec Mayuzhi o1o horse mackerel 〇-to 6-
Yi 418/min-mole di 1-1, -Wu-teyud rainbow~ 7,1 one person Paper, P47B,
E, Sun, J, Mail, J, Berger a.
However, in a nonvolatile memory device, in addition to memory transistors, transistors constituting a read operation control circuit, a programming operation control circuit, etc. must be integrated on the same substrate. Therefore, the board 3
Applying a high-concentration impurity substrate with low substrate resistance to transistors that do not require high breakdown voltages will have negative effects such as an increase in T, an increase in junction capacitance, and a decrease in junction breakdown voltage, making it impossible to achieve high-speed readout functions. Then it becomes impossible.

[Purpose of the invention]

The present invention was made in response to the above problems, and includes a non-volatile memory device that improves writing efficiency, stabilizes operating characteristics, and simultaneously achieves high withstand voltage.
The present invention provides a field effect semiconductor device.

[Structure of the invention]

The present invention provides - a semiconductor single crystal growth layer formed on a conductivity type semiconductor substrate, the semiconductor single crystal growth layer having the same conductivity type as the substrate and having an impurity concentration lower than that of the substrate; an impurity region having the same conductivity type as the substrate and having a higher impurity concentration than the semiconductor single crystal growth layer, which is formed to reach the substrate from the main surface of the growth layer; and at least one of the semiconductor single crystal growth layers. It is characterized by comprising a field effect transistor whose channel region is the main surface of the crystal growth layer, and a field effect transistor whose channel region is the main surface of at least one of the high concentration impurity regions. It is found in NO8 field effect semiconductor devices.

〔Example〕

The present invention will be explained below based on Examples. FIG. 2 is a sectional view showing an example in which the present invention is applied to an EPROM device. In the figure, 21 is an EPROM memory transistor, 22 is a peripheral transistor, and 23 is a high impurity concentration substrate of one conductivity type. , 24 is a low impurity concentration substrate grown on the substrate 23 and has the same conductivity type as 23, and 25 is an E
This is a high impurity region selectively introduced only into the PROM memory transistor formation region. This region has a depth reaching from the substrate surface to the high impurity concentration substrate 23, and its concentration is set to a concentration necessary for memory transistor programming. 26 is an insulating film for isolation between mineral elements; 27 is a spreading layer region of a conductivity type opposite to that of the substrate forming source/drain regions; 28 is a floating gate electrode; 29 is a memory transistor control electrode; 30 is a peripheral transistor electrode;
31 is the first gate insulating film of the memory transistor;
2 is a second gate insulating film, and 33 is a gate insulating film of a peripheral transistor. This structure makes it possible to form only the memory cell transistor in the high concentration substrate. Moreover, the high concentration impurity region 15 is the high concentration impurity substrate 13.
has reached. In this structure, for example, I
There is no problem in using a low resistance substrate having an impurity concentration of cm 2 or more.

Therefore, the actual substrate resistance value can be made extremely small compared to the conventional example. Therefore, even if the same substrate current flows, the amount of positive bias of the substrate becomes smaller.

This increases the allowable substrate current that can flow until the biboral 2 transistor, which flows from the aF/- source, substrate, and drain, is turned on. ” can be rephrased as “ The substrate current generation efficiency is the same as that of the conventional channel doping method if the impurity concentration on the channel surface is the same. Since the substrate current increases depending on the source-to-drain voltage, an increase in allowable substrate current means an increase in the source-drain voltage at which the bipolar transistor consisting of the source, substrate, and drain is turned on, or the withstand voltage between the top and drain. are doing.

By forming the source/drain regions in high concentration impurity regions in this manner, it is possible to increase the breakdown voltage between the source and drain.

However, the write efficiency of a memory transistor does not change as long as the impurity concentration on the channel surface remains the same. Therefore, even in the structure according to the present invention, if the channel surface concentration is made the same as that in the conventional channel doping method, the writing efficiency does not change and the same programming as in the conventional method can be realized.

FIG. 3 shows IV curves of a conventional memory transistor and a memory transistor according to the present invention before and after glodaling.

After programming, the effective threshold voltage increases due to charge accumulation in the floating gate, but the strain current value decreases. The samples are N-channel EPROMs with the same channel length, and the impurity concentration on the channel surface is 2X.
10 cm, and 20 V is applied to the control gate electrode. In the conventional memory transistor and the memory transistor according to the present invention, the source point where charge starts to be injected into the floating gate.
The drain-to-drain voltage is the same at 8. However, after programming, the sample according to the present invention showed a higher source-to-drain breakdown voltage. When actually designing a device, it is necessary to set the source-drain voltage during programming with a margin for both the voltage at which charge injection starts and the source-drain breakdown voltage.
The method of the present invention that allows a large difference between the two voltages mentioned above can provide a margin for the amount of variation in the program voltage when manufacturing a product, making circuit design easier and improving the yield rate of products. I can do it.

Actually, by applying the present invention, the impurity concentration of the substrate was reduced to 1×8 −3 10 cm, and the impurity density of the low impurity concentration growth layer on the substrate was reduced to I.
×10cm, high temperature impurity region impurity density 2×
When an N-channel, channel injection type EP ROM device was fabricated with the setting of 10 cm, the source-drain voltage at the start of channel injection and the source-drain breakdown voltage after programming were 8 V, respectively.
and 16V was obtained. 2×10 on a substrate with impurity concentration of 1×10 cm by conventional channel doping method
The source-drain breakdown voltages of an E F ROM device with a surface concentration of crn were 8 V and 12 V after channel injection initiation and programming, respectively. Finally, when the present invention is applied to an EP ROM device, the source-drain breakdown voltage can be increased to 4V without changing the write start voltage. Furthermore, according to the uninvented method, even if a large number of memory transistors are integrated, by connecting electrodes to the substrate and fixing the substrate potential, the substrate resistance value can be made the same for all memory transistors, so the same substrate bias state can be achieved. It can be made to work. Therefore, there is little variation in characteristics depending on the position within the cell array. Furthermore, since the substrate current generated in the memory transistor is immediately absorbed through this electrode, it has little effect on the operation of peripheral transistor circuits.

Furthermore, since the substrate has a high impurity concentration, the lifetime of minority carriers is short, and even if a dynamic RAM or the like that stores a small amount of charge in a capacitor is integrated on the same substrate, there is little adverse effect due to substrate drift of minority carriers. Therefore, the present invention is highly effective even when manufacturing a high-performance microprocessor with a built-in nonvolatile memory.

Although the above embodiment has been described with respect to an EP ROM, its programming method may be a channel injection method or an avalanche injection method. In either case, the impurity concentration of the high concentration impurity region 15 is high in rotation.
The write efficiency is good, and the source-drain breakdown voltage also increases as the impurity concentration increases.

Furthermore, it is also possible to integrate transistors other than memory transistors within the high concentration impurity region 15. In this case as well, it is possible to increase the breakdown voltage between the source and drain. However, in that case, the junk storage capacity,
Since an increase in threshold voltage and a decrease in breakdown voltage occur, consideration must be given to the type of transistor used.

It is possible to separately adjust the threshold voltage by shallowly doping only the channel surface with an impurity of a conductivity type opposite to that of the substrate.

However, even if this is done, the substrate resistance itself remains unchanged, so the effect of increasing the withstand voltage according to the present invention is not impaired.

Further, the channel type of the memory transistor may be either N type or P type, and the circuit configuration of the peripheral transistor formed in the low concentration impurity region may be not only a single channel type but also a complementary type transistor circuit.

[Effects of the Invention] As described above, according to the present invention, an MO8 field-effect semiconductor device including a non-volatile memory device that improves write efficiency, stabilizes operating characteristics, and achieves high breakdown voltage at the same time. can be easily obtained.

[Brief explanation of the drawing]

FIG. 1 is a structural sectional view of a conventional EPROM device, and FIG. 2 is a structural sectional view of an EPROM device according to an embodiment of the present invention.
Figure 3 shows the I-V% of the channel injection type EPR/0M device.
It is a sex diagram. 1.21...Memory transistor, 2,22
...Peripheral transistor, 3...Substrate,
4.26... Inter-regulator isolation insulation discharge, 5.27...
...Impurity region for forming source/drain regions, 6.
...high impurity channel doping region for programming, 7,28... floating goo), 8.29
...Memory transistor gate electrode, 9.3
0... Peripheral transistor gate electrode, 10.3
1... Memory transistor first insulation, 11
．． 32...Memory transistor second insulating film,
12.33... Peripheral gate insulating film, 23...
. . . High impurity concentration substrate, 24 . . . Low impurity concentration single crystal growth layer, 25 . . . High impurity region. 1st item 3 Fig. 2

Claims (4)

[Claims] (1) - A semiconductor single crystal growth layer formed on a conductivity type semiconductor substrate, the semiconductor single crystal growth layer being of the same conductivity type as the substrate and having a lower impurity concentration than the substrate, and the semiconductor single crystal growth layer being formed in the semiconductor single crystal growth layer. an impurity region having the same conductivity type as the substrate and having a higher impurity concentration than the semiconductor single crystal growth layer, which is formed to reach the substrate from the main surface of the growth layer; and at least one of the semiconductor single crystal growth layers. A field effect transistor whose channel region is the main surface of a crystal growth layer;
An MO8 field effect semiconductor device comprising: a field effect transistor whose channel region is the main surface of at least one high concentration impurity region. (2) A field effect transistor having a main surface on a highly concentrated impurity region as a channel region has a gate insulating film formed on the impurity region, and a field effect transistor having a gate insulating film formed on the impurity region so as to cover at least the channel region. The MO8 field effect semiconductor device according to claim 1, further comprising a floating gate electrode provided electrically insulated from other parts. (3) A field-effect transistor whose main surface on a highly concentrated impurity region is a channel region includes a gate insulating film formed on the impurity region and a gate insulating film that covers at least the channel region. and a floating gate electrode provided electrically insulated from other parts;
Claim 1, characterized in that it has a second insulating film formed to cover the surface of the floating gate electrode, and a control gate electrode provided so as to be in contact with the second insulating film. ) MO8 field effect semiconductor device according to item 1. (4) The impurity concentration of the semiconductor substrate is lXl0 cm
With the above, the impurity concentration of the semiconductor single crystal layer is lXl01
If the impurity concentration of the impurity region with a high concentration is less than 6 cm and is higher than I
Claim No. (1) characterized in that the number is less than 3.
or MO8 described in paragraph (2) or paragraph (3)
7g, field effect semiconductor device.