JPS59136790A - Musical sound generator - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a musical tone generating device, and more particularly to a musical tone generating device that simulates natural musical instrument sounds by manipulating the shape of a musical sound waveform and changing it over time.

Conventional configurations and their problems Traditionally, methods that simulate natural musical instrument sounds include those that use a sine wave synthesis method, those that use a frequency modulation method, and those that use a subtraction method (mainly analog processing with VCO).

Methods using VCF, VCA, etc.) have been proposed, but these have problems such as large circuit scales that are difficult to realize, and limitations in terms of method.

OBJECTS OF THE INVENTION An object of the present invention is to provide a musical tone generating device that can simulate natural musical instrument sounds with a simple configuration and can prevent discontinuities occurring at waveform joints.

Structure of the Invention The musical tone generating device of the present invention comprises a waveform memory that stores at least two or more musical sound waveforms in the form of digital values from among a plurality of musical sound waveforms from the beginning of the musical tones until the end of the musical tones. , a mate clock generation unit that determines the timing of the start, a waveform readout unit that reads out two waveform sample data from the waveform memory based on the output signal of the mate clock generation unit, and a waveform readout unit that reads out two waveform sample data from the waveform memory based on the output signal of the mate clock generation unit; The waveform calculation unit includes a waveform calculation unit that forms a musical sound waveform using two waveform sample data, and a conversion unit that converts the digital output signal of the waveform calculation unit into an analog signal, and the calculations executed by the waveform calculation unit include: A waveform interpolation operation is performed using the two waveform sample data read out by the waveform reading section to obtain a virtual waveform sample value, and a musical tone synchronized with the note clock is generated.
It is possible to generate a musical sound waveform close to a natural instrument sound by changing the shape of the musical sound waveform over time, and since adjacent waveform sample data determines virtual sample values, discontinuities that occur at waveform joints can be prevented. I can do it.

DESCRIPTION OF EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. First, the principle of the present invention will be explained. FIG. 1 shows the musical sound waveform of the first musical tone interval extracted discretely.

The relationship between the time elapsed from the start of pronunciation and the musical sound waveform is shown below.

Musical sound waveform Time elapsed D 320m5 (4) E 720m5 As can be seen from Fig. 1, the shape of the musical sound waveform changes with the passage of time.0 The present invention focuses on the temporal shape change of the musical sound waveform, By applying time-varying changes to the shape of the waveform, Ic generates musical sounds that are typical of natural musical instruments.

Explanation of the contents stored in the data memory Figure 2 shows an example of the envelope envelope state of a musical sound waveform from the start of sound generation to the end of sound generation. Labor division (Il0.1.
. . .Iil . FIG. 3 shows an example of selected and extracted tone waveforms. N waveform sample values obtained by dividing one cycle of one extracted musical sound waveform into N, that is, N x waveform sample values, and control data used when generating musical tones (in the present invention, The control data for performing the insertion is stored in the data memory.

Explanation of the waveform interpolation method The waveform interpolation method is as follows: ■ Divide and selectively extract the sample wave from position i to i+1 (Il0, 1, 2°...
l-1), one cycle of the musical sound wave repeats M times, and the waveform sample/(X, , n), ! ;
'(Iil1.n) to calculate an approximate value by calculating the waveform sample value of the virtual sample value point that exists between '(Iil1.n). The interpolation formula is shown below.

+f(Xi,n)・4...Song・Song・(1) i is the sample position extracted by dividing ■ and is the waveform number@
(io, t, 2, . . . , Il-1) represents a position in the middle of the M-cycle transition between waveform numbers 1 and i+1. (m=o, 1, 2, -
, M-1)n is a sample position obtained by dividing one cycle of the musical sound waveform into N, and is a waveform sample NAND.

(n-0, 1, 2, =-, N-1) As can be seen from Figure 4 (a), which shows an example of interpolation using equation (1), discontinuities occur at the joints of the waveforms. are doing. If the level difference between these discontinuous points is large, it may cause an audible problem as an unnecessary noise component. Therefore,
In this example, by adding a correction term to equation (1),
As shown in Figure 2, the occurrence of discontinuous points is prevented. An interpolation formula obtained by adding a correction term to formula (2) is shown below.

/ (Xl, rn, n) - (f(X4+,, fl)
-/ (Xi, n) Description of how to add an envelope There are two types of musical tones: an organ-type envelope and a piano-type envelope. Figure 5 shows an example of adding organ-shaped and piano-shaped envelopes.
is an organ type, and (b) is a piano type.

In this explanation, unlike the previous example, the waveform stored in the data memory is not the waveform until the end of sound generation, but the stationary part of the musical tone or the point where the waveform shape is stable, and subsequent waveform generation is stored in the data memory. The last memorized waveform shall be used repeatedly.

Explanation of Organ Type When the key signal is turned on at point A in FIG. 5, a musical tone is synthesized by performing waveform interpolation using the waveform data in the data memory. Then, when time advances to point B, the final waveform data is reached, and the final waveform repeats. Thereafter, when the key signal turns off at the 0 point, the envelope signal has an attenuation characteristic and the multi-output waveform attenuates.

Description of Piano Type When the key signal is turned on at point A in FIG. 5, waveform data in the data memory is used to perform waveform interpolation to synthesize musical tones. Then, when it advances to point B, it becomes the final waveform data,
Thereafter, as the final waveform data is repeatedly used, the envelope signal enters the attenuation characteristic state, and the output waveform attenuates in accordance with the attenuation characteristic.

Description of how to generate pitches To determine a pitch, a clock signal corresponding to a 12-tone scale is generated. Regarding the octave relationship, pitches related to the octave are generated by changing the number of samples of one period of the tone waveform stored in the data memory.

If the co sound is 512 samples, the scale clock signal is 82.708H2 x 512 samples" = 16.74
It becomes KHz. Table 1 shows the scale clock frequency, and Table 2 shows the number of waveform samples and the octave relationship.

'Next, one embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram of an electronic musical instrument employing the musical tone generating device of the present invention. (601) is the key, armor part (
KB), (602) is the operation unit (TAB), which is composed of a tone tablet switch, a vibrato effect on/off switch, a glide effect on/off switch, etc.
608) is a central processing unit (CPU) similar to that used in computers, and (604) is a read/write storage device (random access memory with RA
M), (605) is a read-only storage device (605) in which a program that determines the operation of the CPU (608) is stored.
The read-only memory (RAM), (606) stores waveform samples in Table 1 and 7M (K = 8.00096 MHz, Table 2) and control data for waveform interpolation in order to synthesize musical tones. (607) is R
a musical tone generator (606) that generates musical tones using the waveform sample data and control data stored in the OM (606);
08) is a filter that removes sampling noise, (6
09) is an electroacoustic transducer.

Keyboard section (601), operation section (602), CPU (6
08), RAM (604), ROM (605) (6
06), the musical tone generator (607) is connected to a data bus, an address bus, and a control line. This method of coupling data buses, address buses, and control lines is itself a well-known configuration method mainly for minicomputers and microcomputers.

Eight to 16 data buses are used, and data is transmitted and received on these path lines not in one direction but in multiple directions in a time-division manner. If there are multiple address buses, 16 trees are prepared, and normally the CPU (608) outputs the address code, and other parts receive and receive the address code. As control lines, a memory request line (MREO), an I10 request line (LOftQ), a read line (RD), a write line (WR), etc. are normally used.

MREQ indicates reading and writing memory, l0RQ
indicates retrieving the contents of the input/output device (Ilo), RD indicates the timing to read data from the memory or Ilo, and WEL indicates the timing to write data to the memory or Ilo. Zilog's microprocessor Z8 uses such a control line.
0 is given.

Next, the operation of the electronic musical instrument shown in FIG. 6 will be described.

The keyboard section (601) is configured to divide a plurality of key switches into a plurality of groups and send the on/off states of the key switches in the groups to the data bus all at once. For example, in the case of a 61-key keyboard, it is divided into 10 groups of 6 keys (half an octave) and 11 groups of 1 key, and one address code is assigned to each group. An address code indicating one of the above groups arrives on the address line, and a signal I
When OR, Q and signal RD are applied, the keyboard section (601)
decodes the address code and outputs 6-bit or 1-bit data indicating on/off of the key switch in the corresponding group to the data bus. These are the decoder,
It can be configured using a bus driver and some gate circuits. Of the operation section (602), the tablet switch can have the same configuration as the keyboard section (601).

The CPU (608) reads the instruction code from the address of the ROM (605) that corresponds to the code of the internal program counter), decodes it, performs arithmetic operations, logical operations, reads and stores data, and executes the program counter. Instruction jump ζ by changing the contents of ζ The procedures for these operations are written in the ROM (605). First, the CPU (608) is the ROM (60
5) A command for importing data from the keyboard section (601) is read 9, and a code indicating on/off of the duplicate keys of the keyboard section (601) is fetched for each group. Then, the pressed key code is assigned to a finite channel of the musical tone generating section (607), and musical tone generation data corresponding to the assigned key code is sent out.

Next, the CPU (608) sequentially stores a group of instructions for importing data from the operation unit (602) into the ROM (605).
The address code and control signals l0RQ and R corresponding to the operation section (602) are read from
D, the data bus outputs a code representing the state of the switch of the operation unit (602), and the CPU (608
). Based on the data read into the CPU (608), tone selection and predetermined effect control data are generated, and tone selection data and data are stored in the ROM (606).
Effect control data is sent to the musical tone generator (607).

Note that the key code of the pressed key is sent to the tone generator (607).
The method of allocating to a finite number of channels itself is known as the generator assigner function.

Musical sound generation section (607) generates musical sound synthesis data based on the musical sound generation data supplied from the CPU (6o8).
Predetermined waveform sample data and control data are input from the ROM (606) and subjected to waveform interpolation processing to generate a musical sound waveform.
609) to generate musical tones. Note that the musical tone generator (6
The internal processing of 07) is as described above.

Figure 7 shows the musical tone generator (607) from the CPU (60B).
110 port addresses are supplied to the address bus, and tone generation data, effect control data, etc. are supplied to the data bus.

Then, the control signal l0RQtoi changes from a logic low level (hereinafter abbreviated as "O") to a logic high level (hereinafter abbreviated as "1").
The contents of the data bus are latched to the channel specified by the 110 port address at the timing when the data bus becomes low (abbreviated as "°").

Next, various types of data supplied to the musical tone generating section (607) will be explained.

8P, Table 3 shows the I10 boat address and the contents of various data. Ilo, N-) addresses are expressed in hexadecimal. I10 boat address (00) ta to (0
7) The data corresponding to to is musical tone generation data that can be generated for 8 channels, that is, for 8 tones.

The I10 port address (08) ta is sustain data that specifies the attenuation characteristic of the envelope signal explained in FIG. I10 boat address (09)t.

is the ``th'' whose envelope characteristic is valid for piano-shaped i.
8 Table damper data specifies the attenuation characteristics of the envelope signal, similar to the sustain data. (1) 10 boat address (OA) s6 is beat data that specifies the frequency shift when two musical tones are generated.

The I/, 0 port address (OB) 16 is effect control data, which is composed of vibrato on/off signals, glide on/off signals, and the like.

Table 4 shows the composition of the musical tone generation data. Bit positions DQ to D3 are note clock designation data that designates the scale frequency. Bit positions D4 to D6 are waveform sample number designation data that designates the generated sound range. Bit position D
Reference numeral 7 indicates a key on/off signal accompanying the on/off operation of the key switch, which is "0" when off and "°1" when on.

Table 5 shows the code contents of the waveform sample number designation data 5D6-8D2 and the number of samples in one period of the waveform designated by the code. The waveform sample number specification data SD is (ooo
), to (,111), the number of waveform samples can be specified in eight types.In this example, it is 512.
Samples up to 4 samples are specified in Table 5 and Table 6.

Table 6 shows the relationship between the contents of the chords represented by the note clock designation data NDO to ND8 and the designated scale designated by the chords.

Table 7 shows the composition of the effect control data. Bit position DQ is the vibrato on/off signal VIB, and the bit position DQ is the vibrato on/off signal VIB.
02) When the vibrato on/off switch in
0#, becomes 51' when on.

Bit position D1 is delay vibrato on/off signal D
VIB is a delay vibrato effect control signal, and when the delay vibrato on/off switch in the operation section (602) is off, 1011 is on.

The bit position D2 is the glide on/off signal GL, which is 0 when the glide switch in the operation section (602) is off and 1 when it is on.

Bit position taD8 is organ type/piano type designation signal OP
S specifies the envelope characteristics, and is 10' for an organ type and 11) for a piano type.

D4 is a damper on/off signal DMP, which is valid only when the envelope characteristic is a piano type, and becomes tOw when the damper is off and wI'' when it is on.

Bit position D5 is the generator assigner operation mode signal GAM, which is a designated signal when using 2 channels of musical tone generation with 1 key.If the GAM signal is wO'', 1 key is used with 1 tone (8 tone generation). In the case of ``1'', 1 key uses 2 channels (4 tones are generated).

FIG. 8 is a configuration diagram of the musical tone generating section (607). In FIG. 8, (801) is a main oscillator, (802) is a sequencer that controls the operation contents of the musical tone generator (607), and (802) is a sequencer that controls the operation contents of the musical tone generator (607).
0B) is an input register section that latches various data supplied from the CPU (608), (804) is a timer, (805) is a comparison register section, and (806) generates frequency data corresponding to the frequency to be generated. (807) is a waveform data processor (hereinafter abbreviated as WDP) that performs the waveform interpolation process of equation (2) explained above; - (808) is a musical tone synthesis data ROM ( (606) is a data read processor (hereinafter abbreviated as DRP) that reads waveform sample data, control data, etc. from (806), a pulse forming unit (809) that generates a pulse signal with a predetermined pulse width;
(810) is WDP (807), DRP (808)
), etc., a calculation request flag generation unit that requests calculation processing, etc.
(811) is a digital/analog converter (hereinafter abbreviated as DAC) that converts a digital signal into an analog signal, (
812) is an analog buffer memory section which is composed of two analog switches and one capacitor per channel and holds analog signals, and (818) is an integrator.

In the above configuration, (804) (805) (806
) (slo) constitutes a note clock generating section that determines the tone scale, and based on its output signal, a data reading section DRP (808) reads data from the musical tone synthesis data R, OM (606).

In addition, the manual register section (SOa), comparison register section (
805), F'l)P (806), WDP (80
7) , DB, P (808) and the calculation request flag generating section (810) have a procedure determined by the sequencer (802).

When musical tone generation data is supplied from the CPU (60B) to a predetermined channel, for example, channel 1, the sequencer (
FDP (806), WDP (
807), musical tone generation data is supplied to the DRP (808). Then, in DRP (808), waveform sample data and control data are read from musical tone synthesis data R, OM (606). Then, let /(X,,n) shown in equation (2) be the data WDI,' (Xi-h
, n) to the WDP (807) as data WDI. Additionally, based on the read control data (
2) The numerator term of the interpolation coefficient shown in the formula is supplied to the WDP (807) as data MLP. Also, when the final waveform data is reached, the WEF signal instructing the final waveform data is sent to the WDP.
(807).

WDP (807) uses the data WDI, WDI, and MLP supplied from DRP (808) to calculate (2
] The waveform calculation process is performed and the result is supplied to the DAC (811). Then, in the DAC (811), WDP (8
The digital signal supplied from 07) is converted into an analog signal and supplied as an analog signal to the analog buffer memory section (812), where the capacitor charge corresponding to channel 1 is stored.

On the other hand, in li'DP ('806), frequency data is generated based on the musical tone generation data supplied from the input register section (808), and is supplied to the register corresponding to channel no. 11 of the comparison register section (805). be done. Then, the data supplied to the comparison register (405) and the time data supplied from the timer (804) are compared, and if a match is detected, the matching pulse is read out and the pulse forming unit (809) and the calculation request flag are Generating part (8
10).

Then, a readout signal with a predetermined pulse width is generated in the readout pulse forming section (809) and supplied to the analog buffer memory section (812). The charge stored in the capacitor corresponding to channel 1 in the analog buffer memory section (812) is transferred to the integrator (
818).

The calculation request flag generating section (81G) generates and holds a calculation request flag for determining the next waveform sample, that is, the virtual sample point/(X,, m, .□). Thereafter, when the processing timing reaches channel 1 again, since the calculation request flag has been generated, waveform interpolation processing is performed in the same manner as described above, and charges are stored in the capacitor in the analog buffer memory section (812). Thereafter, waveform interpolation processing is performed in response to the calculation request flag, and a musical tone waveform is generated.

Note that the charge stored in the capacitor is / (Xi, m
, It-L) and the waveform sample value obtained this time / (Xl,
m, n). Then, the integrator (8
18) The waveform sample value obtained this time / (Xl,
m, n) will be restored. The operations around the analog buffer memory section (812) and the integrator (818) are described in Japanese Patent Application No. 57-1264181 "Waveform Reading Apparatus".

FIG. 9 is a block diagram of a specific example of the sequencer (802). In FIG. A hexadecimal counter that determines the operation sequence for each channel, (908) a counter that generates the channel code that is currently being processed, (904) a ROM that stores the operation procedure, and (905) a decoder. . FIG. 10 shows a timing chart of the sequencer (802).

A master clock (MCK) signal is supplied from the main oscillator (801) to the two-phase lock generation section (901). In the two-phase lock generation unit (901), two-phase lock generation unit (901) has two phases as shown in FIG.
Generate mutual lock numbers φ1 and φ2. Signal φ1 is 11
It is supplied to the advance counter (902) and counter (908).

The 11-decimal counter (902) has a 4-bit configuration, and count-up processing is performed at the timing when the signal φ1 or Iol changes to 111, and the output signal becomes (1111).
)2, and then when you count up (010
1) Set to 2. As a result, the decimal counter (9
The output signal of 02) is in state 11, i.e. (0101)
2 to (1111)2. This is used as a command step signal.

The counter (908) has a 3-bit configuration.
The output signal of the counter (902) is changed from (1111)2 to (
0101) Count-up processing is performed every time the value changes to 2. As a result, the output signal of the counter (90B) becomes 8 states, that is, (000)2 to (111)2. Use this as the channel code.

The ROM (904) reads out the instruction code based on the instruction step signal supplied from the hexadecimal counter (902) and supplies it to the decoder (905). Decoder (90
5) decodes the instruction code supplied from the ROM (904) and supplies processing control signals to each section.

As a result, the calculation time for one channel is 2.75 μs! Each arithmetic processing is performed in instruction steps of l) and n. Then, the calculated timing jig is returned every 22 μs.

FIG. 11 shows a configuration diagram of a specific example of the analog buffer memory section (812). In the figure, (1101) is the input terminal, (
1102) is an output end, (110g) to (1108) are analog switches, and C1 to C8 are capacitors.

Analog switch (1108) (1105) (11
Signals AWI to AW supplied to the gate input of 07)
8 is supplied by WDP (807). Also, analog switches (1104) (1106) (1108
) are supplied from the read pulse forming section (809).

1) The analog signal converted by AC (811) is applied to the input terminal (1101) and is applied to the analog switch (110B).
(1105) (1107). If the data corresponds to channel 1, only the analog switch (1108) is turned on, and the input terminal (1101) is turned on.
A charge corresponding to analog No. 48 applied to the capacitor C1 is stored in the capacitor C1.

Then, the read pulse Alt corresponding to channel 1,
1 is supplied from the read pulse generator (809) to the gate input of the analog switch (1104), the charge stored in the capacitor C1 is supplied to the integrator (813) via the output terminal (1102). .

Anna Of Sui 7 Chi (1108) (1105) (
1107) is synchronized with the operation timing of the WDP (807), so multiple devices cannot be turned on at the same time. Analog switch (11i34) (1106) (110
8) is designed to turn on in synchronization with the musical scale frequency, so a plurality of them can be turned on at the same time.

FIG. 12 shows the internal operation timing chart of the musical tone generator (607). FIG. 12 shows the timing for four channels. Explanation of abbreviations in the figure CRF is a calculation request signal for each channel.

Then, the request start point is the comparison register. It is synchronized with the coincidence signal supplied from the unit (805).

In other words, CLC occurs every 59.74 μs in the C scale, without synchronizing with the scale frequency.
Indicates waveform calculation timing.

DAC indicates the timing of storing charge in the capacitor in the analog buffer memory (812) via the DAC (811). OTC indicates the timing to store the charge in the capacitor in the analog buffer memory (812). (818), and similarly to CRF, it occurs in synchronization with the scale frequency.

The time chart of channel 1 will be explained.

The calculation timing corresponding to channel 1 is the sequencer (
802), and as shown in the figure, calculation timing is generated every 22 μs.

(2) Signal C) LF 1 occurs in the middle of channel code 1. Waveform interpolation processing is not performed at the timing when 0 occurs.

■...The signal OTC1 is generated at the same time as the signal CRFI is generated.
is generated, and the electric charge of the capacitor C1 in the analog filter memory (812) is supplied to the integrator (813).

The pulse width of the signal OTC is about 2 μs.

■°...When the channel code becomes 1 again, reading processing of waveform sandal data, waveform interpolation processing, frequency data updating processing, etc. are performed.

(2) When the arithmetic processing of the channel 1 is completed, the signal DAC1 is generated, and the charge is stored in the capacitor C1 via the DAC (811).

■...When the arithmetic processing of channel 1 is completed, the signal CR
Reset the FI and cancel the calculation request.

(2) Similar to (2) above, at the timing when the 'signal CRFI is generated again, the charge stored in the capacitor C1 at the timing (2) is supplied to the integrator (818).

From then on, as described above, each time the signal CRF is generated, 1
The temporary phase waveform sample value calculation process is performed twice, and the signal CR
The waveform calculation result is supplied to the integrator (818) in synchronization with the generation timing of F, that is, with the scale synchronization.

The relationship between the calculation cycle and the scale period is as long as the calculation timing of the same channel can be performed twice within the minimum scale period and the calculation result can be stored in the capacitor in the analog backup memory section (812). It is sufficient to provide calculation timing corresponding to 10 channels within a period.

Explanation of how to generate a scale period Figure 18 shows how the comparison register section (
The timer (804), which indicates the transition of frequency data supplied to
Count up sequentially from (8FF)+a,
(8FP) sa becomes (ooo)ta again, and (0
00)+a to (8F'F)16 is the main oscillator (801)
The signal is returned based on the signal MCK supplied from the . That is, the repeating cycle TR of the timer (804) is expressed by the following formula.

= 127.98 μs The output data transition state of the timer (804) is described as timer output data in FIG.

The scale period is generated by comparing the output signal of the timer (804) with the frequency data supplied from Fl)P (806), and if a match is detected, a matching pulse is sent from the comparison register section (805). . The generation cycle of the matching pulse becomes the scale cycle of the scale to be sounded.

As shown in FIG. 13, the note clock signal can be generated by updating the frequency data.

In other words, the arithmetic processing shown in the formula below is performed using FDP (80
6).

NFD=MOD (OFD 10 PD, TDmax)...
(4) NFD is new frequency data.

OFD is frequency data before update.

FD is scale data that is determined by the generated scale.

TDmax C is the number of output states of the timer (804).

In this embodiment, TDmax is 210, that is, 1024.

Table 8 shows scale data PD corresponding to the 12-tone scale.

FIG. 14 is a configuration diagram of a specific example of FD, P (806). In FIG. 14, (1401) is a cent scale data generation unit (hereinafter abbreviated as CPD generation unit) that generates scale data (CPD) expressed in cent scale, and is composed of a ROM that stores cent scale data. Shioshioshi,
Note clock designation data (ND), waveform sample number designation data (SD), and organ type/piano type designation signal (O
CPD based on F2) is selectively generated. (1402) is a beat data gate that selects beat data, (140B) is a vibrato signal generator that generates a vibrato signal, (1404) is a Ug number representation of 1
It's a 0-decimal number.

a glide signal generation unit that generates a ride signal (1405
) is an exponential converter that converts a frequency value expressed in a cent scale into frequency data that is directly proportional to the frequency, (1406)
is the calculation unit, (1407) is the latch (assumed to be AL), (1
40B) is a latch (designated as BL), (1409) is an adder (designated as FA), -(1410) is a buffer, (1
411) is a gate. (1412) (1418)
(1414) is the pass line, (1412) is the FA bus (1418), and the FB bus (1414) is the F'C bus.

In addition, beat data CBD, vibrato data CVD,
Glide data COD is also expressed in cents scale.

Structure of various data Cent pitch data (CPD) It is composed of 11 bits, with the upper 4 bits representing 12-tone equal temperament, and the lower 7 bits representing each point of the chromatic scale divided into 128 equal parts.

Beat data (CBD), vibrato data (C'V
Dχ glide data (CQD) Each bit has an 8-bit configuration, uses two's complement representation, and has a resolution that divides the chromatic scale into 128 equal parts. It also represents positive and negative beat components, vibrato components, and glide components.

Explanation of the vibrato signal generation section (1408) Fig. 22 shows a configuration diagram of a specific example of the vibrato signal generation section (1408) In Fig. 0, (2201) is the vibrato data CV
- Fully memorized thio<hifu' 5-to ROM, ,(
2202) is a vibrato address register (220) that stores address data for reading stored vibrato data from the vibrato ROM (2201);
8) is the shifter used for the delay vibrato effect, (
2204) register (2208) by the signal RD'CVD.
) to supply the output signal (vibrato data CVD) to the FB bus, (2205) is the input register section (8
Signal KD, signal VIB, signal MIB supplied from the sequencer (80g) and signal C supplied from the sequencer (80g)
A condition setting section (2206) is a gate that sets the operating conditions of the vibrato signal generation section (140g) based on HC;
(2207) is a gate, and (220 illusion) is an ADLD gate.

The address data stored in the register (2202) is 14.
It has a bit configuration, and the lower 11 pits are vibrators)
The address data of the ROM (2201) is used, and the upper 8 bits are used as shift data of the shifter (2208).

The shifter (2208) controls the amplitude of the vibrato data pcVD supplied from the vibrato ROM (2201) based on shift data. Shift data vSFD shifter (2208) output f-08FD
The relationship between t and tD is as follows.

V 8 F D = (000)2...OS F D
= (00)ta, VSFD = (001)2.08
FD=(CVD/64), V8FD=(010)2-O
iFD=(CVD/82),..., V8F'D
=(110)2-08F'D=(CVD/2), VSF
D=(111)2.-OS'FD= (CVD) The condition setting section (2205) sets the following operating conditions.

Vibrato off This is the case when the vibrato on/off signal VIB is 10", and the output of the gate (2206) is forced to always be (00) 1.
Let it be a. Then, the shift data of the shifter (220g) will always be (000)2. As a result, shifter (2
The output data of 208) is (001,.) In other words, the vibrato data CVD is always (00)so.

Vibrato on Vibrato on/off signal VIB or signal DVI with 111
When B is '0'', the vibrato is on.Register,
The address data stored in the star (2202) is supplied to the gate (2207) and shifter (2208) via the data (2206). Note that the upper 8 bits of address data, that is, shift data, are forced (111).
.

shall be. Then, the output (vibrato data CVD) of the vibrato FtOM (2201) will be supplied as is to the input of the vibrato FtOM (2204).

When the delay vibrato vibrato on/off signal VIB and the delay upper plate on/off signal DVIB are wll, a delay vibrato state is entered. 8 channel key on/off signal K
When any one key-on/off signal KD turns on from all D's off, the address data is changed to (00
(2206) so as to set it to 0), a. Then, the shifter (2208) controls the amplitude of the vibrato data CVD (0°CVD/64, CVD/82,
CVD/16, CVD/8, CVD/4.

CVD/2, CVD) is performed. Then, when the shift data becomes (111)2, the shift data is forcibly set to (111)2 as in the vibrator-on state.

The address data stored in the register (2202) is the signal 11J supplied from the sequencer (802).
) VAD via the gate (2207) to the FBC bus.

The address data added in the arithmetic unit (1406) is added at the rising edge of the signal φ2 by the signal WRVAD.
It is stored in the register (2202) from the FC bus.

Also, signal RJ) by CVD, vibrar) ROM
The vibrato data CVD stored in (2201) is passed through a shifter (220B) and a gate (2204) to F.
BC bus is provided.

Description of glide signal generation section (1404) The glide signal generation section (1404) also includes a vibrato signal generation section (140B).
) Glide RO stores glide data in the same way as
The glide controller is composed of a glide register M, a glide register for reading predetermined glide data from the ROM, a wide address register, and a controller for controlling generation.

There are two operating modes: glide-off and glide-on.
There are different types.

glide off When the signal GL is lOw, the glide-off state occurs.

Glide data CGD is always (00)to.

glide on If the signal is GL or wl, the glide-on state is achieved.

This is similar to the well-known glide effect. That is, when the key on/off signals KD of all eight channels are turned off and the key on/off signal KD of any one channel is turned on, glide data CGD is read from the glide ROM. Then, after a predetermined time has elapsed, the glide data CGD becomes (oo)ta again.

Description of Index Converter (1405) The index converter (1405) incorporates a conversion I (OM) that stores conversion data for converting cent scale data into frequency data ED that is directly proportional to frequency.

In this embodiment, the EXP-ROM uses the upper 4 bits (bit positions 7 to 10) of the frequency data CF'D on the cent scale as address data, and the
A ΔEXP ROM that uses bits as address data is available.

Then, there is a register in which the frequency data CFD on the cent scale subjected to addition processing in the arithmetic unit (1406) is stored by the signal WREXP, and the above-mentioned EXP ROM, Δ, which uses the data stored in the register as address data.
It consists of an EXP-ROM and a gate that supplies the data stored in the EXP-ROM and ΔEXP-ROM to the FA bus and FB bus by signals RDEXP and RDΔEXP, respectively.

EXP-ROM contains frequency data 1 at 100 cent intervals.
The ΔEXP-ROM stores 6 words and stores differential frequency data of 15×128=1920 points corresponding to 0.78 cent intervals by dividing 100 cents into 27, that is, 128.

FIG. 15 is a processing flowchart showing the data processing procedure of the EDP (806). The calculation processing shown below is performed to calculate new frequency data NF'D from the old frequency data OFD, and the new frequency data NF'D is stored in the comparison register section (805). supplying.

■、CPD=CPD+CVD ■、CPI)2CPD+CQD ■、CPD=CPD+CBD ■、PD ='EXP(CPD)+△EXP(CPD)
(2) NED=OFD+PD Next, the operation shown in FIG. 14 will be explained. FDP(S
Oa) performs arithmetic processing based on processing command signals sent from the sequencer (802).

Table 9 shows the flow of the arithmetic processing sequence. By sequentially executing the instruction steps shown in Table 9, the process explained in FIG. 15 is realized and new frequency data NFD is calculated.

Explanations of the symbols listed in Table 9 are as follows.

AL latches the data supplied to the FA bus at the falling edge of signal -2.

BL latches the data supplied to the FB bus at the falling edge of signal -2.

CR, AL are instructions for clearing the two ALs at °1' of the signal φ2.

Al)Di is an instruction to add "1" to F A (1409)'s carry manpower.

TCA is an instruction to supply the result of arithmetic processing in FA (1409) to the FA bus.

几D(:'pD is an instruction to supply the cent pitch data CPD generated by the CPD generation unit (1401) to the FA bus.

RD CB D is an instruction to open the beat data gate (1402) and supply FB Babas beat data CBD.

FLDCVDld, healer) Gin generation part (14
08) -c'ia generate vibrato data CVD
B. Command to supply Babasu.

R, DCGD is an instruction to supply glide data COD generated by the glide signal generation unit (1404) to the FB bus.

RDEXP is E converted in the exponent converter (1405)
Instruction to supply XP(, (':' P D ) to FA Babas.

aD and hEXP are instructions for supplying ΔE (CPD) converted in the exponent converter (1405) to the FB bus.

1LDFD is an instruction to read the old frequency data OFD from the comparison register section (805) and supply it to the FB bus.

几DVAD is an instruction to supply the contents of the vibrato counter in the vibrato signal generating section (1408) to the FB bus.

17D GAD is a command to supply the contents of the glide counter in the glide signal generation section (1404) to the FB bus.

W-VAD is an instruction to store the result of calculation by F person (1409) into the vibrato counter in the vibrato signal generating section (1408) at the rising edge of signal φ2.

W GAD is an instruction to write the result calculated in F A (1409) to the glide counter in the glide signal generator (1404) at the rising edge of the signal≠2.

WREXP is an instruction to write the result calculated by FA (1409) to the exponent converter ("1405) at the rising edge of signal φ2.

WRFD is an instruction to write the result of the operation in F'A (1409) into the comparison register section (805) at the rising edge of signal φ2.

Note that the state 11 occurring in the decimal counter (902) in the sequencer (802) shown in FIG.
This corresponds to instruction steps 1 to 11 shown in the table.

Explanation of operation content by signal f GAM (generator assigner operation mode signal) When GAM=“0”, one key, one channel operation is performed. In this case, the beat data CBD is forced (o 0) 1
It will be in state 6. In other words, no beat effect is added.

In the case of signal GAM-“1”, a 1-key 2-channel assignment operation is performed. In this case, the 1st channel and the 5th channel, the 2nd channel and the 6th channel, the 8th channel and the 7th channel, and the 4th channel and the 8th channel are assumed to be the same tone data. Then, the beat data CBD used for channels 1 to 4 is forcibly set to (00)16, and the beat data CHD used for channels 5 to 8 is determined to be the beat data supplied from the CPU (608). Yes, it is possible to generate a beat effect.

As described above, since multiple comparators are used and the comparison data is calculated and determined, there is no need to install multiple high-speed frequency dividers (as many as the number of channels) in parallel, and the circuit scale is reduced. Can be made smaller.

Furthermore, using signal GAM, channels 1 to 4 are set to beat data CBD2(00)s6, and beat data CBD for channels 5 to 8 is set to beat data CBD supplied from the CPU (608). , channel 2 and channel 6, channel 3 and channel 7, channel 4
By using the same tone generation data for channel 8 and channel 8, a beat effect can be easily realized without adding complicated peripheral circuits.

Furthermore, channel-independent glide effects can be added by simply preparing glide address counters for each channel in the glide signal generating section (1404).

FIG. 16 is a block diagram showing a specific example of the comparison register section (805). (1601) (1602) (
1608) is the frequency data register F'DRI~FDR
8 is available for 8 channels. (1604)
(1605) (1606) are gates QTI to GT8
We have 8 channels available. (1607) (16
08) (1609) is a comparator, (1610) (1611
) is a decoder''; (1612) is an AND gate.

Output signals TMO-TM9 of the timer (804) are commonly supplied to comparators (1607)-(1609).

The new station wave number data NED calculated by the FDP (806) is supplied from the FC bus to the inputs of registers F'1) LL1 to F'DR8, and both the signal WfLFD and the signal CLRF (calculation request flag signal) are 1'', new station wave number data NFD is written into a predetermined register FDR. In other words, data is loaded only when a calculation request is occurring.

1. When the FDP (806) requires the old frequency data OFD, the signal RDFD is supplied to the decoder (1610), which opens predetermined gates of GTI to GT8 and supplies the old frequency data OFD to the FB bus.

The new frequency data NFD in the data processing means explained in FIG.
Written to any of DRI to FDR8, then l
(According to , DI~R, D8) When read out via GTI~GT8, the new station wave number data NFD is supplied to the F'B bus as the old frequency data OFD.

On the other hand, the comparators (1607) to (1609) use the signals TMO to TM9 from the timer (804) and the register F'
I) Frequency data F' stored in R1 to FDR8
When a match is detected, a match signal N is made.
Output as CI~NCR.

FIG. 17 is a block diagram showing a specific example of the calculation request flag generation unit (810).
) is a NAND gate, (1711) is a decoder, (17
12) to (1719) are R87 lip-flops (R8F
'F'), (1720) is selector, (1721) is D
type flip-flop (DFF).

Match signal NC supplied from comparison register section (805)
I~NC8 as NAND gates (1701)~(1708
) performs a logical operation with the signal MCK supplied from the main oscillator (801), and sends the result to R8F
' Each person from (1712) to (1719) supplies Kayo. When the match signal becomes "11" (match detected by the comparator),
“0” is supplied to the input S of R8FF, and the output Q is “1”
Tonanashi, the calculation request signal CRF explained in FIG. 12 is 11.
It becomes 1.

A selector (1720) selects the signal cuF corresponding to the calculation timing and supplies it to the input of DFLi' (1721).

When the signal WRCLF in the control data supplied from the sequencer (802) becomes "1°," the signal φ
At the falling edge of 2, the selector (1
720) to latch the selected calculation request signal CRF,
Calculation request flag signal CLE? , ,F.

If the calculation request has stopped, the flag signal CLRF is 11°.
, otherwise the flag signal CLRF becomes @oI h.

The timing at which the signal WRCL_F is generated occurs at instruction step 1. That is, the presence or absence of a calculation request is determined at the beginning of the calculation process.

Thereafter, at the timing of instruction step 11, a reset (clear) signal CRCLF, which is one of the control data supplied from the sequencer (802), is supplied. Then, when the flag signal CLRF is 11', N
The AND gate (1709) outputs the output signal "0" and supplies "0" to the predetermined input holes of the RUFFs (1712) to (1718) selected by the decoder (1711) with the channel code CHC to reset R8FF. (Output Q2 is "0"). This operation corresponds to the timing (2) of resetting the calculation request signal CRF' explained in FIG.

Detailed Description of Data Read Processor DRP (808) Without further ado, the data format of musical tone synthesis data FtOM (606) (hereinafter referred to as data bar (DBK)) will be explained.

FIG. 18 is a data configuration diagram of D B K (606).

The start address indicating the start position of the subsequent combined data is stored in the area from address (0000) 16 to 128 words.The combined data consists of control data and waveform data. The control data consists of data specifying the number of repetitions between waveforms and a final waveform flag.

The repetition number designation data will be explained.

The following is a method to simplify the output.

(1) '(In Equation 21, the increment value of the Nm-n term was 1, but the increment value of the numerator of the interpolation coefficient is set to α.

(3) Fix the MNα term to 216.

As a result, the interpolation coefficient becomes (Nm ten n) α/216, and the 1/216th term only needs to be shifted to the right, and M
There is no need to find the N term, and interpolation coefficients can be easily calculated. Table 10 shows the relationship between the comb return designation data, the increment value α, the number of samples in one cycle of the waveform, and the number of comb returns.

Note that if the comb return number designation data is (F)la, it is used as a final waveform flag (signal WEF) indicating the final waveform.

The control data area of the DDK (606) is fixed at 128 words regardless of the number of waveforms. In addition, control data 1
The word is composed of 16 bits, and the repeat specification data is divided into four groups of 4 bits each as shown below.

Pit position O~3...c, c"; D sound bit position 4~
7...I, 1S, F sound bit position 8-11...F'
, G, G# sound bit position 12-15...A, A, B
By doing this, the control data can be set differently depending on the scale, and even if the same waveform data within one octave is used, the rise time of the musical tone and the change time of the waveform shape can be kept constant. It becomes possible to do so. The waveform data is PCM data consisting of 16 bits per word.

Figure 19 is a configuration diagram showing a specific example of DRP (80g).
(DBK) (606) A DBK address register that stores address data for reading predetermined composite data from (606);
1902) is a musical tone synthesis data ROM (DBK) (60
The DBK human Kabaka buffer 1908) that imports the synthetic data from 6) into the DRP (sos) is the DBK (6)
Reference start address gate that outputs address data for reading the start address stored in 06), (1
904) is the waveform data memory that stores the value in 7 (X,, n) and the waveform data memory that stores the value in the pull, (1905) is /(
Waveform data memory (1906) stores the waveform sample value corresponding to the numerator of the interpolation coefficient (Nm+n); (1906) is the coefficient data memory (1906) that stores the waveform sample value corresponding to
07) is the start address register, (1908) is the increment generation unit that generates the increment value α of the (Nm+n) α term of the interpolation coefficient, and (1909) is the waveform sample number memory that stores the sample number n within one waveform period. , (1910) id
Waveform number memory storing waveform number/<i (191
1) is an offset data gate, (1912) is an accumulation register (ACC), (1918) is an arithmetic unit consisting of a full 7#, a latch, a carry flag register, etc., (1914) is an arithmetic unit (1918) ), the DA bus (1915) supplies data to the latch AL in the arithmetic unit (1
(918) is a DJ3 bus that supplies data to the latch BL in
This is a DBK bus that supplies the output of the BK person Kabaka buffer 902) to the waveform data memory I (1904) and the like.

Next, the configuration of each part will be explained. Waveform Data Memo, Sl (1904), Waveform Data Memory I (1905)
) are registers IIL (WDI) that temporarily store the waveform data read from the DBK (606) using signals WR, WD I, and WRWD It in the control data supplied from the 7-controller (802). ,
R (WDI), a 16-bit memory that stores waveform data for 8 channels) x 8 words memory M (W, DI), M (W
, J) 0 Normally, the memory is in a read state and supplies waveform data WDI, WDI of the channel based on the channel code CHC supplied from the sequencer (802) to the WDP (807). ing. - Then, by the signals VIFL and 'kM in the control data from the sequence (802), the memory is put into the write state, and the waveform data stored in the register name -R (WDI), R (WDI) is transferred to the channel. The code is omitted at a predetermined address in memory based on the code CHC.

The coefficient data memory (1906) is the calculation unit (1918)
A register R (M'D) temporarily stores the calculation result of fli (signal WRMD in the I image data) supplied from the sequencer (802), and a register R (M'D) that stores coefficient data for 8 channels. 8 word memory M (MD
) and the output-data of memory M (MD) as signal RDMD
Therefore, it is composed of gates that supply DB bus.

Normally, the memory is in a read state, and the coefficient data (M(MD)) of the address based on the channel code CHC supplied from the sequencer (802) is supplied to the above-mentioned gate and WDP (807). There is.

Then, in response to the signal WRRAM, the memory enters the write state, and the new coefficient data stored in the register 4 (MD) is written to a predetermined address in the memory based on the channel code Cl (C).

The start address register (1907) is the DBK (606
) The first address read from ) is sent to the sequencer (802) 7
5- Signal TDA in the control (goods) data (the same applies hereinafter)
Gate 1, which supplies the 9-person bus, and the signal W 几TA
D? There is a register R (TAD) that temporarily stores the read start address, and a register R (TAD) that temporarily stores the read address.
It consists of a gate 2 that supplies the first address stored in R (TAD) to the DB node.

The increment generation unit (1908) uses a register R (1'LEP) that temporarily stores the control data read from the DBK (606) using a signal WREP, and a note clock supplied from the input register unit (808). A selector selects predetermined repetition specification data from the control data stored in the register R (REP) based on the specification data ND, and a first selector selects the repetition number specification data selected by the selector.
A converter converts the data into the increment value α shown in Table 0, a detector detects the final waveform flag and outputs the final waveform flag WEF same 1"], and a signal RDBEP converts the output data of the converter (increment value It consists of a gate that supplies the value α) to the DA node.

The waveform sample number memory (1909) is stored in the calculation section (
1918) in which the calculation result (new waveform sample nano(n)) is temporarily stored in register R(
WSN) and waveform sample number/(nf
It consists of a memory M (WSN) for storing 16 bits x 8 words, and a gate that supplies the output data of the memory M (WSN) to a DB bus by a signal RDWSN.

Normally, the memo IJM (WSN) is in a read state and supplies the waveform sample number n of the channel based on the channel code CHC supplied from the sequencer (802) to the gate as described above.

And 1 signal WIIAM + memo 1 no M (WS
N) enters the write state and the register 几(WS N
) is written to a predetermined address in the memory based on the channel code.

The waveform number memory (1910) is connected to the calculation section (1918)
(Register R (WND) that temporarily stores the new waveform number using the signal WRWND, and a 16-bit x 8-word CD memo IJ M (WND) that stores the waveform number i for 8 channels. IJ M (WND
) Output, t7 A shifter section that performs a shift process (iX sample number) on data (waveform number) based on the waveform sample number designation data SD supplied from the input register section (808), and outputs a waveform number address WNA. Gate 1 supplies the output data of the memory to the DB bus in response to the signal RDWND, Gate 2 supplies the output data of the shifter section to the DB bus in response to the signal RDWNA, and generates sample number data corresponding to the waveform sample number designation data 8D. It consists of a pull number generator and a gate 3 which supplies the output data of the sample number generator to the I)B bus in response to the signal ItDNWs.

Normally, the memo IJM (WND) is in a read state and supplies the waveform number i of the channel based on the channel code CHC supplied from the seek/su (802) to the gate 1 and shifter section described above. .

And signal W) LRAM Ni! Tute, l MoIJM
(WNJ)) is in write state, register R, (W
The new waveform number i stored in ND) is written to a predetermined address in the memory based on the channel code.

The accumulation register (ACC) (1912) is the arithmetic unit (1
918) is temporarily stored in the register R (ACC) by the signal WRACC, and the data stored in the register R (ACC) is transferred to the DA by the signal RDACC.
It consists of a Babas supply gate.

FIG. 23 is a block diagram showing a specific example of the calculation section (1918). (2801) is a latch AL that stores the contents of the DA bus at the falling edge of the signal φ2, and the signal DC
Cleared by RAL. (2802) is a latch BL that stores the contents of the DJ3 bus at the falling edge of the signal φ2;
2808) is carry input (CI) and carry output (Co)
A 16-bit adder (FA) with 1. (1204
) is the carry output signal of FA (2808) as signal WRMD.
Carry flag register stored by (2805)
is a gate that supplies the output data of F'A (2808) to the DA bus by signal TCA, (2806) is a gate that supplies the output data of F'A (2808) to the DA bus;
The gate that supplies the output data of (2803) to the DC bus, (2807) is the gate that supplies the data (0000)s to the I) C bus.
The gate that supplies 6, (2808) is the input register part (
Key on/off signal KD supplied from 80B)
an on/off detection unit that inputs the signal B/DFLG and the channel code CHC, detects the timing at which the key signal changes from the off state to the on state independently for each channel, and outputs a detection signal, (2809) ~ (2818) is A
ND gate, (21314) (2815) (2816
) is an OR gate.

When the final waveform flag signal WEF and signal RDNWS supplied from the increment generator (1908) are both 111, the output signal of the AND gate (2809) becomes Wl", and the latch B L (2802) is reset. .When both the signal WEF and the signal WRMD are "11", the output signal of the AND gate (2812) becomes "1", and the data (0000) 16 from the gate (2807) is sent to the DC bus.
is supplied.

The offset data generated by the offset data gate (1911) is 256 in decimal notation and corresponds to the storage area for control data.

Like the F'DP (806), the DRP (808) also performs the following arithmetic processing based on the control signal supplied from the sequencer (802).

■ Read the start address TAD stored in DBK.

The musical tone generation data (NII, SD) supplied from the manual register section (808) is supplied to the DC bus by the signal RDRTA supplied from the sequencer (802). and the signal ND on the DC bus.

It is stored in the DBK address register (1901) by the SD6 signal WRDBK and supplied to the DDK (606).

The start address data "TAD" read from the DDK (606) is stored in the register R (TAD) of the start address register (1907) by the signal WRTAD.

■Reading process of data specifying number of returns.

The arithmetic unit (1918) performs addition processing (TAD+i) between the read head address data TAD and the waveform number i stored in the waveform number memory (1910), and stores the addition result in the DBK address register (1901).
DBK (6o6) Reads the return number specification data, register R (R, EP) of the increment generation unit (1908)
Store in.

■Waveform sample/(X, , n) reading processing.

Start address data TAD and offset data (256) stored in the start address register (1907).

The calculation unit (1918) performs addition processing (WAD1=TAD+256) with ACC (1912).
) is stored in R (Ace). Addition process of address 2 data WADI stored in ACC (1912) and waveform sample number n stored in waveform sample number memory (1910) (WAD 1 =WAD 1 +n)
is performed in the arithmetic unit (1918) and the addition result is added to the ACC (1918).
12). Data obtained by shifting address data WADI' and waveform number i stored in ACC (1912) based on waveform sample number designation data SD (i x number of samples; i = 0, 1, 2, etc.). -..., l-1)
Addition process with (WADF-WAf) 1'+i X?
7 full number) is performed in all arithmetic units (1918), and the addition result is sent to ACC (1912) and DBK address register (1
901) and from DBK (606)/(X,,
Read the waveform sample data corresponding to T1) and store it in the register t (WDI) in the waveform memory l (1904). - Read the waveform sample f (X+ +t, n).

ACC (1912) Storage 1. ．． 7) "L/S f -p WADI" waveform sample number specification data SD
The number of waveform samples specified in NW8 (in the waveform number memory (1910) = J raw) and (DMJN processing full
(WAD2-WAD1//+NWS) in the calculation section (191
B) and the addition result is stored in the DBK address register (19
01) DBK (606) Kara f (Xi
171 (1905) Store the waveform sample data corresponding to (l, n) in the internal o v sister R (WDII).

■Update processing of waveform sample number n.

Waveform number (n and sequencer (802); A
Addition processing with the signal DADDI supplied from ``(n =
n + 1) is performed by the arithmetic unit (1918) and stored in the waveform number register R (WSN) in the memory (1909). (2) Update processing of interpolation coefficient (Nm+n) α.

The interpolation coefficient ((Nm+n) a) stored in the coefficient data memory (1906) and the increment generation unit (1908)
The calculation unit (191
B) and save the addition result to the coefficient data memo IJ (19
06) Store the contents in this coefficient data register R (MD), and if the addition result overfollows, set the carry flag register CF in the calculation unit (1918) to 1.
Set to 11.

■Update processing of waveform number i.

The waveform number i stored in the waveform number memory (1910) and the carry flag register CF explained in the above
The arithmetic unit (191B) performs the addition process 'fl (i = i + CF') with the contents of the waveform number memory (19
10) Store in internal waveform number register R (WND).

■L/ Sysp IL(WND), R(W8D>, R(
Data transfer processing of various data stored in MD), R (WDI), ■, (WDI) to respective memory areas specified by channel code CtlC.

At the timing of command step 11, data transfer processing is performed based on the signal WRRAM supplied from the seek/su (fishing).
When the angle is 0°, no transfer processing is performed. This is because no new waveform samples are calculated.

The calculation sequence of DfLP (808) is shown in "11th wing".

By sequentially executing the command steps shown in Table 11, the processes described in sections (1) to (2) above are realized.

Note that the key on/off signal KD explained in Table 4 is 10
The first process that changes from `` to 〒 is an initial process that sets the conditions as described above.

The signal [A] instructing the initial processing is the on/off detection unit (280) in the calculation unit (1918) shown in FIG.
8) occurs.

■Waveform sample number n = (0) 1 (, setting 11th
At the timing of instruction step 7 shown in the table, the signal VIWS is
N is supplied to the calculation unit (1918). Then, A
The output signal of ND Gameday (2810) is "1",
Day) (2806) (2807) control human power 11″
is supplied. As a result, the DC bus has (0000)s
6 is supplied and the waveform sample memory (1909
) (0000) t6 is stored in register R, (WSN).

■Set waveform number i” (0) to.

At the timing of instruction step 10 shown in Table 11, signal WRWND is supplied to the calculation unit (1918). Then, the output signal of AND game day (2811) is “1”
“Tonashi, control of gate (QosX2ao7) - 1 in human power
“ is supplied to the DC bus. As a result, (0000)
t and e are supplied, and (0(jOO)16) is stored in the register R (WND) in the waveform number memory (1910).

By the processing of ■ and ■ above, the key on/off signal KD
Each time the waveform number i and the waveform sample number n change from off to on, the waveform number i and the waveform sample number n are initialized.

Also, the <return designation data read from the DDK (606) is (L”)sa, that is, the final waveform flag WEF
If so, set the conditions as described above.

■Numerator term of interpolation coefficient (Nm+n)α=(0)to setting.

At the timing of instruction step 9 shown in Table 11, the signal W
RMI) is the AND game (2) in the calculation section (1918).
812). Then, AND game day (
The output signal of the gate (2812) becomes @11, and the output signal of the gate (280
6) '1' is supplied to the control input of (2807). As a result, (o o o o ) ta is supplied to the DC bus, and register R (
(0000)to is stored in MD).

■Number of waveform samples NWS = (0) to setting.

At the timing of instruction step 7 shown in Table 11, the signal R
, DNW8 is the AND gate (2
809). Then, AND gate (2
The output signal of the latch BL (2
802) is cleared (0000)we. As a result, the address data of the DBK (606) for reading the waveform sample /(X, +, , n) becomes equal to the address data for reading the waveform sample f(X, , □).

By setting ■ and ■ above, when it comes to the final waveform data,
In effect, no waveform interpolation processing is performed, and the final waveform data is repeatedly used.

Explanation of the signals shown in Table 11 The signals mentioned above are provided by the sequencer (802).

flu) O8D DA the offset data (256)
'Supply the bus.

R, DACC is register 1t in ACC (1912)
An instruction to supply the data stored in (ACC) to the DA bus.

RD RE P is an instruction to supply the increment value α generated in the increment generation unit (1908) to the DA bus. RDWSN is the waveform sample number memory (1909)
A command to supply the waveform sample number n read from the memory M (WSN) in the DB bus.

RDWND is an instruction to supply the waveform number i read from the memo IJM (WND) in the waveform number memory (1910) to the f)B bus.

R, DWNA is an instruction to supply the waveform number address (WNA) generated in the shifter section in the waveform number memory (1910) to the DB bus.

RDTAD is an instruction to supply the start address stored in register I' (, (TAU)) in the start address register (1907) to the DB bus.

R'D N W S is waveform number memory (1910)
An instruction to supply the number of samples generated by the sample number generator in the DB bus.

)t, DMD is an instruction to supply the coefficient data read from the memory M (MD) in the coefficient data memory (1906) to the DB bus.

RDRTA is an instruction to supply musical tone generation data (ND, 5D) supplied from the input register section (8/113) to the 2DC bus.

WItDBK transfers data on l) C bus to register R (D 13 K) in DBK address register (1901).
) WIIACC stores data on the I) C bus in Ace (1
Instruction to store in register R (8CC) in 912).

WRWSN waveforms the data on the DC bus.
Register l(, (W
Instruction to store in SN).

W RM D is an instruction to store data on the DC bus in register R (MI) in the coefficient data memory (1906).

WILWND is the DCC path Q data in the waveform number memo IJ (1910) (1) L/Schiff, evening FL
Instruction to store in (wND).

T'DA is the start address register (1907
) is an instruction to supply the first address read from DBK to the D input bus.

TCA is an instruction to supply data on the DC bus to the DA bus.

DCRAL is the latch A L in the calculation unit (1918)
Command to clear (2801).

DkDDl is FA in the calculation unit (1918), (23o
An instruction to supply a carrier input signal, <+i) to s).

RDF'LG is a command to input a new key on/off signal KD to the on/off detection section (2808) in the calculation section (1918).

WE (SRAM is waveform data memory I (1904)
Register R (WD l ) inside, waveform data memory IF
Register R (WDI) in (1905), register I (, (MD) in coefficient data memory (1906), register R (WDI) in waveform sample number memory (1909)
S, N), the data stored in the register R (WND) in the waveform number memory (1910) are transferred to the respective memories M (WD-1), M (w'Da), M (MD), M (
WSN), ・Instruction to write to M(WND).

As mentioned above, the composite data (
By storing the start address of waveform data, control data), different waveform data can be selected simply by manipulating the data contents in the data memory, without complicating the circuit configuration, and different musical tones can be easily generated. be able to.

In addition, multiple sets of control data (< number of return specification data)
When preparing and synthesizing, predetermined control J data is selected and used, so it is not controlled by the scale (
The data can be set differently, and even if the same waveform data within one octave is used, the rise time of a musical tone and the change time of the waveform shape can be made constant.

Furthermore, since waveform data, control data, and the first address are stored in the same database, and various data are read in a time-sharing manner, the circuit configuration of the data memory (DDK) can be simplified, and the data memory and DRP (
interface processing with SO8) can be simplified.

Detailed Description of Waveform Data Processor WDP (807) FIG. 20 is a flowchart of the arithmetic processing of WDP (807). There are four types of arithmetic processing as the arithmetic processing of WDP (807).

■Perform waveform interpolation calculation to obtain virtual waveform sample value ■Virtual waveform sample value/(X,,rn,n),! :Multiply with the envelope ED to obtain the enveloped △ liquid type sample value/(X,...l''tQlr).

■Previously calculated envelope added waveform sample value △ old/ (XI, m, n, 4.r) and envelope added waveform sample value calculated this time new/ (Xi, m, n+Q+
r ) and calculate the difference waveform sample value Df.
(X, r), m, n, q.

demand.

■Update envelope data ED.

Next, the envelope data ED and the envelope adding method will be explained.

Envelope data ED consists of 20 bits. The upper 4 bits are EDU (Q), the lower 16 bits are E
Let it be DL (几).

How to update envelope data ED: New BD = Old ED
It is determined by performing an arithmetic process called +IED.

Incremental envelope data △ED is CPU (60B
) is used to supply the sustain data DSUS or damper data DDMP to the input register section (808). Sustain data and damper data are selected based on the organ-type envelope, piano-type envelope, and key-on/off signal.

The formula for calculating the envelope-added waveform sample value is shown below.

/(X・ )・・・・・・・・・・・・(5)+, m
, n q=Q , 1 , 2 ,..., Q-1 (Q=2')
r=0, 1, 2, -, R-1 (R=2") Envelope data HD is monotonically increased, that is, new ED = old E
By setting D+ΔED (constant) and executing equation (5), an exponential characteristic damping (falling) envelope can be added. Also, monotonically decreasing, i.e. new ED − old ED − ΔhD
<constant), it is possible to obtain attack envelope data of exponential characteristics. By performing such processing, the envelope data ED can be obtained only by calculation without generating an envelope with exponential characteristics.
generation can be realized with a simple configuration.

FIG. 21 is a configuration diagram showing a specific example of the WDP (807).
02) is the waveform data data) I, (2108) is the envelope increment generator (△ED generator) that generates the incremental value of the envelope data HD, and (2104) is the old Satsugata sample value △ f (X, , m, n, 1.r), and (2105) is the envelope data ED.
The envelope data memory section (ED memory section) (2106) for storing , is a multiplication section, (2107) is a thick section that performs the operation of 1/2q or 1/2"' shown in equation (5), and (2108) ) is an arithmetic unit consisting of a full adder, latch, carry flag register, etc. (2109
) is an output that stores the difference waveform sample value D/(X, r), m, n, q.

Buffer register (OBR), (2110) Analog switches (1108) to (1107) in U analog buffer memory section (812) (capacitors C, -C8
Turn on/on the Ruri-toge switch (Fig. 711) that stores charge in
A write pulse generator (2111) that controls off is a WA bus (2112) that supplies data to the launch AL in the calculation unit (2108) and a WB bus (2112) that supplies data to the latch BL in the calculation unit (2108). 2118) is a WC bus that supplies the results of the arithmetic processing performed by the arithmetic unit (2108) to each register.

Next, the configuration of each part will be explained. △ED generation part (
2108') is a selector for selecting either sustain data DSU8 or damper data DDMP as incremental data ΔED, a key on/off signal KD, and an organ type/piano type designation signal OPS which are supplied from the input register section (80B). and a controller that generates a selection signal from the damper on/off signal DMP, a signal KD, a signal OP8,
Signals DMP and bR'P! ' The final waveform flag signal W supplied from the increment generator (1908) in (808)
It is composed of a virtual key signal generator that generates a virtual key on/off signal from BF and outputs a virtual key signal EADG.Table 12 shows the selection contents of the incremental data △ED and the virtual key signal E/! I) Shows the state of occurrence of G.

When the signal OPS shown in Table 7 is 101, that is, organ type designation, the virtual key signal EADG is key-on/
The off signal K D (7) is equal to the ("1") and off ("0") state.

When the signal OPS is "1", that is, the piano is specified, the virtual key signal EADG is in the downward state.

(a) When the signal WWF is 10'' (a) When the signal DMP (danbao//off signal shown in Table 7) is 10'', the virtual key signal EA-DG is in the 1-on-1 state.

(b) When signal DMP is °1', virtual key signal EAD
Q is equal to the on/off state of the key on/off signal KD.

(2) When the signal WEF is "1" The virtual key signal EADG is in the off state regardless of the states of the signal DMP and the key on/off signal KD.

Explanation of the function of the virtual key signal EAD G When the signal WEF is ``1'' and is used repeatedly without the final waveform data to generate a sustained musical tone, if an organ type is specified, the musical tone characteristics are equal to the organ type musical tone characteristics. No problems will occur.

When specifying a piano type, the musical tone characteristics must be attenuation characteristics, and if the signal WEF = 1°, even if the final waveform data is used to generate a sustained tone, the virtual key signal EA
The DG is turned off and a damping envelope characteristic is added to force the musical tone characteristic to be a damping characteristic.

The river waveform data memory section (2104) is connected to the calculation section (210
A register R (OWD) temporarily stores the calculation result of B) using the signal ywaowtD supplied from the sequencer (802), and a register R (OWD) that stores the envelope-added waveform sample value/(X, ,)a-16 for 8 channels. Bit+, m, n, q.

×8 word memory M (OWD) and memory M (OW
D) output data to WB by signal R, I) OWD.
It consists of a gate that supplies to Perth. Normally, the memory M (OWD) is in the read state, and the channel code (CH) supplied from the sequencer (802) is
The envelope-added waveform sample value of address t based on CIζ is supplied to the above-mentioned gate. Then, signal W
The RRAM keeps the memory M (OWD) in a write state, and the data stored in the register R (OWD) is written into the memory M (OWD).

The ED memory unit (2104) has registers I((EDL), E(;(
EDU), memory M (EDL) that stores envelope data ED for 8 channels, output data of M (EDU) and memory M (EDL) is supplied by signal FLD E D L. The memory M (EDL) consists of 16 bits x 8 words, 16 bits x 8 words, Memory M (
EDU) is one normal memory M(ED
L) and M (EDU) are in the read state, and the envelope data ED of the address based on the channel code CHC& is read out and supplied to the above-mentioned gates L1 and M (EDU), respectively. is supplied to the multiplier section (2106), and the signal EDL is supplied to the shifter section (2107).

Then, by the signal WRRAM, the memory M (EDL),
M (EDU) enters the write state and registers R, (E
, DL) and 几(BDU) are written to the memories M(EDL) and M(EDU).

The multiplication unit (2106) converts the waveform data into signals WB and MLP.
When the signal 8ELWB is '0', the coefficient data MLP supplied from the DRP (808) is temporarily stored in the register R (MLPI), and the coefficient data MLP supplied from the DRP (808) is temporarily stored.
=@l", the register R (MLP2) that temporarily stores the envelope data EDL supplied from the BD memory unit (2105) and the register I'(, (MLP 1 )
A 16-bit x 16-bit = 32-bit multiplier whose multiplicand (two's complement representation) is the data stored in register R (MLP 2 ) and a multiplier (absolute value representation), and a signal It is composed of gates that supply the WB bus to the upper 16 pits of the multiplication result of the multiplier using R and DMLP.

The shifter section (2107) supplies the operation result of the -1 operation section (2108) with the signal WR8FT to the register R (SFT) for storing JI, and the data stored in the register R (SFT) from the ED memory section (2105). Shift operation 1 ((8
FT).

(--, q20, 1, 2..., 2' -1) q shifter and register R (SFA) that temporarily stores the chic output data by signal WR8FA.
It consists of a gate A which supplies the data stored in the register RC8FA by the SFA to the WA bus, and a gate B which directly supplies shifter data to the WB bus by signals R and DSFB.

FIG. 24 is a block diagram showing a specific example of the calculation section (2108). (2401) is an inverting gate that inverts the data on the Wi bus with the signal Nv, (2402) is the inverted data latch AL that temporarily stores the output data of (2401) at the falling edge of the signal φ2, and the signal WCRAL
The storage state is (oooO)t. , that is, it is reset. (240B) is a latch BL that temporarily stores data on the WB bus at the falling edge of signal φ2.
, (2404) is 1 with carry input and carry output.
The 6-pit adder (FA), (2405) is FA (2
The carry flag registers E and CF (2406), which store the carry output of (2404) by the signal WREDL and reset by the signal RDEDL, are AND gates (2406).
0? ) is the OEL gate, (2408) is the gate A that supplies the output data of F'A (2404) to the WA bus by the signal WTCA, (2409) is the gate B that supplies data (FFFF)so to the WC bus, (241
0) supplies data on the WB bus to the WC bus. Gate C1 (2411) supplies the output data of F A (2404) to the WC bus. D, (2412) supplies data (0000) ta to the WC bus. Supply gate E
, (2418) are signals TBC1 signal WREI)U, signals WR, EDL, signals EADG and F, A (24
Gate B based on the output signal (pit position 4) of 04)
(2409) to gate E (2412).

The gates selected by the gate selector (2418) will be explained. Gate C (2410) is selected by signal TBC supplied from sequencer (802), and WC
Data on the WB bus is supplied to the bus.

When the virtual key signal BADG supplied from the ΔED generation unit (2108) is in the on state, the gate B (2412) is activated by the signal WREDL or the signals WR and EDU.
is selected, and data (0000) 1e is supplied to the WC bus. That is, envelope data EDU.

Both EDLs will be set to -(0000)16.

As a result, the envelope added waveform sample value △' (Xi, m, n, q, r) =/ (Xi, m, n
).

-Also, the output signal of FA (2404) (pit position 4)
is 111 and signal Wl (data when EDU is supplied)
B (2409) is selected and the data (FF
'FF)1. is supplied. That is, the envelope data EDU is always set to (F)IQ.

In states other than the above, D (2411) is selected and the output data of F A (2404) is supplied to the WC bus.

Note that the signal WRRAN supplied to the river waveform data memory section (2105) and the ED memory section (2106) is the same as the signal WRRAM explained in connection with the DRP (808).

WD P (807) also D RP (808), F
Similar to the D P (806), it performs the following arithmetic processing based on the control signal supplied from the sequencer (802), thereby realizing the processing contents of (1) to (4) described above.

■Find the virtual waveform sample value/(X, , m, n).

The waveform sample values /(X,,n) and f(X+++
, n) are supplied to WA Babas, WB Babas, and the arithmetic unit (21
The waveform sample value is stored in the latches AL and BL of 08) at the falling edge of the signal φ2.

At this time, the data stored in the launch AL by the signal INV applied to the arithmetic unit (2108) becomes inverted data, that is, /(X,, n).

And latch A L (24o2), latch B L
(2408) using the data stored in the calculation unit (21
08) performs addition processing (/ (X4, rl) + / (X
1+t, n) +1] That is, (/(X, ,,
n)−/(X,, n)) is executed, the operation result is output to the WC path, and the multiplication unit (210
It is written to the multiplicand register R (MLP 1) in DRP (80
8) is stored in the multiplication number register R (MLP2).

Then, in the multiplier (2106), (J(Xt++, n) /(Xi, n):)X(Nm
+n) Multiplication of α is performed. The 0 multiplication result shall be the correct value by the end of instruction step 4. The 0th order signal R
DWDI D, L: Rectangle #Full value/(X4,1
1) The multiplication result is supplied to the WA bus by the signal RDMLP, and the respective data are stored in the latches AL and BL at the falling edge of the signal φ2 (corresponding to instruction step 5). Note that the multiplication result uses the upper 16 bits of the multiplier. This nine is 1/2. This is equivalent to +6 processing.

The multiplication unit (2108) executes the addition process,
Virtual waveform sample value f(X+, m,
n) is required.

■Envelope added waveform sample value f(Xi, rtl,
n21. Find r).

The virtual waveform sample value/(X, , , , n) is the signal WR
MLP, the signal W5FT (corresponding to instruction step 6) causes the multiplicand register R (ML
P 1 ) and register R (S
FT) at the rising edge of the signal≠2. Also, H
A signal 5ELWE is applied to the envelope data EDL- supplied from the D memory section (2105) to the multiplication section (2106).
(corresponding to instruction step 6) Niyotte multiplication unit (2106
) and executes multiplication processing D(Xi, m, n)Xr).

On the other hand, register R (SFT,
)/(X,,rn,n)
from the ED memory section (2105) to the shifter section (2107)
Shift operation D(XI, t, 1.n)/2q) is performed based on envelope data EDU(Q) supplied to output register R(SF
B).

Then, the multiplication result performed in the multiplication unit (2106) is transferred to the register R (8FT) in the thick unit (2107) using the signal TBC and the signal W8FT (corresponding to instruction step 8).
The shift operation material is stored based on the envelope data EDU(Q).

Signal [) SFA, RDSFB (Instruction 7. Tare
)9 d correspondence), the output register 1? in the thick section (2107) is output. , (SFB) and the data (t
(x, , m, n)/2q) is calculated m (2108)
Inside (7) Rough f B L D, shifter section (210'
r) The logic is inverted by the signal INV, and the arithmetic unit (2108
) are respectively stored in latches AL.

Then, by performing addition processing in the arithmetic unit (2108), the envelope added waveform sample value, ・′/ (
Xi, m, n, q, r) are melaryl.

■Difference waveform sample value D 7 (x,, r, l, n, 1
．． ”

The old waveform memory section (2104) is output by the signal W OWD.
At the same time, the output data is stored in the register R (OWD) in the arithmetic unit (2108), and the output data is supplied to the WA bus by the signal TCA (FA (2404)). do. Further, in response to the signal RDOWD, the old envelope added waveform sample value is read from the old waveform memory unit (2104) and stored in the latch BL in the calculation unit (2108).

Then, by executing the addition process in the calculation unit (2108), the difference waveform sample value D f, (XI, m, ny
Qrr) is determined, and 0RR(
The difference waveform sample value is stored in register R (OBR) in 2109).

■Update of envelope data ED.

Signals RDEDL, RD, ED (corresponding to instruction step 3)
As a result, the envelope data ED and the ΔED% raw part (21o8) empty incremental data ΔED are read out to the WA bus W'B bus from the ED memory section (2105), and the arithmetic operation section ( 2108) in latches AL and BL, respectively.

Then, the addition process (ED, L+ΔED) is performed by the calculation unit (21
08) to obtain new envelope data E'D,
By signal WRJEDL (corresponding to instruction step 4),
(7) L/Register (ED) in ED memory section (2105)
L) Stores the new envelope data E'D and adds the adder FA (2404) in the arithmetic unit (2108).
(7) In the carry calculation section (2108) (7)
7 L f L/ Shifter ECF (2405) Store.

The envelope data ED'[J is read out by kfRDEDU (corresponding to instruction step 6) and is sent to the arithmetic unit (2).
108) te, register ECF' (2405) (7
) The contents and the envelope data EDU are added to obtain the new second and second half data BDTJ. The obtained envelope EDU is sent to E by the signal WREDU.
It is stored in register R (EDU) in D memory section (2105).

Then, similar to DI(P (808)), the signal VIRA
Yacht teleshifter R (EDL), R (EDU), R to M
(OWD) D. Transfers the stored various data to each memory area specified by the channel code CHC.

Analog huffer memory section (812), DAC (811)
) Explains the timing of supplying data to .

The write pulse generated by the write pulse generator (2110) is reset by the signal CRI)AS (corresponding to instruction step 9). And the signal WROBR
OBB by (corresponding to instruction step 11).

(2109) Inside (7) L/ Shifter R, (OBR)
Difference waveform sample value D / (X,, m, n, 4.r)
The DAC (811) i2m converts the digital signal into an analog signal and supplies it to the analog buffer memory section (812). The writing bus corresponding to the set port and the analog switches AWL to AW8i in the analog sofa memo 13 (812) are supplied. At this time, the signal CLR
If F is 0゛ (when no calculation request is made),
Avoid setting the write bus.

Table 18 shows the calculation sequence of WD P (807).

By sequentially executing the instruction steps shown in Table 18, the processing described above is realized.

The control signals shown in Table 13 will be explained.

The signals mentioned above are provided by the sequencer (802).

RDWDI is the waveform data WDlf supplied from the DRP (808): a command to be supplied to the WA bus.

RDWDI is an instruction to supply the waveform data WDI supplied from the DRP (80B) to the WB bus.

RDΔED is a command to supply the sustain data D, SO8 or damper data DUMP selected in the ΔED generation unit (2108) to the WA bus as incremental data ΔED.・RDSFA is the output data of the shifter in the shifter unit (2107). An instruction to supply WA Babas.

RDEDL is the memory M in the ED memory section (2105)
A command to supply the envelope data EDL read from (EDL) to the WB bus.

RDMLP is an instruction to supply the output data (upper 16 bits) of the multiplier in the multiplication unit (2106) to the WB bus.

RDEDU is the memory M in the ED memory unit (2105)
A command to supply the envelope data BDU read from (EDU) to the WB bus.

RD8FB is the register R (in the shifter section (2107)).
An instruction to supply data (f (X(, m, In)/2q) stored in SFB) to the WB bus.

fLD OWD is a command to supply the envelope added waveform sample value read from memory M (OWD) in the river waveform memory unit (2104) to the W B bus.

WFLMLP converts the data on the WC bus into a multiplication unit (210
6) Instruction to store in multiplicand register R (MLP 1 ).

WREDL stores data on the WC bus in the ED memory section (2
105) instruction to store in register R, (EDL).

WR8FT transfers data on the WC bus to a shifter section (210
7) Instruction to store in register R (8FT).

WREDU transfers the data on the wc bus to the ED memory section (2
105) to be stored in register R (EDU).

WROWD is an instruction to store data on the WC bus in register R (OWD) in the old waveform data memory section (2104).

WB and OBR transfer data on the WC bus to OBR (21
Instruction to store in register R (OWR) in 09).

INV inverts the logic of the data on the WA bus and stores the inverted data in the latch A L (2
402).

WADDI is F' A (2
The instruction register WCRAL that supplies the carry input signal (+1) to the latch AL (
2402) - 8ELWE is the instruction to clear the multiplier register R in the multiplication section (2106).
The data selection command zero selection data stored in (MLP2) includes coefficient data (MLP) supplied from DRP (808) and envelope data EDL''T: supplied from ED memory section (2105).

WR8FB transfers the output data of the shifter in the shifter section (2107)' to the register R(S) in the thick section (2107).
Instruction to store in FB).

'I:, , BC is an instruction to supply data on the WB bus to the wc bus.

CRDAS is a command to reset the write pulse supplied from the write pulse generator (2110) to the analog buffer memory unit (812).

TCA is the calculation unit (2108)
An instruction to supply the output data of 04) to the WA bus.

Note that when the virtual key signal EADG shown in Table 12 is in the on state, the gate selection (241
Data) B (2412) is selected by 8), and both envelope data EDL and EDU are data (00
00) ss. As a result, when the envelope added waveform sample and the virtual key signal EADG turn off, the envelope data HD is updated (ED=BD+
△ED) starts. As a result, arithmetic processing is performed to obtain the envelope-added waveform sample value shown in equation (5), and a musical sound waveform with a damping characteristic is obtained.

Further, when the update processing of the envelope data ED progresses and the envelope data EDU reaches the state (1111)t, the update timing of the envelope data EDU is updated (data in the update timing calculation unit (2108)) B (2409).
is selected, and the eight envelope data EDU is always in the state (1111)2. This state corresponds to the stop of sound generation of the musical sound waveform.

As mentioned above, since the waveform interpolation method is realized using the interpolation coefficient (Nm + n) α/HN with a correction term added as shown in equation (2), the level difference between the waveforms is large. It is possible to prevent the generation of unnecessary noise components.

Further, in areas where the waveform shape changes little, data compression becomes possible by reducing the amount of waveform data stored in the data memory section and increasing the number of repetitions.

Furthermore, one converter (DD
Since it consists of an AC and an analog buffer memory section, only one DAC is required, and each channel operates independently, so even if two channels of sound are played simultaneously, there is no cross-modulation distortion due to quantization distortion. No more outbreaks.

Furthermore, since the sampling frequency is an integer multiple of the fundamental frequency of the waveform, all aliasing components and sample wave components generated due to quantization can be matched to harmonics of the fundamental frequency. , it is possible to create the same clear sound as before.

Next, the interrelationships between the various parts within the musical tone generating section (607) will be explained.

First, the input register section (808) will be explained.

The input controller (GOA) has registers I (, (ADD), DAT) that temporarily store I10 port address data, musical tone generation data, sustain data, etc. supplied from the CPU (608), and the CPU (608).
Flag registers (registers WBC, F 11') and the address stored in register R (ADD) as the write address and the sequencer (
A register file (stores musical tone generation data for 8 channels, has a capacity of 8 bits x 8 words) and stores the musical tone generation data stored in register R (DAT). (1) and an effect register section that stores sustain data, damper data, beat data, and effect control data based on the address data of register R (ADD).

The timing for transferring new data stored in register R (DAT) to the register file or effect register section is when register WRCF is in the state of "1" and signal WRDAT is supplied from the sequencer (802). The data stored in register R (DAT) is transferred to a predetermined address based on the I10 port address stored in (ADD). After that, register WRCF is reset.

The signal WRDAT supplied from the sequencer (802) is a data acquisition control signal to the register file or effect register section, and corresponds to the timing of instruction step 1 shown in Tables 9, 11, and 13. The signal is then supplied to the input register section (808).

The reason for inputting new data into the register file or effect register section at the timing of instruction step 1 is El)
P (806), WDP (807), DB, p (8
08) If the musical tone generation data or various effect data changes while various arithmetic processing is being executed within the .08), the correct arithmetic processing will not be performed.
I'll take it in.

Explanation of mutual relationships An explanation corresponding to channel 1 will be given. It is assumed that the calculation request flag signal CCRF is generated.

■When the channel code CHC generated by the sequencer (802) reaches the timing of channel 1, the musical tone generation data corresponding to channel 1 is transferred from the register file in the input register section (808) to FDP (806) and WDP.
(807) and is supplied to the DRP (808).

■Then, as mentioned in the detailed explanation of D RP (808), D RP (808) transfers the starting address, control data, and waveform data f(Xl) from DBI ((606) to , n) and /(X, +,, n
) is read, and the coefficient data (Nm+n) α obtained based on the control data and the waveform data f('X, , n) and / (X, +, , n) read from the DBK (606) are sent to the command step. DB, P at the timing of 11 (808
), memory M (MD), memory M (WD)), and memory M (WJ).

■On the other hand, WDP (807) f is the instruction step 1~
During the 1° timing, coefficient data and waveforms are read from memory M (MD), memory M, (WDI), and memory M (WDI) in Di(, P (808)) based on channel code CHC. Data f(X,, n-1) and /
wDP (807
) (7) Detailed fM As described in the fx description, waveform calculation processing is performed. Then, at the timing of instruction step 11, the calculation result (difference waveform sample value DR(O
BR) 2 storage area, DAC (811) 2 supply area.

The above-described processes (1) to (2) are executed within the same timing of instruction steps 1 to 11 corresponding to channel 1 of channel code CHC generated from the sequencer (802).

(-, then re-enter the channel code corresponding to channel 1)
When CHC is generated from the sequencer (802), the
.

The processing described above is performed.

■Similar to the explanation of ■ above, the musical tone generation data corresponding to channel 1 is transmitted to FDP (806), WD P (807)
), DRP (808) 2-supplied rel.

■Similar to the explanation of ■ above, in DRP (808), DB
The starting address, control data, and waveform data f (Xi, n+s), / (
X++, m+ n) is read and memory M (MD
), Memory M (WDI), Memo IJ M (WDII)
2 is stored.

However, the difference from the content explained in section ■ above is that DBK (
The control data and waveform data read from 606) are data based on the waveform number i and waveform sample number n updated at the timing (2) above, that is, the previous channel 1 calculation timing.

■Similar to the above ■, memory M (M
,D) 1. lMo IJ M (WDI), Memo IJ M
Waveform calculation processing is performed based on the data read out from (WDI).

Note that the data used for waveform calculation processing at the current calculation timing is the data used for the DRP calculation at the previous channel 1 calculation timing.
Coefficient data and waveform data/(X, , n) that were read in (808).

f(X1+2.n).

Thereafter, the above process is repeated at the calculation timing corresponding to channel 1 based on the calculation request flag signal CLRF.

As explained above, the data read by the DRP (808) is sent to the WD at the next calculation timing (when the 1 calculation request flag signal CLRF is generated).
It is used for waveform calculation processing performed in P (807).

In this way, the operation speed of the components of each part can be increased by dividing the processing time and timing and performing pipeline processing, rather than executing all the readout and waveform calculation processing within the same calculation timing. Can be slowed down.

'In the explanation in A-i above, the waveform data stored in the data memory (DBK) was in the form of PCM data and stored the number of waveform cycles, but waveform symmetry, DPCM conversion,
The result of converting to ADPCM is sent to DDK as waveform data.
By storing the waveform data in the DRP (808) and performing restoration processing within the DRP (808), data compression of the waveform data becomes possible.

As described in detail, the musical tone generating device of the present invention has a waveform that stores at least two or more musical sound waveforms from among a plurality of musical sound waveforms from the start of musical tone generation to the end of musical tone generation in the form of digital values. a memory, a note clock generation section that determines a tone scale, a waveform readout section that reads out two waveform sample data from the waveform memory based on the output signal of the note-clock generation section, and two waveform sample data read out by the waveform readout section. a waveform calculation unit that forms an f-tone waveform using two waveform sample data, and a conversion unit that converts the digital output signal of the waveform calculation unit into an analog signal; Using 1, DRP (808)
Waveform sample data read out/(X,, n) and f(
Xi+1. n), the virtual sample value/(X, , m
, n), the shape of the musical waveform can be changed over time, making it possible to simulate natural musical instrument sounds and preventing discontinuities that occur at waveform joints.

Furthermore, the interpolation coefficient (Nm+n)/MN is (Nm+n)
Replacing tt/h/IRa and making the MNα term a power of 2 has the advantage that the calculation contents of equation (2) can be simplified and waveform generation by waveform interpolation can be easily realized.

[Brief explanation of the drawing]

1 to 5 are explanatory diagrams of the operation of the present invention, FIG. 6 is a block diagram of an electronic musical instrument employing the musical tone generating device of the present invention, and FIG.
The figure shows a time chart when data is supplied from the CPU (608) to the musical tone generating section (607), FIG. 8 is a configuration diagram of the musical tone generating section (607), and FIG. 9 shows the sequencer (80
2) - A block diagram of a specific example, Figure 10 is a sequencer (
802), and FIG. 11 is a configuration diagram of a concrete example of the analog buffer memory section (812).
Figure 2 is an internal operation time chart of the musical tone generator (607), Figure 18 is a transition diagram of frequency data supplied from the FDP (soe) to the comparison register unit (805), and Figure 14 is a diagram of the - of the FDP (806). A configuration diagram of a specific example, FIG. 15 is a processing flowchart showing the data processing procedure of the FDP (806), FIG. 16 is a configuration diagram of a specific example of the comparison register section (805), and FIG. 17 is a calculation request flag generation Department (810)
- A configuration diagram showing a specific example, Fig. 18 is a DBK (606)
(7) Data configuration diagram, Figure 19 is DB, P (808)
(7) - A configuration diagram showing a specific example, Figure 20 is a WDP
(807) flowchart, Figure 21 is a flowchart of the arithmetic processing of WDP (807).
22 is a block diagram showing a specific example of the vibrato generating section (1408), FIG. 28 is a block diagram showing a specific example of the calculation section (1918), and FIG.
The figure is a configuration diagram showing a specific example of the calculation unit (2108). (601)...Keyboard section, (602)...Operation section, (
608)...Central processing unit, (604)...RAM
, (605)...ROM, (606)...musical tone synthesis data R, OM, (607)...musical tone generator, (8
01)...Main oscillator, (802)...Sequencer,
(81) 8)...Input register section, (804)...
Timer, (805)... Comparison register section, (806
) Frequency data processor, (807) Waveform data processor, (808) Data read processor, (809) Read pulse forming unit, (
810)...Calculation request flag generation unit, (811)...
・DAC,, (812)...Analog buffer memory section, (818)...Integrator agent Yoshihiro Morimoto Figure 1

Claims (1)

[Claims] 1. A waveform memory that stores at least two or more musical sound waveforms out of a plurality of musical sound waveforms from the start of sound generation to the end of sound generation in the form of digital values, and a note that determines the sounding scale. A clock i generation section, a waveform reading section that reads out two waveform sample data from the waveform memory based on the output signal of the note clock generation section, and a musical waveform using the two waveform sample data read out by the waveform reading section. and a conversion section that converts the digital output signal of the waveform calculation section into an analog signal, and the calculation content executed by the waveform calculation section is based on the two waveforms read out by the waveform reading section. Sample data/(
Xi, n), /(Xi+s, n), perform the waveform interpolation calculation shown in the following formula, and obtain the virtual waveform sample value / (X,
, ff, , n). fCX, , m, n) - (/(X, , , n) - fc
X, , n)) (Nm+n) x MN+f(X, ) i=0.1.2. ... f-1 waveform number m = 0
．． 1.2. ...M-1<return number n=0.
1, 2. ...N-1 number of waveform samples 2, interpolation coefficient (Nm+n) A4 for calculation to obtain virtual sample value
A musical tone according to claim 1, in which N is replaced with (Nm+n)a/MNa, the MNσ term is set to a power of 2, and the specified data is controlled by the number of samples of the 18th period of the waveform because the incremental data α is repeated. Generator.